WO2012165599A1

WO2012165599A1 - Level shift circuit

Info

Publication number: WO2012165599A1
Application number: PCT/JP2012/064226
Authority: WO
Inventors: 智裕根塚
Original assignee: ザインエレクトロニクス株式会社
Priority date: 2011-05-31
Filing date: 2012-05-31
Publication date: 2012-12-06
Also published as: JP2012249261A; TW201315151A

Abstract

A level shift circuit (2A) comprises: a first PMOS transistor (31); a second PMOS transistor (32); a first NMOS transistor (41); a second NMOS transistor (42); a third NMOS transistor (43); and a fourth NMOS transistor (44). The respective source terminals of the first PMOS transistor (31) and the second PMOS transistor (32) are connected to a second reference potential (Vddh) which is higher than a first reference potential (Vddl). The respective drain terminals of the third NMOS transistor (43) and the fourth NMOS transistor (44) are also connected to the second reference potential (Vddh). It is possible to provide a level shift circuit with which greater power consumption reduction and improved speed are possible.

Description

Level shift circuit

The present invention relates to a level shift circuit.

The level shift circuit plays a role of bypassing a system that processes signals with a low voltage and a system that processes signals with a high voltage. This level shift circuit is used in a signal processing system of a semiconductor integrated circuit and contributes to power saving. In general, the level shift circuit receives a first input signal and a second input signal which are complementary to each other and are output from a circuit which operates by being supplied with the first reference potential Vddl and the third reference potential Vss. Generating a first output signal and a second output signal complementary to each other having a high level voltage value greater than a high level voltage value of the signal and the second input signal, and the first output signal and the second output signal Both or one of them is output to a circuit that operates by being supplied with the second reference potential Vddh and the third reference potential Vss. However, Vddh> Vddl> Vss.

Here, when one of the first input signal and the second input signal is at a high level, the other is at a low level. Similarly, when one of the first output signal and the second output signal is at a high level, the other is at a low level. The change of the high level / low level of the first output signal and the second output signal is the same as the change of the high level / low level of the first input signal and the second input signal.

For example, when the CPU core is driven with a power supply voltage of 1.8 V and the peripheral circuit for the CPU is driven with a power supply voltage of 3.3 V, the level shift circuit outputs the high level of the signal output from the CPU core. Is converted from 1.8 V to 3.3 V, and the level-converted signal is output to the peripheral circuit.

A circuit disclosed in Patent Document 1 is known as such a level shift circuit. The level shift circuit disclosed in this document includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor as a basic configuration. The first PMOS transistor and the first NMOS transistor are sequentially connected in series between the second reference potential Vddh and the third reference potential Vss, and the drain terminal of the first PMOS transistor and the drain terminal of the first NMOS transistor are connected to each other. The connection point is connected to each other as a second output terminal, and a second output signal is output from the second output terminal. The second PMOS transistor and the second NMOS transistor are provided in series and sequentially connected between the second reference potential Vddh and the third reference potential Vss. The drain terminal of the second PMOS transistor and the drain terminal of the second NMOS transistor Are connected to each other as a first output terminal, and a first output signal is output from the first output terminal.

The level shift circuit disclosed in Patent Document 1 includes a third NMOS transistor and a fourth NMOS transistor in addition to the above basic configuration. The third NMOS transistor is provided between the first reference potential Vddl and the second output terminal, and the fourth NMOS transistor is provided between the first reference potential Vddl and the first output terminal. The level shift circuit disclosed in Patent Document 1 includes the third NMOS transistor and the fourth NMOS transistor, thereby reducing power consumption and speed.

JP 11-136120 A

However, the present inventor has found that a level shift circuit including the third NMOS transistor and the fourth NMOS transistor as described above in addition to the basic configuration does not necessarily reduce power consumption and increase speed as expected. It was.

The present invention was made to solve the above problems based on the knowledge of the present inventor, and an object thereof is to provide a level shift circuit capable of further reducing power consumption and improving speed. To do.

The level shift circuit according to the present invention receives a first input signal and a second input signal which are complementary to each other and are output from a circuit which is supplied with the first reference potential Vddl and the third reference potential Vss and operates. The first output signal and the second output signal are generated by generating complementary first output signals and second output signals having high level voltage values greater than the high level voltage values of the input signal and the second input signal. Is a level shift circuit that outputs either or both of them to a circuit that operates by being supplied with the second reference potential Vddh and the third reference potential Vss. However, Vddh> Vddl> Vss.

The level shift circuit of the present invention includes (1) a first input terminal to which a first input signal is input, (2) a second input terminal to which a second input signal is input, and (3) a first output signal. A first node that appears, (4) a second node where a second output signal appears, (5) a source terminal to which a second reference potential Vddh is input, a drain terminal connected to the second node, and a first node A first PMOS transistor having a gate terminal connected to the gate, (6) a source terminal to which the second reference potential Vddh is input, a drain terminal connected to the first node, and a gate terminal connected to the second node A first PMOS having (7) a source terminal to which the third reference potential Vss is input, a drain terminal connected to the second node, and a gate terminal connected to the first input terminal. Transistor, (8) third reference potential Vss A second NMOS transistor having an input source terminal, a drain terminal connected to the first node, and a gate terminal connected to the second input terminal; and (9) a drain terminal to which the second reference potential Vddh is input. A third NMOS transistor having a source terminal connected to the second node and a gate terminal connected to the second input terminal, (10) a drain terminal to which the second reference potential Vddh is input, and a first node And a fourth NMOS transistor having a source terminal connected to the first input terminal and a gate terminal connected to the first input terminal.

The level shift circuit of the present invention may further include a first buffer circuit that outputs a signal obtained by logically inverting the first output signal appearing at the first node from the output terminal. The first buffer circuit includes a buffer PMOS transistor and a buffer NMOS transistor connected in series between the second reference potential Vddh and the third reference potential Vss, and each of the buffer PMOS transistor and the buffer NMOS transistor Preferably, the drain terminal is connected to the output terminal, the first node is connected to the gate terminal of the buffer PMOS transistor, and the first input signal is input to the gate terminal of the buffer NMOS transistor. Alternatively, the first buffer circuit includes a first PMOS transistor for buffer, a second PMOS transistor for buffer, and an NMOS transistor for buffer connected in series between the second reference potential Vddh and the third reference potential Vss, The drain terminal of each of the second PMOS transistor for buffer and the NMOS transistor for buffer is connected to the output terminal, the first node is connected to one of the gate terminals of the first PMOS transistor for buffer and the second PMOS transistor for buffer, and the other It is also preferable that the first input signal is input to the gate terminal and the first input signal is input to the gate terminal of the buffer NMOS transistor. In this case, the level shift circuit of the present invention further includes a first delay circuit that delays the first input signal input to the first buffer circuit with respect to the first input signal input to the gate terminal of the first NMOS transistor. It is also suitable to provide.

The level shift circuit of the present invention may further include a second buffer circuit that outputs a signal obtained by logically inverting the second output signal appearing at the second node from the output terminal. The second buffer circuit includes a buffer PMOS transistor and a buffer NMOS transistor sequentially connected in series between the second reference potential Vddh and the third reference potential Vss, and each of the buffer PMOS transistor and the buffer NMOS transistor The drain terminal is connected to the output terminal, the second node is connected to the gate terminal of the buffer PMOS transistor, and the second input signal is preferably input to the gate terminal of the buffer NMOS transistor. Alternatively, the second buffer circuit includes a buffer first PMOS transistor, a buffer second PMOS transistor, and a buffer NMOS transistor connected in series between the second reference potential Vddh and the third reference potential Vss in order. The drain terminal of each of the second PMOS transistor for buffer and the NMOS transistor for buffer is connected to the output terminal, the second node is connected to one of the gate terminal of the first PMOS transistor for buffer and the second PMOS transistor for buffer, and the other It is also preferable that the second input signal is input to the gate terminal and the second input signal is input to the gate terminal of the buffer NMOS transistor. In this case, the level shift circuit of the present invention further includes a second delay circuit that delays the second input signal input to the second buffer circuit with respect to the second input signal input to the gate terminal of the second NMOS transistor. It is also suitable to provide.

The level shift circuit of the present invention can reduce power consumption and increase speed.

It is a figure which shows the structure of the level shift circuit 1A of a 1st comparative example. It is a figure which shows the structure of the level shift circuit 1B of the 2nd comparative example. It is a figure which shows the structure of the level shift circuit 2A of 1st Embodiment. It is a figure which shows the structure of the level shift circuit 2B of 2nd Embodiment. It is a figure which shows the structure of the level shift circuit 2C of 3rd Embodiment. It is a figure which shows the structure of the level shift circuit 2D of 4th Embodiment. It is a figure which shows the structure of the level shift circuit 2E of 5th Embodiment.

Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted. Also, after first describing the level shift circuit of the comparative example, the level shift circuit of the embodiment will be described.

(First comparative example)

FIG. 1 is a diagram showing a configuration of a level shift circuit 1A of the first comparative example. In this figure, in addition to the level shift circuit 1A, a first input circuit 3 and a second input circuit 4 which are operated by being supplied with the first reference potential Vddl and the third reference potential Vss are also shown. The level shift circuit 1A includes a first input terminal 11, a second input terminal 12, a first output terminal 21, a second output terminal 22, a first PMOS transistor 31, a second PMOS transistor 32, a first NMOS transistor 41, and a second NMOS transistor 42. Prepare.

The level shift circuit 1A receives the complementary first input signal Sip and second input signal Sin output from the

circuits

3 and 4 that operate by being supplied with the first reference potential Vddl and the third reference potential Vss. , 12 are input. The level shift circuit 1A generates a first output signal Sop and a second output signal Son which are complementary to each other and have a high level voltage value larger than the high level voltage value of the first input signal Sip and the second input signal Sin. To do.

Then, the level shift circuit 1A outputs either or both of the first output signal Sop and the second output signal Son to a circuit that operates by being supplied with the second reference potential Vddh and the third reference potential Vss. , 22. The low level voltage values of the first output signal Sop and the second output signal Son are equal to the low level voltage values of the first input signal Sip and the second input signal Sin. However, Vddh> Vddl> Vss.

The first input terminal 11 receives the first input signal Sip output from the first input circuit 3. The second input terminal 12 receives the second input signal Sin output from the second input circuit 4. The first input signal Sip and the second input signal Sin are complementary to each other, and when one is at a high level, the other is at a low level.

The first output terminal 21 outputs the first output signal Sop. The second output terminal 22 receives the second output signal Son. The first output signal Sop and the second output signal Son are complementary to each other, and when one is at a high level, the other is at a low level.

The 1PMOS transistor 31 has a source terminal second reference potential Vddh is input, a drain terminal connected to the second node N _2, and a gate terminal connected to the first node N _1. The 2PMOS transistor 32 has a source terminal second reference potential Vddh is input, a drain terminal connected to the first node N _1, and a gate terminal connected to the second node N _2.

The 1NMOS transistor 41 has a source terminal third reference potential Vss is input, a drain terminal connected to the second node N _2, and a gate terminal connected to the first input terminal 11. The 2NMOS transistor 42 has a source terminal third reference potential Vss is input, a drain terminal connected to the first node N _1, and a gate terminal connected to the second input terminal 12.

The first node N ₁ appears first output signal Sop, first output terminal 21 to the first node N ₁ is connected. The second node N ₂ appears second output signal Son, the second output terminal 22 to the second node N ₂ is connected. That is, the first output terminal 21 can output the first output signal Sop, and the second output terminal 22 can output the second output signal Son.

In the level shift circuit 1A of the first comparative example configured as described above, the first input signal Sip input to the first input terminal 11 is at a high level (Vddl) and is input to the second input terminal 12. When the second input signal Sin is at a low level (Vss), the first NMOS transistor 41 is on and the second NMOS transistor 42 is off. Further, at this time, the first PMOS transistor 31 is in an off state and the second PMOS transistor 32 is in an on state. Therefore, at this time, the first output signal Sop output from the first output terminal 21 is at a high level (Vddh), and the second output signal Son output from the second output terminal 22 is at a low level (Vss). .

Conversely, when the first input signal Sip input to the first input terminal 11 is at a low level (Vss) and the second input signal Sin input to the second input terminal 12 is at a high level (Vddl). The first NMOS transistor 41 is in an off state, and the second NMOS transistor 42 is in an on state. Further, at this time, the first PMOS transistor 31 is in an on state and the second PMOS transistor 32 is in an off state. Accordingly, at this time, the first output signal Sop output from the first output terminal 21 is at a low level (Vss), and the second output signal Son output from the second output terminal 22 is at a high level (Vddh). .

However, the high level / low level change timings of the first output signal Sop and the second output signal Son are delayed from the high level / low level change timings of the first input signal Sip and the second input signal Sin. Further, the change from the low level to the high level of each of the first output signal Sop and the second output signal Son is slower than the change from the high level to the low level. The cause of this phenomenon is as follows.

The

NMOS transistors

41 and 42 are directly driven by the input signals Sip and Son to cause an on / off state change, whereas the

PMOS transistors

31 and 32 change the potential of the drain terminals of the

NMOS transistors

41 and 42. In response, an on / off state change occurs. Therefore, there is a period in which both the first PMOS transistor 31 and the first NMOS transistor 41 are simultaneously turned on when the first input signal Sip changes from the low level to the high level. During this period, a through current flows through the first PMOS transistor 31 and the first NMOS transistor 41 connected in series. This through current causes an increase in power consumption. Since there is a parasitic capacitance at the connection point (second node N ₂ ) between the drain terminal of the first PMOS transistor 31 and the drain terminal of the first NMOS transistor 41, the parasitic capacitance is charged by passing through current, which increases the speed. It becomes a factor to prevent. Even when the second input signal Sin changes from the low level to the high level, there is a period in which both the second PMOS transistor 32 and the second NMOS transistor 42 are turned on at the same time. Therefore, the same phenomenon as described above occurs.

Thus, the level shift circuit 1A of the first comparative example has a problem that power consumption is large and it is difficult to improve the speed. As a configuration for solving such a problem, a configuration of a level shift circuit 1B of a second comparative example described below can be considered.

(Second comparative example)

FIG. 2 is a diagram showing a configuration of the level shift circuit 1B of the second comparative example. Compared with the configuration of the level shift circuit 1A of the first comparative example shown in FIG. 1, the level shift circuit 1B of the second comparative example shown in FIG. 2 further includes a third NMOS transistor 43 and a fourth NMOS transistor 44. It is different in point.

The 3NMOS transistor 43 has a drain terminal that first reference potential Vddl is input, a source terminal connected to the second node N _2, and a gate terminal connected to the second input terminal 12. The 4NMOS transistor 44 has a drain terminal first reference potential Vddl is input, a source terminal connected to the first node N _1, and a gate terminal connected to the first input terminal 11.

Level shifting circuit 1B of the thus constituted second comparative example, when the first input signal Sip is changed from the low level to the high level, the 4NMOS transistor 44 is turned on, the first node N ₁ i.e. the The first output signal Sop appearing at the 1 output terminal 21 becomes high level. At this time, the first NMOS transistor 41 is turned on, the potential of the drain terminal of the first PMOS transistor 31 is lowered, and the fourth NMOS transistor 44 is also turned on, and the potential of the gate terminal of the first PMOS transistor 31 is turned on. because increases, the 1PMOS transistor 31 is turned off, the first output signal Son appearing at second node N _2, that is, the second output terminal 22 becomes a low level. Note that the fourth NMOS transistor 44 is turned off because the potential between the gate terminal and the source terminal becomes lower than the threshold voltage as the potential of the source terminal increases. The same applies when the second input signal Sin changes from low level to high level.

As described above, the level shift circuit 1B of the second comparative example includes the

NMOS transistors

43 and 44 that are directly driven by the input signals Sip and Son, so that the first PMOS transistor 31 and the first NMOS transistor connected in series are connected. The period during which both 41 are turned on simultaneously is shortened, and the period during which both the second PMOS transistor 32 and the second NMOS transistor 42 connected in series are simultaneously turned on is shortened. Therefore, compared with the level shift circuit 1A of the first comparative example, the level shift circuit 1B of the second comparative example can improve the speed and reduce the power consumption.

However, even with the configuration of the level shift circuit 1B of the second comparative example, power consumption reduction and speed improvement are not sufficient. The level shift circuits 2A to 2E of the embodiments described below can further reduce power consumption and speed.

(First embodiment)

FIG. 3 is a diagram illustrating a configuration of the level shift circuit 2A according to the first embodiment. Compared with the level shift circuit 1B of the second comparative example shown in FIG. 2, the level shift circuit 2A of the first embodiment shown in FIG. 3 is connected to the drain terminals of the third NMOS transistor 43 and the fourth NMOS transistor 44, respectively. It differs in terms of the input potential.

That is, in the level shift circuit 1B of the second comparative example, the potential input to the drain terminals of the

NMOS transistors

43 and 44 is supplied to the

first circuits

3 and 4 connected to the

input terminals

11 and 12, respectively. The potential was Vddl. On the other hand, in the level shift circuit 2A of the first embodiment, the potential input to the drain terminals of the

NMOS transistors

43, 44 is supplied to the second stage circuit connected to the

output terminals

21, 22. The potential is Vddh.

The level shift circuit 2A of the first embodiment can operate in substantially the same manner as the level shift circuit 1B of the second comparative example. However, in the level shift circuit 2A of the first embodiment, since the second reference potential Vddh higher than the first reference potential Vddl is input to the drain terminals of the

NMOS transistors

43 and 44, the

NMOS transistors

43 and 44 are turned on. Large amount of current. Since the

NMOS transistors

43 and 44 can drive the output voltage directly to the high level and the gates of the

PMOS transistors

31 and 32 can be driven to the second reference potential Vddh, the through current can be reduced. Therefore, as compared with the level shift circuit 1B of the second comparative example, the level shift circuit 2A of the first embodiment can further reduce power consumption and increase the speed.

(Second embodiment)

FIG. 4 is a diagram showing a configuration of the level shift circuit 2B of the second embodiment. Compared with the level shift circuit 2A of the first embodiment shown in FIG. 3, the level shift circuit 2B of the second embodiment shown in FIG. 4 further includes a first buffer circuit 50B and a second buffer circuit 60B. It is different in point.

The first buffer circuit 50B outputs a logical inversion signal Sop # the first output signal Sop appearing at first node N ₁ from the first output terminal 21. The first buffer circuit 50B includes a PMOS transistor 51 and an NMOS transistor 53 that are sequentially connected in series between the second reference potential Vddh and the third reference potential Vss. The drain terminals of the PMOS transistor 51 and the NMOS transistor 53 are connected to the first output terminal 21. The first node N ₁ is connected to the gate terminal of the PMOS transistor 51. The first input signal Sip is input to the gate terminal of the NMOS transistor 53.

The second buffer circuit 60B outputs a logical inversion signal Son # a second output signal Son appearing at second node N ₂ from the second output terminal 22. The second buffer circuit 60B includes a PMOS transistor 61 and an NMOS transistor 63 that are sequentially connected in series between the second reference potential Vddh and the third reference potential Vss. The drain terminals of the PMOS transistor 61 and the NMOS transistor 63 are connected to the second output terminal 22. The second node N ₂ is connected to the gate terminal of the PMOS transistor 61. The second input signal Sin is input to the gate terminal of the NMOS transistor 63.

In the present embodiment, the first buffer circuit 50B substantially has the function of an inverter circuit. However, while the first output signal Sop of the first node N ₁ is inputted to the gate terminal of the PMOS transistor 51, the first input signal Sip is directly input to the gate terminal of the NMOS transistor 53. Thereby, the output of the first buffer circuit 50B can be changed at high speed. The same applies to the second buffer circuit 60B.

Further, in the present embodiment, the first node N is compared with the case where the gate terminals of the PMOS transistor 51 and the NMOS transistor 53 are connected to the first node N ₁ (that is, in the case of the configuration of a normal inverter circuit). since the number of transistors connected to _one decreases, it is possible to change the first node first output signal Sop of N ₁ at high speed. The same applies to the second buffer circuit 60B.

(Third embodiment)

FIG. 5 is a diagram showing the configuration of the level shift circuit 2C of the third embodiment. Compared with the level shift circuit 2B of the second embodiment shown in FIG. 4, the level shift circuit 2C of the third embodiment shown in FIG. 5 replaces the first buffer circuit 50B with the first buffer circuit 50C. The difference is that the second buffer circuit 60C is provided instead of the second buffer circuit 60B.

The first buffer circuit 50C outputs a logical inversion signal Sop # the first output signal Sop appearing at first node N ₁ from the first output terminal 21. The first buffer circuit 50C includes a PMOS transistor 51, a PMOS transistor 52, and an NMOS transistor 53 that are sequentially connected in series between the second reference potential Vddh and the third reference potential Vss. The drain terminals of the PMOS transistor 52 and the NMOS transistor 53 are connected to the first output terminal 21. The first node N ₁ is connected to the gate terminal of the PMOS transistor 51. The first input signal Sip is input to the gate terminal of the PMOS transistor 52. The first input signal Sip is input to the gate terminal of the NMOS transistor 53.

The second buffer circuit 60C outputs a logical inversion signal Son # a second output signal Son appearing at second node N ₂ from the second output terminal 22. The second buffer circuit 60C includes a PMOS transistor 61, a PMOS transistor 62, and an NMOS transistor 63 that are sequentially connected in series between the second reference potential Vddh and the third reference potential Vss. The drain terminals of the PMOS transistor 62 and the NMOS transistor 63 are connected to the second output terminal 22. The second node N ₂ is connected to the gate terminal of the PMOS transistor 61. The second input signal Sin is input to the gate terminal of the PMOS transistor 62. The second input signal Sin is input to the gate terminal of the NMOS transistor 63.

As in the first buffer circuit 50B in the second embodiment, the first buffer circuit 50C also has a function of an inverter circuit in this embodiment. However, compared with the first buffer circuit 50B in the second embodiment, the first buffer circuit 50C in the present embodiment includes a PMOS transistor 52 between the PMOS transistor 51 and the first output terminal 21, and the PMOS transistor 52 The first input signal Sip is directly input to the gate terminals of the NMOS transistor 53 and the NMOS transistor 53.

As in the second buffer circuit 60B in the second embodiment, the second buffer circuit 60C also has a function of an inverter circuit in this embodiment. However, compared with the second buffer circuit 60B in the second embodiment, the second buffer circuit 60C in the present embodiment includes a PMOS transistor 62 provided between the PMOS transistor 61 and the second output terminal 22, and the PMOS transistor 62 The second input signal Sin is directly input to the gate terminals of the NMOS transistor 63 and the NMOS transistor 63.

In the second embodiment, slow state transition of the PMOS transistor 51 when the level transition of the first output signal Sop of the first node N ₁ is slow, because the state transition while the NMOS transistor 53 is fast, the first buffer circuit A through current is generated at 50B. On the other hand, in this embodiment, the PMOS transistor 52 into which the first input signal Sip is directly input to the gate terminal is inserted, so that the through current of the first buffer circuit 50C can be suppressed. The output value of the first buffer circuit 50C can be changed at high speed. The same applies to the second buffer circuit 60C.

(Fourth embodiment)

FIG. 6 is a diagram showing the configuration of the level shift circuit 2D of the fourth embodiment. Compared with the level shift circuit 2C of the third embodiment shown in FIG. 5, the level shift circuit 2D of the fourth embodiment shown in FIG. 6 replaces the first buffer circuit 50C with the first buffer circuit 50D. It is different in that the second buffer circuit 60C is provided instead of the second buffer circuit 60C.

Compared with the first buffer circuit 50C in the third embodiment, the first buffer circuit 50D in the present embodiment is different in that the arrangement of the PMOS transistor 51 and the PMOS transistor 52 is reversed. Compared with the second buffer circuit 60C in the third embodiment, the second buffer circuit 60D in the present embodiment is different in that the arrangement of the PMOS transistor 61 and the PMOS transistor 62 is reversed.

The level shift circuit 2D of the present embodiment operates in the same manner as in the third embodiment. However, in the present embodiment, the first buffer circuit 50D, the gate potential of the PMOS transistor 52 in the second reference potential Vddh side is confirmed quickly among the PMOS transistor 51 and the PMOS transistor 52 is connected to the first node _{N 1} Since the PMOS transistor 51 is close to the first output terminal 21, the output value of the first buffer circuit 50D can be changed at high speed. The same applies to the second buffer circuit 60D.

(Fifth embodiment)

FIG. 7 is a diagram showing the configuration of the level shift circuit 2E of the fifth embodiment. Compared with the level shift circuit 2D of the fourth embodiment shown in FIG. 6, the level shift circuit 2E of the fifth embodiment shown in FIG. 7 further includes a first delay circuit 70 and a second delay circuit 80. It is different in point. The first buffer circuit 50E in the present embodiment has the same configuration as the first buffer circuit 50D in the fourth embodiment. The second buffer circuit 60E in the present embodiment has the same configuration as the second buffer circuit 60D in the fourth embodiment.

The first delay circuit 70 delays the first input signal Sip input to the first buffer circuit 50E with respect to the first input signal Sip input to the gate terminal of the first NMOS transistor 41. The second delay circuit 80 delays the second input signal Sin input to the second buffer circuit 60E with respect to the second input signal Sin input to the gate terminal of the second NMOS transistor 42.

In the fourth embodiment, the level transition of the input signals Sip and Sin input to the

buffer circuits

50D and 60D may be too early. In this embodiment, the

delay circuits

70 and 80 are provided, so that the buffer The timing of the level transition of the input signals Sip and Sin input to the

circuits

50E and 60E is optimized.

(Modification)

The present invention is not limited to the above embodiment, and various modifications are possible. For example, although both the first buffer circuit and the second buffer circuit are provided in the second to fifth embodiments, depending on the configuration of the circuit connected to the subsequent stage of the level shift circuit, the first buffer circuit and the second buffer circuit are provided. Only one of the buffer circuits may be provided. Further, the

delay circuits

70 and 80 provided in the fifth embodiment may be provided also in the second to fourth embodiments.

1A, 1B, 2A to 2E ... level shift circuit, 3 ... first input circuit, 4 ... second input circuit, 11 ... first input terminal, 12 ... second input terminal, 21 ... first output terminal, 22 ... first 2 output terminals 31 ... first PMOS transistor 32 ... second PMOS transistor 41 ... first NMOS transistor 42 ... second NMOS transistor 43 ... third NMOS transistor 44 ... fourth NMOS transistor 50B-50E ... first buffer circuit 60B 60E, second buffer circuit, 70, first delay circuit, 80, second delay circuit, N _1, first node, N _2, second node.

Claims

The first input signal and the second input signal complementary to each other output from the circuit that operates by being supplied with the first reference potential Vddl and the third reference potential Vss are input, and the first input signal and the second input signal are input. Generating a first output signal and a second output signal complementary to each other having a high-level voltage value greater than the high-level voltage value, and the first output signal and / or the second output signal are A level shift circuit for supplying a second reference potential Vddh and a third reference potential Vss to an operating circuit (where Vddh>Vddl>Vss);
A first input terminal to which the first input signal is input;
A second input terminal to which the second input signal is input;
A first node at which the first output signal appears;
A second node at which the second output signal appears;
A first PMOS transistor having a source terminal to which a second reference potential Vddh is input, a drain terminal connected to the second node, and a gate terminal connected to the first node;
A second PMOS transistor having a source terminal to which a second reference potential Vddh is input, a drain terminal connected to the first node, and a gate terminal connected to the second node;
A first NMOS transistor having a source terminal to which a third reference potential Vss is input, a drain terminal connected to the second node, and a gate terminal connected to the first input terminal;
A second NMOS transistor having a source terminal to which a third reference potential Vss is input, a drain terminal connected to the first node, and a gate terminal connected to the second input terminal;
A third NMOS transistor having a drain terminal to which a second reference potential Vddh is input, a source terminal connected to the second node, and a gate terminal connected to the second input terminal;
A fourth NMOS transistor having a drain terminal to which a second reference potential Vddh is input, a source terminal connected to the first node, and a gate terminal connected to the first input terminal;
A level shift circuit comprising:
A first buffer circuit that outputs a signal obtained by logically inverting the first output signal appearing at the first node from an output terminal;
The first buffer circuit includes a buffer PMOS transistor and a buffer NMOS transistor sequentially connected in series between a second reference potential Vddh and a third reference potential Vss;
The drain terminals of the buffer PMOS transistor and the buffer NMOS transistor are connected to the output terminal,
The first node is connected to a gate terminal of the buffer PMOS transistor;
The first input signal is input to a gate terminal of the buffer NMOS transistor;
The level shift circuit according to claim 1.
A first buffer circuit that outputs a signal obtained by logically inverting the first output signal appearing at the first node from an output terminal;
The first buffer circuit includes a first PMOS transistor for buffer, a second PMOS transistor for buffer, and an NMOS transistor for buffer connected in series between a second reference potential Vddh and a third reference potential Vss,
The drain terminals of the buffer second PMOS transistor and the buffer NMOS transistor are connected to the output terminal,
The first node is connected to a gate terminal of one of the first PMOS transistor for buffer and the second PMOS transistor for buffer, and the first input signal is input to the other gate terminal,
The first input signal is input to a gate terminal of the buffer NMOS transistor;
The level shift circuit according to claim 1.
A first delay circuit for delaying the first input signal input to the first buffer circuit with respect to the first input signal input to the gate terminal of the first NMOS transistor;
The level shift circuit according to claim 2 or 3, wherein
A second buffer circuit for outputting a signal obtained by logically inverting the second output signal appearing at the second node from an output terminal;
The second buffer circuit includes a buffer PMOS transistor and a buffer NMOS transistor sequentially connected in series between a second reference potential Vddh and a third reference potential Vss;
The drain terminals of the buffer PMOS transistor and the buffer NMOS transistor are connected to the output terminal,
The second node is connected to a gate terminal of the buffer PMOS transistor;
The second input signal is input to a gate terminal of the buffer NMOS transistor;
The level shift circuit according to any one of claims 1 to 4, wherein:
A second buffer circuit for outputting a signal obtained by logically inverting the second output signal appearing at the second node from an output terminal;
The second buffer circuit includes a first PMOS transistor for buffer, a second PMOS transistor for buffer, and an NMOS transistor for buffer connected in series between a second reference potential Vddh and a third reference potential Vss,
The drain terminals of the buffer second PMOS transistor and the buffer NMOS transistor are connected to the output terminal,
The second node is connected to one gate terminal of the first PMOS transistor for buffer and the second PMOS transistor for buffer, and the second input signal is input to the other gate terminal,
The second input signal is input to a gate terminal of the buffer NMOS transistor;
The level shift circuit according to any one of claims 1 to 4, wherein:
A second delay circuit for delaying the second input signal input to the second buffer circuit with respect to the second input signal input to the gate terminal of the second NMOS transistor;
The level shift circuit according to claim 5 or 6, wherein