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WO2012038121A1 - Système de puce retournée comportant un élément réfrigérant et procédé de fabrication d'un système de puce retournée - Google Patents

Système de puce retournée comportant un élément réfrigérant et procédé de fabrication d'un système de puce retournée Download PDF

Info

Publication number
WO2012038121A1
WO2012038121A1 PCT/EP2011/062879 EP2011062879W WO2012038121A1 WO 2012038121 A1 WO2012038121 A1 WO 2012038121A1 EP 2011062879 W EP2011062879 W EP 2011062879W WO 2012038121 A1 WO2012038121 A1 WO 2012038121A1
Authority
WO
WIPO (PCT)
Prior art keywords
flip
chip
cooling element
underside
arrangement according
Prior art date
Application number
PCT/EP2011/062879
Other languages
German (de)
English (en)
Inventor
Volker Weeber
Original Assignee
Robert Bosch Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch Gmbh filed Critical Robert Bosch Gmbh
Publication of WO2012038121A1 publication Critical patent/WO2012038121A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors

Definitions

  • Circuit board to be glued or soldered. Compared to the usual packaging, the chip is then reversed, ie with the active top side down, on the
  • Cooling elements according to the prior art usually have a higher thermal expansion coefficient than the flip-chip. If the flip-chip is adhesively bonded to the cooling element, then the system will become attached
  • Cooling element bonding which can damage the solder connection to the circuit carrier or the flip-chip itself.
  • the flip-chip can be connected to the cooling element instead of via a bond via a liquid or permanently elastic heat-conducting medium.
  • the cooling element must be pressed by suitable means on the flip-chip.
  • 5,610,442 discloses in a first variant a conventional chip arrangement in which the chip rests on a circuit carrier with the underside and is connected to the circuit carrier by means of bonding wires on the top side of the chip.
  • a planar substrate is glued, on which in turn an external heat sink is arranged.
  • the planar substrate comprises a rigid material such as silicon, ceramic or metal to serve automated handling of the chip. If the coefficient of thermal expansion of the planar material is different than that of the active die, a suitable adhesive of appropriate thickness may be used to avoid shear stresses due to differential thermal expansion.
  • the chip, the bonding wires and the side surfaces of the planar substrate are encapsulated.
  • US Pat. No. 5,610,442 discloses, in a second variant, a flip-chip arrangement in which the chip is soldered with the top side onto a circuit carrier. On an central partial surface of the underside of the chip, an external heat sink is arranged.
  • the flip-chip variant expressly does not use the planar substrate of the conventional variant.
  • the chip and the solder connection are encapsulated.
  • the flip-chip arrangement according to the invention has the advantage that a cooling element can be bonded to the flip-chip with a very thin adhesive layer, without mechanical stresses acting on the flip-chip as a result of this bonding in the event of temperature changes.
  • a cooling element has only a relatively small geometric extent and is used only as a spreading element to the
  • FIG. 1 is a schematic representation of a flip-chip arrangement according to a
  • Embodiment of the present invention shows
  • Fig. 2 is a schematic representation of a flip-chip arrangement according to another
  • Embodiment of the present invention shows.
  • Fig. 1 shows a flip-chip assembly 10 with a flip-chip 1 1 with contact surfaces 12 on an upper side 13 and on a lower side 14 of the flip-chip 1 1 arranged cooling element 15 according to an embodiment of the present invention.
  • the flip Chip 1 1 is by means of solder balls 16 on contact surfaces 12 with a circuit carrier 17,
  • the cooling element 15 is connected to the flip-chip 1 1 via an adhesive layer 19, which extends over the entire underside 14 of the flip-chip 11.
  • the cooling element 15 covers the entire bottom 14 of the flip-chip and extends laterally beyond the bottom 14 of the flip-chip 1 1 addition.
  • the cooling element 15 is made of a material which has a similar thermal expansion coefficient as the material of the flip-chip 1 1.
  • the cooling element 15 is made of graphite in this example. Alternative materials include ceramics and other materials
  • the flip-chip assembly 10 has the advantage that the cooling element 15 can be glued to the flip-chip 1 1 with a very thin adhesive layer 19, without mechanical stresses acting on the flip chip 1 1 by this bond with temperature changes.
  • Fig. 2 shows a flip-chip assembly 20 according to another embodiment of the present invention.
  • Flip-chip 21 is connected in the same way as flip-chip 1 1 of FIG. 1 to the circuit board 18.
  • a cooling element 22 is connected to the flip-chip 21 via an adhesive layer 23, which extends over the entire underside 24 of the flip-chip 21.
  • the cooling element 22 covers the entire underside 24 of the flip-chip and extends laterally beyond the bottom 24 of the flip-chip 21.
  • the cooling element 22 is now designed as a spreading element 25, which forms a heat connection to a heat sink 26.
  • the cooling element 22 is connected to the heat sink 26 by means of an elastic heat conducting medium in the heat conducting layer 27.
  • the cooling element 22 is made of a material which has a similar thermal expansion coefficient as the material of the flip-chip 21.
  • the cooling element 15 is made of graphite in this example.
  • the cooling element 22 has only a relatively small geometric extent and is used only as a spreading element 25 in order to increase the cross-sectional area in the heat flow direction.
  • the area of the heat-conducting layer 27 is much larger than the area of the adhesive layer 23 or the
  • the heat sink 26 may be an external heat sink, for example a housing part.
  • FIG. 3 shows in flowchart 30 the method for producing a flip-chip arrangement with a flip-chip having contact surfaces on an upper side and a cooling element arranged on the underside of the flip-chip according to an embodiment of the present invention.
  • the process begins with the process step
  • cooling element consists of a material which has a similar coefficient of thermal expansion as the material of the flip-chip.
  • the cooling element is glued to the underside of the flip-chip by means of adhesive.
  • the cooling element preferably comprises a material of ceramic and materials
  • Carbon base in particular the material graphite or the material aluminum with Carbon fibers, on.
  • a heat sink is arranged on the cooling element, wherein advantageously the cooling element is connected to the heat sink by means of an elastic heat conduction medium.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

L'invention concerne un système de puce retournée (10, 20) comportant une puce retournée (11, 21) dotée de surfaces de contact (12) sur une face supérieure (13) et un élément réfrigérant (15, 22) installé sur la face inférieure (14, 24) de la puce retournée, l'élément réfrigérant (15, 22) étant constitué d'un matériau dont le coefficient d'expansion thermique est similaire à celui du matériau de la puce retournée (11, 21). Ces matériaux sont de préférence de la céramique et des substances à base de carbone, en particulier le graphite ou l'aluminium comportant des fibres de carbone. L'élément réfrigérant (22) peut être réalisé sous forme d'élément d'écartement (25) et être relié à un dissipateur thermique externe (26) au moyen d'un milieu thermoconducteur élastique (27).
PCT/EP2011/062879 2010-09-23 2011-07-27 Système de puce retournée comportant un élément réfrigérant et procédé de fabrication d'un système de puce retournée WO2012038121A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE201010041261 DE102010041261A1 (de) 2010-09-23 2010-09-23 Flip-Chip Anordnung mit einem Kühlelement und Verfahren zur Herstellung einer Flip-Chip Anordnung
DE102010041261.9 2010-09-23

Publications (1)

Publication Number Publication Date
WO2012038121A1 true WO2012038121A1 (fr) 2012-03-29

Family

ID=44514677

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2011/062879 WO2012038121A1 (fr) 2010-09-23 2011-07-27 Système de puce retournée comportant un élément réfrigérant et procédé de fabrication d'un système de puce retournée

Country Status (2)

Country Link
DE (1) DE102010041261A1 (fr)
WO (1) WO2012038121A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150070186A (ko) * 2012-09-24 2015-06-24 메디뮨 리미티드 세포주
CN111384009A (zh) * 2018-12-26 2020-07-07 三星电子株式会社 半导体封装件

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102021209485A1 (de) 2021-08-30 2023-03-02 Robert Bosch Gesellschaft mit beschränkter Haftung Flip-Chip-Anordnung und Verfahren zum Herstellen einer Flip-Chip-Anordnung

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5778158A (en) * 1980-11-04 1982-05-15 Nippon Telegr & Teleph Corp <Ntt> Semiconductor integrated circuit device
US5523260A (en) * 1993-08-02 1996-06-04 Motorola, Inc. Method for heatsinking a controlled collapse chip connection device
US5610442A (en) 1995-03-27 1997-03-11 Lsi Logic Corporation Semiconductor device package fabrication method and apparatus
JPH09213847A (ja) * 1996-02-01 1997-08-15 Hitachi Ltd 半導体集積回路装置及びこの製造方法並びにそれを用いた電子装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5778158A (en) * 1980-11-04 1982-05-15 Nippon Telegr & Teleph Corp <Ntt> Semiconductor integrated circuit device
US5523260A (en) * 1993-08-02 1996-06-04 Motorola, Inc. Method for heatsinking a controlled collapse chip connection device
US5610442A (en) 1995-03-27 1997-03-11 Lsi Logic Corporation Semiconductor device package fabrication method and apparatus
JPH09213847A (ja) * 1996-02-01 1997-08-15 Hitachi Ltd 半導体集積回路装置及びこの製造方法並びにそれを用いた電子装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150070186A (ko) * 2012-09-24 2015-06-24 메디뮨 리미티드 세포주
KR102155389B1 (ko) 2012-09-24 2020-09-11 메디뮨 리미티드 세포주
CN111384009A (zh) * 2018-12-26 2020-07-07 三星电子株式会社 半导体封装件

Also Published As

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DE102010041261A1 (de) 2012-03-29

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