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WO2012036739A3 - An eeprom-based, data-oriented combo nvm design - Google Patents

An eeprom-based, data-oriented combo nvm design Download PDF

Info

Publication number
WO2012036739A3
WO2012036739A3 PCT/US2011/001593 US2011001593W WO2012036739A3 WO 2012036739 A3 WO2012036739 A3 WO 2012036739A3 US 2011001593 W US2011001593 W US 2011001593W WO 2012036739 A3 WO2012036739 A3 WO 2012036739A3
Authority
WO
WIPO (PCT)
Prior art keywords
floating gate
approximately
nonvolatile memory
flotox
voltage level
Prior art date
Application number
PCT/US2011/001593
Other languages
French (fr)
Other versions
WO2012036739A2 (en
Inventor
Peter W. Lee
Fu-Chang Hsu
Original Assignee
Aplus Flash Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aplus Flash Technology, Inc. filed Critical Aplus Flash Technology, Inc.
Publication of WO2012036739A2 publication Critical patent/WO2012036739A2/en
Publication of WO2012036739A3 publication Critical patent/WO2012036739A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H10D30/683—Floating-gate IGFETs having only two programming levels programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)

Abstract

A nonvolatile memory device has a combination of FLOTOX EEPROM nonvolatile memory arrays. Each FLOTOX-based nonvolatile memory array is formed of FLOTOX-based nonvolatile memory cells that include at least one floating gate tunneling oxide transistor such that a coupling ratio of the control gate to the floating gate of the floating gate tunneling oxide transistor is from approximately 60% to approximately 70% and a coupling ratio of the floating gate to the drain region of the floating gate tunneling oxide transistor is maintained as a constant of is from approximately 10% to approximately 20% and such that a channel length of the channel region is decreased such that during the programming procedure a negative programming voltage level is applied to the control gate and a moderate positive programming voltage level is applied to the drain region to prevent the moderate positive programming voltage level from exceeding a drain-to-source breakdown voltage.
PCT/US2011/001593 2010-09-15 2011-09-15 An eeprom-based, data-oriented combo nvm design WO2012036739A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US40347910P 2010-09-15 2010-09-15
US61/403,479 2010-09-15

Publications (2)

Publication Number Publication Date
WO2012036739A2 WO2012036739A2 (en) 2012-03-22
WO2012036739A3 true WO2012036739A3 (en) 2012-05-18

Family

ID=45832154

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2011/001593 WO2012036739A2 (en) 2010-09-15 2011-09-15 An eeprom-based, data-oriented combo nvm design

Country Status (1)

Country Link
WO (1) WO2012036739A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8675405B1 (en) * 2013-03-12 2014-03-18 Cypress Semiconductor Corp. Method to reduce program disturbs in non-volatile memory cells
US10262747B2 (en) 2013-03-12 2019-04-16 Cypress Semiconductor Corporation Method to reduce program disturbs in non-volatile memory cells
US9361995B1 (en) * 2015-01-21 2016-06-07 Silicon Storage Technology, Inc. Flash memory system using complementary voltage supplies

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040079972A1 (en) * 2002-10-22 2004-04-29 Terra Semiconductor, Inc. Flash EEPROM unit cell and memory array architecture including the same
US20060221682A1 (en) * 2004-02-24 2006-10-05 Taiwan Semiconductor Manufacturing Company, Ltd. Floating gate memory with split-gate read transistor and split gate program transistor memory cells and method for making the same
US20060262605A1 (en) * 1989-02-06 2006-11-23 Koichi Seki Nonvolatile semiconductor memory device
US20070053223A1 (en) * 2005-09-02 2007-03-08 Samsung Electronics Co., Ltd. Non-Volatile Memory Devices Having L-Shaped Floating Gate Electrodes and Methods of Forming Same
US20090190402A1 (en) * 2008-01-03 2009-07-30 Aplus Flash Technology, Inc. Integrated SRAM and FLOTOX EEPROM memory device
US20100171168A1 (en) * 2009-01-06 2010-07-08 Samsung Electronics Co., Ltd Non-volatile memory device and method of manufacturing the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060262605A1 (en) * 1989-02-06 2006-11-23 Koichi Seki Nonvolatile semiconductor memory device
US20040079972A1 (en) * 2002-10-22 2004-04-29 Terra Semiconductor, Inc. Flash EEPROM unit cell and memory array architecture including the same
US20060221682A1 (en) * 2004-02-24 2006-10-05 Taiwan Semiconductor Manufacturing Company, Ltd. Floating gate memory with split-gate read transistor and split gate program transistor memory cells and method for making the same
US20070053223A1 (en) * 2005-09-02 2007-03-08 Samsung Electronics Co., Ltd. Non-Volatile Memory Devices Having L-Shaped Floating Gate Electrodes and Methods of Forming Same
US20090190402A1 (en) * 2008-01-03 2009-07-30 Aplus Flash Technology, Inc. Integrated SRAM and FLOTOX EEPROM memory device
US20100171168A1 (en) * 2009-01-06 2010-07-08 Samsung Electronics Co., Ltd Non-volatile memory device and method of manufacturing the same

Also Published As

Publication number Publication date
WO2012036739A2 (en) 2012-03-22

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