WO2012008197A1 - Appareil émetteur/récepteur - Google Patents
Appareil émetteur/récepteur Download PDFInfo
- Publication number
- WO2012008197A1 WO2012008197A1 PCT/JP2011/060030 JP2011060030W WO2012008197A1 WO 2012008197 A1 WO2012008197 A1 WO 2012008197A1 JP 2011060030 W JP2011060030 W JP 2011060030W WO 2012008197 A1 WO2012008197 A1 WO 2012008197A1
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- WO
- WIPO (PCT)
- Prior art keywords
- phase
- signal
- loop
- loop band
- detection circuit
- Prior art date
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- 230000010355 oscillation Effects 0.000 claims abstract description 11
- 238000001514 detection method Methods 0.000 claims description 45
- 230000005540 biological transmission Effects 0.000 claims description 10
- 230000002194 synthesizing effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 16
- 238000001228 spectrum Methods 0.000 description 12
- 238000000034 method Methods 0.000 description 11
- 230000001360 synchronised effect Effects 0.000 description 5
- 238000004891 communication Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 230000035945 sensitivity Effects 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000010365 information processing Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
- H03L7/1072—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the charge pump, e.g. changing the gain
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
- H03L7/1075—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth
Definitions
- the present invention relates to a transmitter / receiver provided with a plurality of transmitter / receiver blocks.
- a plurality of antennas are required to realize a spatial diversity method and a beam steering method, and a baseband signal is converted into an RF (Radio Frequency) signal, or an RF signal is converted into a baseband signal.
- RF Radio Frequency
- a transceiver block and an antenna with a shortest distance in order to reduce a loss due to wiring.
- the transceiver block is also arranged apart.
- the number of antennas and the number of transmitter / receiver blocks may be increased in order to increase the gain by the antenna.
- the number of antennas and the number of transmitter / receiver blocks may be increased in order to increase the gain by the antenna.
- the size of the IC becomes too large.
- the manufacturing yield may be reduced.
- each transmitter / receiver block is usually formed by an individual IC. Even if each transmitter / receiver block is formed of individual ICs, the LO signal phase is synchronized for each transmitter / receiver block when the LO signal generated by one LO signal (local oscillation signal) source is distributed to each IC. There is a problem that it is difficult to cause the distribution loss to increase. For this reason, in a radio communication system of the spatial diversity method or the beam steering method, a plurality of transmitter / receiver blocks are formed by individual ICs, and LO signal sources are provided in the respective transmitter / receiver blocks, and phase synchronization is performed by these LO signal sources. A configuration for generating each LO signal is adopted.
- FIG. 1 shows a configuration example of a background art receiving apparatus including two receiver blocks 1a and 1b.
- the receiving apparatus shown in FIG. 1 has two receiver blocks 1a and 1b, two antennas 2a and 2b, and a signal source 5 that oscillates a signal having a constant frequency with high stability.
- the receiver block 1a includes a low-noise amplifier 3a, a mixer 4a, and a phase-locked oscillator (hereinafter referred to as PLO (Phase Locked Oscillator)) 6a which is an LO signal source.
- the receiver block 1b includes a low noise amplifier 3b, a mixer 4b, and a PLO 6b.
- a well-known PLL (Phase Locked Loop) circuit is used for the PLOs 6a and 6b.
- the PLO (PLL circuit) used in the wireless communication system is also described in Patent Document 1 and Patent Document 2, for example.
- the RF signals received by the antennas 2a and 2b are amplified by the low noise amplifiers 3a and 3b.
- the PLOs 6a and 6b generate LO signals whose phases are synchronized with the signals output from the signal source 5, respectively.
- the RF signals output from the low noise amplifiers 3a and 3b are mixed with the LO signals generated by the PLOs 6a and 6b and down-converted by the mixers 4a and 4b.
- the signals output from the two mixers 4a and 4b are combined on the wiring path and output from the output terminal 7 as a baseband signal.
- FIG. 2 shows a signal waveform (130 MHz) of a baseband signal appearing at the output terminal 7 when an RF signal (sine wave) of 60.61 GHz is input to the receiving apparatus shown in FIG. 1 (the frequency of the LO signal is 60.48 GHz). Sine wave) measurement results.
- the output signal (baseband signal) of the receiving apparatus shown in FIG. 1 has a large jitter and contains many unnecessary frequency components.
- PLOs 6a and 6b having sufficiently small phase noise may be used.
- the present invention provides a transmitter / receiver that includes a plurality of transmitter / receiver blocks and can reduce jitter of a signal obtained by synthesizing the output signals of the transmitter / receiver blocks even in a high frequency band where an LO signal source with sufficiently small phase noise cannot be realized.
- the purpose is to provide.
- the transmitting / receiving apparatus of the present invention generates a phase oscillation signal for generating a local oscillation signal for down-converting each RF signal received by a plurality of antennas or a local oscillation signal for up-converting a baseband signal.
- a loop band detection circuit that detects a difference in loop band of the phase-locked oscillator provided for each transceiver block and generates a control signal for matching the loop band of the phase-locked oscillator; and
- FIG. 1 is a block diagram illustrating a configuration of a background art receiving apparatus including a plurality of receiver blocks.
- FIG. 2 is a waveform diagram illustrating an example of a signal waveform of a baseband signal output from the receiving apparatus illustrated in FIG.
- FIG. 3 is a graph showing the frequency spectrum of the output signal of each receiver block included in the receiving apparatus shown in FIG.
- FIG. 4 is a graph showing a state when the frequency spectrums of the output signals of the respective receiver blocks included in the receiving apparatus shown in FIG. 1 are matched.
- FIG. 5 is a waveform diagram showing an example of a signal waveform of a baseband signal output from the receiving apparatus in the state shown in FIG. FIG.
- FIG. 6A is a diagram illustrating a configuration example of the transmission / reception device according to the first embodiment, and is a block diagram illustrating an overall configuration of the reception device.
- FIG. 6B is a block diagram illustrating a configuration example of the PLO illustrated in FIG. 6A.
- FIG. 7A is a block diagram showing another configuration example of the PLO shown in FIG. 6A.
- FIG. 7B is a circuit diagram showing a configuration example of the loop filter shown in FIG. 7A.
- FIG. 8 is a block diagram illustrating a configuration example of the loop band detection circuit illustrated in FIG. 6A.
- FIG. 9 is a block diagram illustrating a configuration example of the PLO for improving the detection sensitivity of the power sensor illustrated in FIG.
- FIG. 10 is a block diagram illustrating a configuration example of the receiving apparatus according to the second embodiment.
- FIG. 3 shows frequency spectra of output signals of the respective receiver blocks 1a and 1b when the two receiver blocks 1a and 1b provided in the receiving apparatus shown in FIG. 1 are individually operated.
- the frequency spectrum of the output signal of the receiver block 1a is significantly different from the frequency spectrum of the output signal of the receiver block 1b. This is because the phase noises output from the PLOs 6a and 6b are different due to the performance variations of the PLOs 6a and 6b, which are PLL circuits, in particular, the loop bands of the PLO 6a and the PLO 6b are different.
- FIG. 4 shows a state when the frequency spectra of the output signals of the two receiver blocks 1a and 1b shown in FIG. 1 are matched.
- FIG. 5 shows the signal waveform of the baseband signal output from the receiving apparatus when the frequency spectra of the receiver blocks 1a and 1b are matched as shown in FIG.
- FIG. 4 shows the result of adjustment to widen the loop band of the PLO (PLL circuit) 6a in order to match the frequency spectrum of the output signal of the reception block 1b with the frequency spectrum of the output signal of the reception block 1a.
- PLO PLO
- the phase noise of the LO signal includes (1) fluctuation of a reference frequency of a crystal oscillator, (2) fluctuation of a power supply voltage supplied from an external power supply, (3) jitter existing in a PLL circuit such as a phase comparator, (4 ) Generated by thermal noise or 1 / f noise of the voltage controlled oscillator of the PLL circuit.
- (1) and (2) are considered to have the same influence on a plurality of PLOs, that is, the same origin of phase noise.
- the jitters pointed out in (3) there is no correlation with random jitter, but there is a case where there is a correlation with regular jitter called deterministic jitter. That is, the phase noise of LO signals generated by a plurality of PLOs may be synchronized.
- the LO signals generated by the respective PLOs are similarly modulated by the phase noise when the loop bands are matched. Therefore, it is considered that the jitter (fluctuation) of the baseband signal that is a signal obtained by synthesizing the output signals of the plurality of receiver blocks is reduced.
- FIG. 6A shows the overall configuration of the receiving apparatus
- FIG. 6B shows an example of the configuration of the PLO shown in FIG. 6A
- 7A is a block diagram showing another configuration example of the PLO shown in FIG. 6A
- FIG. 7B is a circuit diagram showing a configuration example of the loop filter shown in FIG. 7A.
- the receiving apparatus includes two receiver blocks 1a and 1b, two antennas 2a and 2b, and a signal source that oscillates a signal having a constant frequency (hereinafter referred to as a reference signal) with high stability. 5 and a loop band detection circuit 16 that detects a difference between the loop bands of the PLOs included in the receiver blocks 1a and 1b and adjusts the loop bands to coincide with each other.
- a reference signal a signal having a constant frequency
- the receiver block 1a includes a low noise amplifier 3a, a mixer 4a, and a PLO 6a.
- the receiver block 1b includes a low noise amplifier 3b, a mixer 4b, and a PLO 6b.
- the signals received by the antennas 2a and 2b are amplified by the low noise amplifiers 3a and 3b.
- the PLOs 6a and 6b generate LO signals whose phases are synchronized with the reference signal output from the signal source 5, respectively.
- the output signals of the low noise amplifiers 3a and 3b are mixed by the LO signals generated by the PLOs 6a and 6b with the mixers 4a and 4b and down-converted.
- the signals output from the mixers 4a and 4b are combined in the wiring path and output from the output terminal 7 as a baseband signal.
- each of the PLOs 6a and 6b includes a voltage controlled oscillator 8, a frequency divider (DIV) 9, a phase comparator (PFD) 10, a charge pump (CP) 11, and a loop filter 12, respectively.
- This is a PLL (Phased Locked Loop) circuit.
- FIG. 6B shows an example in which a low-pass filter (LPF) is used as the loop filter 12.
- LPF low-pass filter
- FIG. 6B shows a configuration example for adjusting the loop bandwidth of the PLOs 6a and 6b by changing the output current amount of the charge pump (CP) 11.
- the reference signal generated by the signal source 5 is input to the phase comparator 10 via the input terminal 13.
- the phase comparator 10 compares the phase of the reference signal with the phase of the output signal of the frequency divider 9 and outputs a signal corresponding to the phase difference between them.
- the charge pump 11 outputs a current having a value corresponding to the output signal of the phase comparator 10.
- the loop filter 12 converts the output current of the charge pump 11 into a voltage signal and blocks a high frequency signal component of the voltage signal.
- the voltage controlled oscillator 8 oscillates a signal having a frequency corresponding to the input voltage.
- the frequency divider 9 divides the oscillation frequency of the voltage controlled oscillator 8 and feeds it back to the phase comparator 10.
- the feedback loop operates so that the frequency of the reference signal matches the frequency of the output signal of the frequency divider 9. Therefore, an LO signal having a desired frequency can be obtained from the voltage controlled oscillator 8 based on the frequency of the reference signal and the frequency division ratio of the frequency divider 9.
- the LO signal output from the voltage controlled oscillator 8 is output from the output terminal 14.
- the loop bands of the PLOs 6a and 6b are determined by the gain of the phase comparator 10, the output current amount of the charge pump 11, and the band of the loop filter 12.
- the LO signals generated by the PLOs 6a and 6b are input to the loop band detection circuit 16, respectively.
- the loop band detection circuit 16 detects a difference between the loop bands of the PLOs 6a and 6b from the LO signals generated by the PLOs 6a and 6b, and supplies a control signal for matching the loop bands to the PLOs 6a and 6b.
- the loop band detection circuit 16 matches the loop bands of the PLOs 6a and 6b by changing the amount of current of the charge pump 11 included in the PLOs 6a and 6b, for example, by changing the voltage applied to the current source, according to the control signal.
- the loop band detection circuit 16 uses the control signal to charge the PLO 6a.
- the current amount of the pump 11 is decreased or the current amount of the charge pump 11 of the PLO 6b is increased.
- the loop band detection circuit 16 matches the loop bands of the PLOs 6a and 6b that generate the LO signal. As a result, the jitter of the baseband signal output from the output terminal 7 of the receiving device is reduced.
- the loop band of the PLOs 6a and 6b can be adjusted by changing the filter characteristics of the loop filter 12.
- a low-pass filter including capacitive elements 19a and 19b whose capacitance value can be changed by an input voltage or a resistive element 20 whose resistance value can be changed by an input voltage.
- the loop band detection circuit 16 may match the loop bands of the PLOs 6a and 6b by changing the capacitance values of the capacitive elements 19a and 19b or the resistance value of the resistive element 20 according to the control signal.
- the PLOs 6a and 6b have the configuration shown in FIG. 7A.
- the loop band detection circuit 16 can be realized, for example, with the configuration shown in FIG.
- FIG. 8 is a block diagram showing an example of the configuration of the loop band detection circuit shown in FIG. 6A.
- the loop band detection circuit 16 includes a mixer 21, a power sensor 22 that detects a power value of a signal output from the mixer 21, and a control unit 28.
- the LO signals generated by the PLOs 6a and 6b are input to the mixer 21 via the input terminals 23a and 23b.
- the signal output from the mixer 21 is the difference between the LO signals generated by the PLOs 6a and 6b, and becomes a frequency spectrum having a peak in the low frequency region (usually several MHz or less).
- the power value of the difference in phase noise power at the high detuning frequency of the voltage controlled oscillator 8 provided in the PLOs 6a and 6b appears.
- the phase noise power of the voltage controlled oscillator 8 is originally very small and the power value of the difference between the phase noise powers is also small, this value need not be considered.
- the power value of the signal output from the mixer 21 is equal to the difference between the loop bands of the PLOs 6a and 6b. Therefore, if the control signal is supplied to the PLOs 6a and 6b so that the power value (detected value) detected by the power sensor 22 is minimized, the loop bands of the PLOs 6a and 6b can be made to substantially coincide.
- the control unit 28 generates a control signal for adjusting the loop band of the PLOs 6a and 6b so as to minimize the detection value of the power sensor 22, and outputs the control signal from the output terminals 24a and 24b.
- the control unit 28 may be any circuit as long as the detection value of the power sensor 22 can be arithmetically processed, and includes a combinational circuit, a sequential circuit, a DSP, a CPU, an FPGA, a memory, an A / D converter, a D / A converter, and the like. It can be realized by a known information processing apparatus.
- the control signal generation method by the control unit 28 includes the following methods.
- a control signal for expanding one of the PLOs 6a and 6b is output, and a change in the detection value of the power sensor 22 is observed.
- a control signal for expanding the loop band of the PLO 6a is output from the output terminal 24a.
- the control unit 28 reduces the loop band of the PLO (in this case, PLO 6a) that has been changed until the detection value of the power sensor 22 becomes sufficiently small.
- a control signal for narrowing is output.
- a control signal for widening the loop band of the PLO that has not been changed first is output.
- the control unit 28 increases the loop bandwidth of the PLO (in this case, PLO 6a) that has been changed until the detection value of the power sensor 22 becomes sufficiently small. Outputs a control signal for spreading. Alternatively, a control signal for narrowing the loop band of the PLO that has not been changed first (in this case, PLO 6b) is output.
- the detection sensitivity of the power sensor 22 included in the loop band detection circuit 16 is not so high, the detection sensitivity can be improved by the following method.
- one end of the switch 25 is connected to a connection node between the phase comparators 10 of the PLOs 6 a and 6 b and the charge pump 11, and the other end of the switch 25 is connected to the input terminal 26.
- the control unit 28 inputs a pilot signal from the input terminal 26 and makes the switch 25 conductive.
- the frequency of the pilot signal is set to a frequency slightly higher than at least one of the loop bands of the PLOs 6a and 6b.
- a peak appears at a frequency separated from the center frequency by the frequency of the pilot signal in the frequency spectrum of the LO signal generated by the PLOs 6a and 6b.
- the level of the peak due to the pilot signal differs depending on the difference between the frequency of the loop band of the PLOs 6a and 6b and the frequency of the pilot signal. That is, since the difference between the loop bands of the PLOs 6a and 6b appears as a peak value, if the peak value is detected using the power sensor 22, the difference between the loop bands of the PLOs 6a and 6b can be detected.
- the configuration and method for matching the loop bandwidth of the PLO included in each receiver block have been described using the receiver as an example.
- the low noise amplifier 3a instead of 3b, if a power amplifier for supplying the RF signals output from the mixers 4a and 4b to the antennas 2a and 2b is provided, and an up-conversion mixer is used as the mixers 4a and 4b, the technique shown in this embodiment is
- the present invention can also be applied to a transmission apparatus having a plurality of transmitter blocks having a PLO.
- the configuration example in which the receiver includes the two receiver blocks 1a and 1b has been described.
- the number of receiver blocks is not limited to two, and three or more receiver blocks are provided. May be.
- the PLO loop band included in any one of the receiver blocks is used as a reference, and the PLO loop band included in the other receiver block is determined as the reference PLO loop band. Should be matched to each.
- the loop band detection circuit 16 can match the loop bands of the PLOs 6a and 6b included in the receiver blocks 1a and 1b. Therefore, in a receiving device including a plurality of receiver blocks, jitter of the signal waveform of the baseband signal can be reduced even in a high frequency band where an LO signal source with sufficiently small phase noise cannot be realized.
- FIG. 10 is a block diagram illustrating a configuration example of the receiving apparatus according to the second embodiment.
- the receiving apparatus includes a jitter detection circuit 27 that detects the power of the jitter component of the baseband signal that is output from the receiver blocks 1a and 1b and is synthesized.
- the bandwidth detection circuit 16 is different from the reception device shown in the first embodiment in that the loop bandwidth of the PLO included in each receiver block is adjusted in consideration of the power of the jitter component detected by the jitter detection circuit 27. ing. Since other configurations and operations are the same as those of the receiving apparatus according to the first embodiment, description thereof is omitted. Since the second embodiment is configured to detect the power of the jitter component of the baseband signal, it can be applied only to the receiving apparatus.
- the jitter of the baseband signal output from the receiving device largely depends on the relationship of the loop bandwidth of the PLO included in each receiver block.
- the power of the jitter component detected by the jitter detection circuit 27 is minimized while the loop band detection circuit 16 adjusts the loop bands of the PLOs 6a and 6b to coincide. Further, the loop band of the PLOs 6a and 6b is further adjusted.
- the jitter detection circuit 27 may acquire the power of the jitter component included in the baseband signal by using, for example, the following methods (1) to (3).
- a jitter component is extracted from the baseband signal output from the receiving device by filtering, and the power of the extracted jitter component is measured by a power sensor.
- a jitter component is extracted from the baseband signal output from the receiving device by FFT processing, and the power of the extracted jitter component is measured by a power sensor.
- the power of the output signal of the receiver block 1a and the power of the output signal of the receiver block 1b are respectively measured by the power sensor, and a first detection value obtained by adding these values is obtained.
- the second detection value obtained by measuring the power of the baseband signal output from the receiving apparatus that is, the power of the signal output from the receiver blocks 1a and 1b and synthesized by the wiring path, with the power sensor is acquired.
- the electric power of a jitter component is acquired by calculating
- the jitter detection circuit 27 executes the above filter processing, FFT processing, arithmetic processing, and the like in addition to the power sensor.
- Combination circuit, sequential circuit, DSP, CPU, FPGA, memory, A / D converter, D / A conversion This can be realized by a well-known information processing apparatus equipped with a container.
- the jitter band 27 is adjusted by the loop band detection circuit 16 so that the loop bands of the PLOs 6a and 6b match, and the jitter component power included in the baseband signal is detected by the jitter detection circuit 27. Since the loop band of the PLOs 6a and 6b is adjusted so that the power of the jitter component is minimized, the jitter of the signal waveform of the baseband signal can be reduced as compared with the receiving apparatus of the first embodiment.
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- Noise Elimination (AREA)
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Abstract
L'invention concerne un appareil émetteur/récepteur comprenant une pluralité de blocs émetteurs/récepteurs incluant des oscillateurs à synchronisation de phase respectifs pour générer des signaux d'oscillation locaux utilisés pour abaisser la fréquence des signaux RF correspondants reçus par une pluralité d'antennes ou encore des signaux d'oscillation locaux utilisés pour élever la fréquence des signaux en bande de base. L'appareil émetteur/récepteur comprend en outre un circuit détecteur de bande de boucle qui détecte la différence entre les bandes de boucle des oscillateurs à synchronisation de phase se trouvant dans les blocs émetteurs/récepteurs respectifs et qui génèrent un signal de commande utilisé pour faire coïncider entre elles les bandes de boucle des oscillateurs à synchronisation de phase respectifs.
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JP2012524473A JPWO2012008197A1 (ja) | 2010-07-13 | 2011-04-25 | 送受信装置 |
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JP2010158647 | 2010-07-13 | ||
JP2010-158647 | 2010-07-13 |
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WO2012008197A1 true WO2012008197A1 (fr) | 2012-01-19 |
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PCT/JP2011/060030 WO2012008197A1 (fr) | 2010-07-13 | 2011-04-25 | Appareil émetteur/récepteur |
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WO (1) | WO2012008197A1 (fr) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10771030B2 (en) | 2018-08-24 | 2020-09-08 | Analog Devices International Unlimited Company | Phase-locked loop with adjustable bandwidth |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0730318A (ja) * | 1993-07-13 | 1995-01-31 | Sumitomo Electric Ind Ltd | 同相合成装置およびそれを用いたアンテナ装置 |
JPH0846662A (ja) * | 1994-07-27 | 1996-02-16 | Fujitsu Ltd | 同期検波方式 |
-
2011
- 2011-04-25 WO PCT/JP2011/060030 patent/WO2012008197A1/fr active Application Filing
- 2011-04-25 JP JP2012524473A patent/JPWO2012008197A1/ja not_active Withdrawn
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0730318A (ja) * | 1993-07-13 | 1995-01-31 | Sumitomo Electric Ind Ltd | 同相合成装置およびそれを用いたアンテナ装置 |
JPH0846662A (ja) * | 1994-07-27 | 1996-02-16 | Fujitsu Ltd | 同期検波方式 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10771030B2 (en) | 2018-08-24 | 2020-09-08 | Analog Devices International Unlimited Company | Phase-locked loop with adjustable bandwidth |
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JPWO2012008197A1 (ja) | 2013-09-05 |
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