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WO2011093225A1 - Dispositif d'imagerie à semi-conducteurs et procédé de lecture de signaux de matrice de pixels de dispositif d'imagerie à semi-conducteurs - Google Patents

Dispositif d'imagerie à semi-conducteurs et procédé de lecture de signaux de matrice de pixels de dispositif d'imagerie à semi-conducteurs Download PDF

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Publication number
WO2011093225A1
WO2011093225A1 PCT/JP2011/051093 JP2011051093W WO2011093225A1 WO 2011093225 A1 WO2011093225 A1 WO 2011093225A1 JP 2011051093 W JP2011051093 W JP 2011051093W WO 2011093225 A1 WO2011093225 A1 WO 2011093225A1
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WIPO (PCT)
Prior art keywords
signal
circuit
column
pixel
signal processing
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PCT/JP2011/051093
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English (en)
Japanese (ja)
Inventor
祥二 川人
聡 青山
恭志 渡辺
鍾皓 朴
Original Assignee
国立大学法人静岡大学
株式会社ブルックマン テクノロジ
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Priority to JP2011551832A priority Critical patent/JPWO2011093225A1/ja
Publication of WO2011093225A1 publication Critical patent/WO2011093225A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/67—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response
    • H04N25/671—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction
    • H04N25/677—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction for reducing the column or line fixed pattern noise
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Definitions

  • the present invention relates to a solid-state imaging device and a method of reading a signal from a pixel array of the solid-state imaging device.
  • Patent Document 1 describes a CMOS image sensor.
  • the imaging unit has an effective pixel unit and an ineffective pixel unit.
  • the effective pixel portion and the invalid pixel portion include the same pixel circuit.
  • An optical black portion for fixed pattern noise correction is provided in a part of the invalid pixel portion.
  • the signal amount of each pixel obtained from the optical black portion is measured, and the signal amount of the pixel of the optical black portion is subtracted from the signal amount of the effective pixel portion.
  • the pixel average signal amount of the optical black portion is obtained as an average value by a predetermined averaging process, and this average value is subtracted from the signal amount of each pixel of the effective pixel portion.
  • an optical black portion is provided around an effective pixel portion that generates imaging data.
  • the optical black portion is a pixel including a light-shielded photoelectric conversion element, a transfer gate, and a floating diffusion portion, or including a transfer gate and a floating diffusion portion. The difference between the signal obtained from the pixel in the optical black portion and the signal obtained from the pixel in the effective pixel portion is generated to cancel the fixed pattern noise.
  • a pixel in the invalid pixel includes a photoelectric conversion element covered with a light shielding film for shielding light, a transfer gate, and a floating diffusion portion.
  • the optical black portion is affected by light leakage from the effective pixel portion and carrier diffusion through the substrate of the CMOS image sensor.
  • an invalid pixel that is affected by leakage light or diffused electrons cannot play the role of a correct optical black because its reference level changes depending on incident light. Therefore, stable fixed pattern noise removal cannot be performed using optical black.
  • the influence of leakage on such invalid pixels becomes more prominent as the pixel size becomes smaller, and becomes a serious problem particularly in an image sensor using finer pixels.
  • fixed pattern noise can be roughly categorized into the following two types.
  • One is fixed pattern noise (hereinafter referred to as “pixel fixed pattern noise”) caused by the pixel circuit in the pixel, and the other is fixed pattern noise (hereinafter referred to as “column”) caused by the column circuit.
  • Pixel fixed pattern noise is caused by dark current of a photoelectric conversion element of a pixel, threshold value variation of a transistor of a pixel circuit, and the like.
  • the column fixed pattern noise is caused by column circuits arranged in the columns of the pixel array. The imaging signals from the individual column circuits reflect the characteristics of the column circuits used for reading out the pixel signals corresponding to the imaging signals.
  • the column circuits arranged in the columns of the pixel array have different characteristics for each column circuit due to variations in electronic elements such as capacitors, transistors, and amplifiers in the column circuit. For this reason, a signal from a certain column circuit has noise inherent to the column circuit. For example, in the dark when light is not incident on a pixel array having no variation, a difference that appears between readout signals for each column circuit is caused by column fixed pattern noise.
  • the present invention has been made in view of such circumstances, and an object of the present invention is to provide a solid-state imaging device capable of reducing column fixed pattern noise without being affected by light leakage from a pixel array or diffused electrons. It is another object of the present invention to provide a method of reading a signal from a pixel array of a solid-state imaging device that can reduce column fixed pattern noise.
  • the solid-state imaging device includes: (a) a pixel array including pixels having a photoelectric conversion element and a pixel circuit that provides a signal from the photoelectric conversion element; and (b) a pseudo signal source for reducing column fixed pattern noise.
  • a reference signal generation unit having one or a plurality of reference circuits including the reference circuit and arranged outside the pixel array, and (c) an imaging signal from a pixel signal from the pixel array and a pseudo signal from the reference signal generation unit, respectively.
  • a column signal processing unit including a column signal processing circuit that generates a reference signal, and (d) a signal processing unit that receives the imaging signal and the reference signal and generates a readout signal.
  • the pixel array includes a plurality of column arrangements, the column signal processing unit reads the pseudo signal k times (1 ⁇ k) per frame, and the pseudo signal source of the reference circuit includes a photoelectric conversion element and The readout signal of the signal processing unit does not include a floating diffusion unit, and is generated by performing arithmetic processing on the imaging signal using the reference signal to reduce column fixed pattern noise related to the column signal processing circuit. .
  • the column signal processing circuit generates an imaging signal and a reference signal from the pixel signal and the pseudo signal, respectively. Therefore, the imaging signal and the reference signal include column fixed pattern noise related to the column signal processing circuit. Since the signal processing unit performs the above arithmetic processing on the imaging signal using the reference signal, column fixed pattern noise related to the column signal processing circuit is reduced in the readout signal. Since the pseudo signal source does not include a photoelectric conversion element and a floating diffusion portion, the column fixed pattern noise reduction process is not affected by light leakage from the pixel array or diffused electrons.
  • Another aspect of the present invention relates to a method of reading a signal from a pixel array of a solid-state imaging device including a column signal processing circuit and a reference circuit.
  • the method includes (a) reading out a pixel signal from a pixel in the pixel array using the column signal processing circuit to generate an imaging signal, and (b) from the reference circuit outside the pixel array. Reading a pseudo signal for reducing column fixed pattern noise using the column signal processing circuit to generate a reference signal; and (c) column fixed pattern noise related to the column signal processing circuit. Performing a reduction operation on the imaging signal using the reference signal to generate a readout signal.
  • the pixel includes a photoelectric conversion element and a pixel circuit that provides a signal from the photoelectric conversion element, the reference circuit includes a pseudo signal source that generates the pseudo signal, and the pseudo signal source is a photoelectric conversion element.
  • the column signal processing circuit does not include the floating diffusion unit and performs at least one of correlated double sampling, A / D conversion, amplification, and sample and hold operations on the pixel signal and the pseudo signal. .
  • the imaging signal and the reference signal are generated from the pixel signal and the pseudo signal, respectively, using the same column signal processing circuit. Therefore, the imaging signal and the reference signal include column fixed pattern noise related to the column signal processing circuit. Since the above arithmetic processing is performed on the imaging signal using the reference signal, column fixed pattern noise related to the column signal processing circuit is reduced in the readout signal. Since the pseudo signal source does not include a photoelectric conversion element and a floating diffusion portion, the column fixed pattern noise reduction process is not affected by light leaked from the pixel array or diffused electrons.
  • the pixels in each column array are connected to column lines.
  • the reference circuit may include a switch for providing the pseudo signal to the column line.
  • the pixel circuit of the pixel may include a control mechanism for providing a signal from the photoelectric conversion element of the pixel to the column line.
  • the reference circuit provides a pseudo signal to the column line via the switch.
  • the pixel circuit provides a pixel signal to the column line through a control mechanism. Therefore, the reference circuit can generate a pseudo signal suitable for reducing column fixed pattern noise.
  • the column signal processing unit includes an array of the column signal processing circuits, and each of the column signal processing circuits is connected to the column array, and the reference
  • the signal generation unit includes an array of the reference circuits, each of the reference circuits is connected to the column signal processing circuit, and the signal processing unit includes an arithmetic circuit that performs the arithmetic processing, and the signal processing unit Performs processing for generating a difference between the reference signal and the imaging signal as the arithmetic processing for each column signal processing circuit, and the readout signal can be generated using the arithmetic circuit.
  • each of the column signal processing circuits is electrically connected to the column arrangement, and each of the reference circuits is electrically connected to the column signal processing circuit.
  • a column signal processing circuit and a reference circuit are provided for each column arrangement.
  • the imaging signal and the reference signal read for each column array include column fixed pattern noise related to the column signal processing circuit for the column array.
  • the signal processing unit can perform the above arithmetic processing on the imaging signal using the reference signal for each column arrangement.
  • the reference signal generation unit may include an additional reference circuit connected to the column signal processing circuit.
  • the reference signal generation unit can read the pseudo signal from the reference circuit and the additional reference circuit.
  • the reference signal may be generated by combining the pseudo signal from the reference circuit and the additional reference circuit. Further, since the position of the reference circuit is different from the position of the additional reference circuit, the variation of these reference circuits can be averaged. Reading of the pseudo signal from the reference circuit is performed at a time different from that of reading the pseudo signal from the additional reference circuit, which helps to reduce random noise.
  • the column signal processing unit may include a correlated double sampling (CDS) circuit.
  • the correlated double sampling circuit reads the pixel signal, and the pixel signal includes a first signal level including a noise component and a second signal level including a signal component superimposed on the noise component, and the imaging The signal indicates a difference between the first signal and the second signal.
  • CDS correlated double sampling
  • column fixed pattern noise caused by the CDS circuit can be reduced.
  • the CDS circuit With the CDS circuit, reset noise in the pixel circuit and variations in threshold values of the transistors can be removed.
  • the column signal processing unit may include an A / D conversion circuit that receives an output signal from the correlated double sampling circuit.
  • the A / D conversion circuit provides a digital reference signal and an imaging signal.
  • the A / D conversion method in the A / D conversion circuit is, for example, an integral type conversion, a cyclic type conversion, a successive approximation type conversion, or a conversion method combining them.
  • said conversion system is applicable to a solid-state imaging device.
  • the column signal processing circuit includes first and second capacitors, an operational amplifier circuit, and the first capacitor, the second capacitor, and the operational amplifier circuit.
  • a switch circuit for changing the connection of the The switch circuit includes a first connection that enables correlated double sampling to the first and second capacitors and the operational amplifier circuit, and a cyclic A to the first and second capacitors and the operational amplifier circuit. And a second connection enabling D conversion.
  • the column signal processing circuit can perform the correlated double sampling by the first connection and the cyclic A / D conversion by the second connection.
  • column fixed pattern noise caused by the operational amplifier circuit, the first capacitor, the second capacitor, and the switch circuit can be reduced.
  • the pixel array, the reference signal generation unit, and the column signal processing unit can be integrated on a single semiconductor chip.
  • the signal processing unit is provided outside the semiconductor chip. Without being limited to being integrated on a single semiconductor chip, the signal processing unit can be provided in various forms.
  • the pixel array, the reference signal generation unit, the column signal processing unit, and the signal processing unit can be integrated on a single semiconductor chip. According to the above aspect, a readout signal with reduced column fixed pattern noise is provided from an integrated circuit for a solid-state imaging device.
  • a solid-state imaging device capable of reducing column fixed pattern noise without being affected by light leaked from a pixel array or diffused electrons is provided. Further, according to the present invention, a method for reading a signal from a pixel array of a solid-state imaging device is provided. According to this method, column fixed pattern noise can be reduced.
  • FIG. 1 is a diagram illustrating a block configuration of a solid-state imaging device such as a two-dimensional image sensor.
  • FIG. 2 is a diagram illustrating a configuration of a reference circuit of the reference voltage generation unit.
  • FIG. 3 is a diagram illustrating an arrangement of reference circuits.
  • FIG. 4 is a diagram illustrating an example of a column signal processing circuit for the solid-state imaging device according to the present embodiment.
  • FIG. 5 is a drawing showing another example of the column signal processing circuit for the solid-state imaging device according to the present embodiment.
  • FIG. 6 is a drawing showing still another example of the column signal processing circuit for the solid-state imaging device according to the present embodiment.
  • FIG. 7 is a diagram illustrating an example for a solid-state imaging device and a reading method thereof.
  • FIG. 8 is a diagram illustrating another example for a solid-state imaging device and a reading method thereof.
  • FIG. 9 is a diagram illustrating an example of a circuit configuration of the signal processing unit.
  • FIG. 10 is a diagram illustrating still another example for a solid-state imaging device and a reading method thereof.
  • FIG. 11 is a diagram illustrating an example of a circuit configuration of the signal processing unit.
  • FIG. 12 is a diagram illustrating still another example for the solid-state imaging device and the reading method thereof.
  • FIG. 13 is a diagram illustrating an example of a circuit configuration of the signal processing unit.
  • FIG. 14 is a diagram illustrating an example of IIR filter characteristics.
  • FIG. 15 is a diagram illustrating main steps in a method of reading a signal from a pixel array of a solid-state imaging device.
  • the amplification type solid-state imaging device has a pixel having an amplification function and a scanning circuit arranged around the pixel, and reads pixel data from the pixel by the scanning circuit.
  • An example of an amplification type solid-state imaging device is an APS (Active Pixel Sensor) type image sensor composed of CMOS (Complementary Metal Oxide Semiconductor), which is advantageous for integration of pixels with peripheral drive circuits and signal processing circuits. is there.
  • An example of a pixel in the APS type image sensor is a four-transistor type pixel that can obtain high image quality.
  • the transistor can be, for example, a MIS type or a MOS type.
  • the solid-state imaging device according to the present embodiment can be applied to camera device equipment.
  • the camera device apparatus includes the solid-state imaging device according to the present embodiment.
  • FIG. 1 is a diagram showing a block configuration of a solid-state imaging device such as a two-dimensional image sensor.
  • the solid-state imaging device 1 includes a pixel array 3, a column signal processing unit 5, a reference signal generation unit 7, and a signal processing unit 9.
  • the pixels 11 are arranged in a matrix to form a pixel array 3.
  • the pixels 11 are connected to the column signal line C, and these pixels constitute a column arrangement.
  • a specific row is selected from the row of each pixel by the row decoder circuit 13a.
  • the row drive circuit 14 a provides a drive signal to the drive line 12.
  • the drive line 12 represents a transfer transistor drive line, a reset transistor drive line, and a row selection transistor drive line.
  • the reference signal generation unit 7 is selected by the reference row selection circuit 13b.
  • the row drive circuit 14b provides a drive signal to the drive line 25 to the reference signal generation unit.
  • the drive line 25 represents a reference row selection transistor drive line.
  • the solid-state imaging device 1 can include a timing generation circuit 10 that generates a control signal, a clock signal, and the like for controlling the operation timing of a circuit included in the device 1.
  • the pixel array 3 includes an array of pixels 11.
  • each pixel 11 includes a photoelectric conversion element 11a and a pixel circuit 11b.
  • the photoelectric conversion element 11a can include a photodiode, for example.
  • the photoelectric conversion element 11a converts the received light L into an electrical signal.
  • the pixel circuit 11b amplifies the signal S (ph) from the photoelectric conversion element 11a to provide a pixel signal S (pixel).
  • the pixel circuit 11b includes a transfer transistor TR (TF) that responds to a transfer signal, a reset transistor TR (RS) that responds to a reset signal, an amplification transistor TR (AM), and a switch transistor TR (SW) that responds to a row selection signal. including.
  • the pixel circuit 11b includes a floating diffusion portion FD.
  • the transfer transistor TR (TF) receives a transfer signal at its gate, and is connected between the photoelectric conversion element 11a and the floating diffusion portion FD.
  • the transfer transistor TR (TF) controls the transfer of charges from the photoelectric conversion element 11a to the floating diffusion portion FD.
  • the reset transistor TR (RS) is connected to the floating diffusion portion FD and resets the floating diffusion portion FD.
  • the amplification transistor TR (AM) receives a signal from the floating diffusion portion FD at its gate, and is connected between a reference potential line Vdd such as a power supply line and the column line C.
  • the switch transistor TR (SW) is connected in series to the amplification transistor TR (AM), and is connected between the reference potential line Vdd and the column line C.
  • the pixel circuit 11b provides the pixel signal S (pixel) to the column line C.
  • the reference signal generator 7 is arranged separately from the pixel array 3.
  • the reference signal generation unit 7 includes one or a plurality of reference circuits 7a.
  • FIG. 2 is a diagram illustrating a configuration of a reference circuit of the reference voltage generation unit.
  • the reference circuit 7a includes a pseudo signal source PSD for reducing column fixed pattern noise, and a switch that provides a pseudo signal S (psd) from the pseudo signal source PSD, for example, a switch transistor TR. (SW0) is included.
  • the pseudo signal source PSD of the reference circuit 7a does not include the photoelectric conversion element 11a and the floating diffusion portion FD, and includes a transistor which is an element unlike the photoelectric conversion element 11a.
  • the reference circuit 7a includes a transistor TR (PSD) corresponding to the amplification transistor, the gate of the transistor TR (PSD) is connected to a voltage source such as a power supply line Vdd, and the transistor TR (PSD) is referred to as a power supply line Vdd.
  • the reference potential line and the column line C are connected.
  • the transistor TR (PSD) and the transistor TR (SW0) are connected in series, and the node where the transistor TR (PSD) and the transistor TR (SW0) are connected together is biased via the transistor TR (PSD).
  • the transistors TR (SW0) and TR (PSD) having the same structure as the transistors TR (SW) and TR (AM) in the pixel 11 can be used, respectively.
  • the column signal processing unit 5 can read the pseudo signal S (psd) k times (1 ⁇ k) per frame.
  • the column signal processing unit 5 receives the pixel signal S (pixel) from the pixel 11 in the pixel array 3 and the pseudo signal S (psd) from the reference signal generation unit 7, and the pixel signal S
  • the imaging signal S (img) and the reference signal S (ref) are generated from (pixel) and the pseudo signal S (psd), respectively.
  • the column signal processing unit 5 performs, for example, at least one of correlated double sampling, A / D conversion, amplification, and sample and hold operations on the pixel signal S (pixel) and the pseudo signal S (psd). These processes can be analog or digital signal processing.
  • the signal processor 9 receives the imaging signal S (img) and the reference signal S (ref), and generates a readout signal S (OUT).
  • the readout signal S (OUT) of the signal processing unit 9 is generated by performing arithmetic processing for reducing column fixed pattern noise related to the column signal processing circuit 15 on the imaging signal S (img) using the reference signal S (ref). Is done.
  • the imaging signal S (img) and the reference signal S (ref) of the column signal processing unit 5 can be digital signals of a predetermined digital form. Signals for each column such as the imaging signal S (img) and the reference signal S (ref) are provided to the signal processing unit 9.
  • a signal for each column is provided to the horizontal signal line 17 by, for example, the column decoder circuit 16, and is output to the outside of the semiconductor element or the sensor block.
  • the column signal processing unit 5 can include a column decoder circuit 16 and a horizontal signal line 17.
  • the column signal processing circuit 15 generates the imaging signal S (img) and the reference signal S (ref) from the pixel signal S (pixel) and the pseudo signal S (psd), respectively. Therefore, the pixel signal S (pixel) and the pseudo signal S (psd) include column fixed pattern noise related to the column signal processing circuit 15. Since the signal processing unit 9 performs the above arithmetic processing on the imaging signal S (img) using the reference signal S (ref), the column fixed pattern noise is reduced in the readout signal S (OUT).
  • the pseudo signal source PSD does not include the photoelectric conversion element 11a and the floating diffusion portion FD, it is not necessary to shield the light, and the process of reducing the column fixing pattern noise is not affected by light leaked from the pixel array 3 or diffusion electrons. .
  • the general description is as follows.
  • S1 a portion in which the column signal processing circuit is generated from the pixel signal S (pixel);
  • R1 a portion in which the column signal processing circuit is generated from the pseudo signal S (psd);
  • N1 Column fixed pattern noise specific to the column signal processing circuit; N1_OB: Noise caused by leakage light, diffused electrons, and the like.
  • Column fixed pattern noise is removed.
  • the reference circuit 7a is not limited to the specific circuit shown in FIG. 2A, and its size, pattern, etc., correspond to the transistors TR (SW) and TR (AM) in the pixel 11.
  • Other circuits 7b and 7c having transistor characteristics matched to each other can also be used.
  • FIG. 2B is a diagram illustrating another example of the reference circuit.
  • the reference circuit 7b includes a pseudo signal source PSD for reducing column fixed pattern noise, and a switch transistor TR (SW0) that provides a pseudo signal S (psd) from the pseudo signal source PSD.
  • the reference circuit 7b generates the pseudo signal S (psd) using the two transistors 24 and TR (PSD).
  • Each transistor TR (SW0), 24, TR (PSD) can have the same structure as the transistors TR (SW), TR (RS), TR (AM) in the pixel circuit 11, respectively. It is desirable to match the geometric dimensions and orientations to match the current-voltage characteristics of the corresponding transistors.
  • the gate 27 of the transistor 24 is connected to a fixed potential (for example, Vdd line).
  • the gate of the transistor TR (PSD) is biased from the transistor 24 that is always conducting.
  • FIG. 2C is a diagram showing still another example of the reference circuit.
  • the gate of the transistor TR (PSD) is connected to the voltage source 29.
  • the pseudo signal source PSD includes a voltage source 29 and a transistor TR (PSD).
  • a voltage source 29 can be arranged in the reference circuit 7c. Since the reference potential level of the voltage source 29 can be set individually for each reference circuit 7c in accordance with the tendency of noise, the reference voltage level is set in accordance with the characteristic unique to the column.
  • FIG. 3 is a drawing showing an arrangement of reference circuits.
  • the reference signal generation unit 7 can include an array 21 of reference circuits.
  • the reference circuit 7d includes transistors TR (SW0) and TR (PSD).
  • the gate 33 of the transistor TR (PSD) is connected to a voltage source 32 that supplies a reference voltage in common in the row direction.
  • the voltage source 32 can be provided in the solid-state imaging device 1. If necessary, it can also be supplied from outside the solid-state imaging device 1.
  • the set potential of the voltage source 32 sets the level of the reference voltage in the column line C.
  • the reference circuits 7a, 7b, 7c and 7d can also be arranged for each column.
  • the reference circuits 7a to 7d can be arranged for each column, these reference circuits can be arranged over a plurality of rows. Alternatively, a single reference circuit may be provided in the solid-state imaging device 1 and shared by all column signal processing circuits. Further, the physical positions of the reference circuits 7a, 7b, 7c, and 7d are not particularly limited. If necessary, reference circuits 7a, 7b, 7c, and 7d can be provided inside and outside the column signal processing circuit. The nodes in the reference circuits 7a, 7b, 7c, 7d are biased directly by a voltage source or by a conducting transistor.
  • the pixel for the solid-state imaging device 1 is not limited to the pixel 11 shown in FIG.
  • the transfer transistor TR (TF) in the pixel 11 can be omitted, and the photoelectric conversion element 11a can be directly connected to the gate of the amplification transistor TR (AM).
  • the pixel having such an arrangement has a three-transistor pixel configuration.
  • the photoelectric conversion element 11a is configured by, for example, a photodiode, and the photodiode is manufactured by the same silicon manufacturing process as a transistor used as a circuit element in the solid-state imaging device 1. However, another manufacturing process (for example, a compound semiconductor such as GaAs) can be applied to manufacture the solid-state imaging device 1.
  • the photoelectric conversion element 11a can be manufactured using a photoconductive film such as a-Si or an organic film stacked on the pixel readout circuit in the solid-state imaging device 1.
  • a photoconductive film such as a-Si or an organic film stacked on the pixel readout circuit in the solid-state imaging device 1.
  • the floating diffusion portion FD is set to the reset potential by the reset transistor. Thereafter, the signal charge obtained by photoelectric conversion is accumulated in the floating diffusion portion FD. After this accumulation, the potential of the floating diffusion FD is amplified by the amplification transistor TR (AM) and provided to the column line C as a signal potential via the switch TR (SW). Further, immediately after that, the floating diffusion portion FD is reset by the conduction / non-conduction operation of the reset transistor TR (RS).
  • AM amplification transistor TR
  • SW switch TR
  • RS conduction / non-conduction operation of the reset transistor TR
  • the potential of the floating diffusion FD is amplified by the amplification transistor TR (AM) similarly to the signal potential, and is supplied to the column line C as the reset potential via the selection switch TR (SW0).
  • the pixel signal S (pixel) includes a first signal level including a noise component and a second signal level including a signal component superimposed on the noise component.
  • other amplifying pixels such as a 5-transistor pixel can be applied to the image sensor according to this embodiment.
  • FIG. 4 is a diagram illustrating an example of a column signal processing circuit for the solid-state imaging device according to the present embodiment.
  • the column signal processing circuit 15 may include a correlated double sampling (referred to as “CDS”) circuit 31.
  • the correlated double sampling circuit 31 reads out the pixel signal S (pixel) and the pseudo signal S (psd).
  • the pixel signal S (pixel) includes a first signal level S1 including a noise component and a second signal level S2 including a signal component superimposed on the noise component.
  • the imaging signal S (img) includes a difference between the first signal and the second signal.
  • the correlated double sampling circuit 31 includes switches 33a and 33b, capacitors 35a and 35b, and an operational amplifier circuit 37.
  • One input (negative input) 37a of the operational amplifier circuit 37 receives a signal from the input VIN via the switch 33a and the capacitor 35a connected in series, and the other input (positive input) 37b of the operational amplifier circuit 37 is common.
  • a reference signal (V COM ) is received.
  • a switch 33b and a capacitor 35b are connected in parallel between one input 37a of the operational amplifier circuit 37 and an output 37c of the operational amplifier circuit 37.
  • the output V OUT receives a signal from the output 37 c of the operational amplifier circuit 37.
  • the switch 33a controls the signal input operation, and the switch 33b controls the reset operation.
  • the solid-state imaging device 1 can include a CDS circuit 31 arranged in a column for each column arrangement.
  • the analog CDS results in a slight difference for each column due to variations in the characteristics of the capacitors 35a and 35b and the operational amplifier circuit 37. This is fixed to the column. It becomes pattern noise. According to this embodiment, column fixed pattern noise caused by the analog CDS circuit can be reduced.
  • FIG. 5 is a drawing showing another example of the column signal processing circuit for the solid-state imaging device according to the present embodiment.
  • the column signal processing circuit 15 can include a CDS circuit 31 and an A / D conversion circuit 41.
  • the A / D conversion circuit 41 receives a signal from the CDS circuit 31.
  • the A / D conversion circuit 41 A / D converts the analog CDS result to generate a first digital signal (digital imaging signal) S (ADC1).
  • the selection switch TR (SW) of the pixel 11 is opened, and the column arrangement of the pixel array 3 is separated from the column line C. Thereafter, the selection switch TR (SW0) in the reference circuits 7a to 7d in FIGS. 2 and 3 is turned on to connect the reference circuits 7a to 7d to the column line C.
  • the CDS circuit 31 closes the switches 33a and 33b and takes the pseudo signal S (psd) into the capacitor 35a. Thereafter, the switch 33b is opened while the switch 33a is closed.
  • the CDS circuit 31 generates a signal for the reference signal S (ref) that is associated with the pseudo signal S (psd).
  • the A / D conversion circuit 41 receives the pseudo signal S (psd) via the CDS circuit 31.
  • the A / D conversion circuit 41 takes in the signal on the output 37c of the operational amplifier circuit 37 as a pseudo signal level.
  • the A / D conversion circuit 41 A / D converts the pseudo signal level to generate a second digital signal (digital image pickup signal) S (ADC2).
  • ADC2 digital image pickup signal
  • the A / D conversion circuit 41 provides a digital reference signal and an imaging signal.
  • the column signal processing circuit 15 can include an A / D conversion circuit 41 without including the CDS circuit 31.
  • the column signal processing circuit 15 can include an A / D conversion circuit.
  • a cyclic A / D converter can provide a more efficient circuit configuration.
  • the cyclic A / D converter can provide an A / D conversion operation, and can also provide a CDS operation as required.
  • FIG. 6 is a drawing showing still another example of the column signal processing circuit for the solid-state imaging device according to the present embodiment.
  • the column signal processing circuit shown in FIG. 6 can constitute a circuit that performs CDS operation / amplification operation / A / D conversion operation using a single amplifier.
  • the column signal processing circuit 5 includes a cyclic A / D conversion circuit 51.
  • the cyclic A / D conversion circuit 51 can include first and second capacitors 43a and 43b, an operational amplifier circuit 45, a switch circuit 47, a D / A conversion circuit 48, and a comparator 49 (49a and 49b).
  • a reset switch 238 and a capacitor 43b of the switch circuit 47 are connected between one input 45a and the output 45c of the operational amplifier circuit 45.
  • a capacitor 43a connected in series and switches 234 and 235 of the switch circuit 47 are connected between one input 45a and the output 45c of the operational amplifier circuit 45.
  • the other input 45b of the operational amplifier circuit 45 is connected to the shared reference signal VCOM line.
  • One end of the capacitor 43 a is connected to the reference signal V COM line via the switch 236, and is connected to one input 45 a of the operational amplifier circuit 45 via the switch 235 of the switch circuit 47.
  • the other end of the capacitor 43a is connected to the D / A conversion circuit 48, is connected to the input VIN line via the switch 232 of the switch circuit 47, and is connected to the operational amplifier circuit 45 via the switch 234 of the switch circuit 47. Connected to output 45c.
  • the D / A conversion circuit 48 includes switches 240, 241, and 242.
  • the switches 240, 241, and 242 of the switch circuit 47 are D / A converted in response to the signals ⁇ M1 , ⁇ 01 , and ⁇ P1 from the comparator 49.
  • Voltage signals V RM , V COM , and V RP are switched as signals.
  • the switch circuit 47 changes the connection of the first capacitor 43a, the second capacitor 43b, and the operational amplifier circuit 45.
  • the switch circuit 47 can form a first connection that enables a correlated double sampling operation to the connection between the first and second capacitors 43a and 43b and the operational amplifier circuit 45.
  • the first and second capacitors A second connection that enables a cyclic A / D conversion operation can be formed between the capacitors 43 a and 43 b and the operational amplifier circuit 45.
  • the column signal processing circuit 5 can perform correlated double sampling by the first connection and cyclic A / D conversion by the second connection. According to this embodiment, column fixed pattern noise caused by the first capacitor 43a, the second capacitor 43b, the operational amplifier circuit 45, and the switch circuit 47 can be reduced.
  • the CDS operation in the circuit shown in FIG. 6 is possible by making the same element connection as the CDS circuit in FIG.
  • the connection method for the CDS operation in the switch circuit 47 is specifically as follows.
  • the switch 238 is opened while the switches 232 and 235 are closed, and the signal potential level S2 is taken from the pixel 11 into the capacitor 43a, so that the output 45c of the operational amplifier circuit 45 includes the reset level S1 and the signal level S2.
  • Difference that is, an analog CDS result.
  • the switches 234 and 236 are always opened during this operation.
  • the signal on the output 45c of the operational amplifier circuit 45 is subjected to 1.5-bit A / D conversion (sub A / D conversion) by the two comparators 49a and 49b. Using the result, an operation for A / D conversion of the next digit is performed. For this calculation, the switches 234 and 236 are closed to connect the capacitor 43a (C1) to the output 45c of the operational amplifier circuit 45, and all other switches are opened. Thereafter, the switches 234 and 236 are opened, and one end of the capacitor 43a (C1) is connected to the D / A conversion circuit 48, and the other end of the capacitor 43a (C1) is connected to the input 45a of the operational amplifier circuit 45 via the switch 235.
  • one of the switches 240, 241, and 242 When connected, one of the switches 240, 241, and 242 is turned on to generate a 1.5-bit A / D conversion residual signal.
  • This residual signal is stored in the capacitors 43a and 43b.
  • An arithmetic operation for A / D conversion of the next digit is performed on the residual signal. Residual generation and A / D conversion are repeated as many times as necessary.
  • the CDS circuit and the A / D converter can be integrated, and the operation equivalent to the circuit shown in FIG. can do.
  • the column signal processing circuit 5 can provide an amplification function together with the CDS function according to the capacitance ratio (C1 / C2) in the CDS operation performed before the A / D conversion.
  • the pixel array 3, the column signal processing unit 5, and the reference signal generation unit 7 can be integrated on a single semiconductor chip.
  • the signal processing unit 9 is provided outside the semiconductor chip, there is no limitation by integrating the signal processing unit 9 on a single semiconductor chip, and the signal processing unit can be provided in various forms.
  • the pixel array 3, the column signal processing unit 5, the reference signal generation unit 7, and the signal processing unit 9 can be integrated on a single semiconductor chip. At this time, a readout signal with reduced column fixed pattern noise is provided from the integrated circuit for the solid-state imaging device.
  • the signal processing unit 9 receives a digital reference signal and a digital imaging signal.
  • FIG. 7 is a diagram illustrating an example of a solid-state imaging device and a reading method thereof.
  • the 1H period of one frame of the pixel array 3 can include a first period 61a and a second period 61b.
  • the first period 61a the pixel signal S (pixel) for 1H is read from the pixels 11 of the pixel array 3.
  • the pseudo signal S (psd) is read from the reference signal generator 7.
  • the pixel signal S (pixel) from the pixels 11 in one row of the pixel array 3 is read out.
  • the pseudo signal S (psd) is read in all the column arrays. In one frame of the pixel array 3, readout of the pixel signal S (pixel) for one row and readout of the pseudo signal S (psd) are alternately performed. Therefore, since the pseudo signal S (psd) is read every 1H period, the value of the pseudo signal S (psd) updated every IH period is used to calculate the imaging signal S (img) for each row of the pixel array 3. Processing can be performed. Since the random noise of the pseudo signal S (psd) is different from the imaging signal S (img) for each row, generation of fixed pattern noise due to the random noise can be avoided.
  • the pixel signal S (pixel) read from the pixel array 3 is stored in a storage circuit such as a line memory (circuit 55a in FIG. 9A) during reading of the pseudo signal S (psd).
  • a storage circuit such as a line memory (circuit 55a in FIG. 9A) during reading of the pseudo signal S (psd).
  • the imaging signal S (img) is read from the storage circuit (the circuit 55a in FIG. 9) in the signal processing unit 9, A signal corresponding to the difference between the imaging signal S (img) and the reference signal S (ref) is generated.
  • the signal processing unit 9 includes an arithmetic circuit (circuit 55b in FIG. 9A) that performs arithmetic processing for this purpose.
  • a storage circuit such as a line memory (for example, the circuit 55a) is used to generate a signal indicating the difference.
  • a storage circuit such as a line memory (for example, the circuit 55a) is used to generate a signal indicating the difference.
  • the averaging process of the reference signal S (ref) does not allow the process to proceed smoothly.
  • the reference signal S (ref) It is desirable to perform an averaging process.
  • the pseudo signal S (psd) is stored in the memory circuit 55a), while the second period 61b is the second period 61b in the 1H period.
  • the pixel signal S (pixel) is stored in the memory circuit 55a). Therefore, when the pixel signal S (pixel) and the pseudo signal S (psd) are treated in the same way, they are equivalent. Further, when the allowable signal amplitude of the pseudo signal S (psd) can be made smaller than the pixel signal S (pixel), the former can reduce the capacity (the number of bits in the case of digital) of the memory circuit 55a).
  • FIG. 8 is a drawing showing another example of the solid-state imaging device and the readout method.
  • One frame of the pixel array 3 includes a plurality of first 1H periods 63a and a single second 1H period 63b.
  • the first 1H period 63a the pixel signal S (pixel) from the pixel 11 of the pixel array 3 is read.
  • the second 1H period 63b the pseudo signal S (psd) from the reference circuit 7a is read. Since the pseudo signal S (psd) is read from the reference circuit 7a in the single 1H period 63b, the frame rate can be increased. Except when necessary, the smoothing of the process is possible by not performing the averaging process of the reference signal S (psd).
  • the second 1H period 63b is located at the end of the one frame.
  • the arithmetic processing for the imaging signal S (img) in the one frame can be performed using the reference signal S (ref) in the immediately preceding frame.
  • This configuration is performed using a storage circuit such as a line memory (the circuit 56a in FIG. 9B).
  • the memory circuit (the circuit 56a in FIG. 9B) stores the common reference signal S (ref), and also receives the image signal S (img) sequentially input as the common reference signal S (ref). And is processed by the arithmetic circuit (the circuit 56b in FIG. 9B).
  • the imaging signal S (img) in the one frame using the reference signal S (ref) in the frame.
  • This mode is performed using a memory circuit such as a frame memory (the circuit 57a in FIG. 9C).
  • the memory circuit (the circuit 57a in FIG. 9C) stores the imaging signal S (img) for one pixel array read out earlier, and uses a common reference signal S (ref) read out later.
  • the stored imaging signals are sequentially processed by an arithmetic circuit (circuit 57b in FIG. 9C).
  • the second 1H period is located at the head of the one frame.
  • the arithmetic processing for the imaging signal in the one frame can be performed using the reference signal read out in the first 1H period.
  • This configuration is performed using a storage circuit such as a line memory (circuit 55a in FIG. 9A).
  • the reference signal is not changed over one frame and is a common value.
  • the memory circuit stores the common reference signal and processes the sequentially input imaging signals using the common reference signal (circuit 55b in FIG. 9A).
  • the second 1H period may be located away from the beginning and end of the one frame. Except when there is a special need, the smoothing of the process is possible by not performing the averaging process of the reference signal S (ref).
  • the column signal processing circuit 7 can read the pseudo signal S (psd) of the reference circuit 7a a plurality of times. According to the above aspect, the pseudo signal S (psd) from the reference circuit 7a is read a plurality of times at different times, which is useful for reducing random noise. Further, if necessary, the reference signal generation unit 7 can include an additional reference circuit (referred to as “additional reference circuit 7a”) having the same configuration as the reference circuit 7a. This additional reference circuit 7 a is connected to the column signal processing circuit 5. The reference signal generation unit 7 can read the pseudo signal S (psd) from the plurality of reference circuits 7a.
  • additional reference circuit 7a additional reference circuit having the same configuration as the reference circuit 7a. This additional reference circuit 7 a is connected to the column signal processing circuit 5.
  • the reference signal generation unit 7 can read the pseudo signal S (psd) from the plurality of reference circuits 7a.
  • the reference signal S (ref) can be generated by combining (for example, averaging) the pseudo signal S (psd) from the reference circuit 7a and the additional reference circuit 7a. Further, since the position of the reference circuit 7a is different from the position of the additional reference circuit 7a, variations of these reference circuits 7a can be averaged. Reading of the pseudo signal S (psd) from the reference circuit 7a is performed at a different time from reading of the pseudo signal S (psd) from the additional reference circuit, which helps to reduce random noise.
  • FIG. 10 is a drawing showing still another example of the solid-state imaging device and the readout method.
  • one frame of the pixel array 3 can include m first 1H periods 67a and k second 1H periods 67b.
  • the pixel signal S (pixel) from the pixel 11 of the pixel array 3 is read.
  • the pseudo signal S (psd) from the reference circuit 7a is read.
  • the m first 1H periods 67a are continuously arranged.
  • the k second 1H periods 67b are continuously arranged.
  • the reference signals S (ref) in the k second 1H periods 67b are averaged. This average random noise is reduced by 1 / sqrt (k).
  • sqrt represents a square root calculation.
  • the second 1H period 67b can be continuously arranged at the head of the one frame.
  • the arithmetic processing of the imaging signal S (img) is performed by the arithmetic circuit (the circuit 58a in FIG. 11A) using the average value of the reference signals S (ref) read in the k 1H periods 67b. be able to.
  • the average value generation of the reference signal S (ref) can be performed by an average value circuit (circuit 58b in FIG. 11A).
  • the second 1H period 67b is continuously arranged at the end of the one frame.
  • the arithmetic processing of the imaging signal S (img) in the frame is performed (see FIG. 11 ( This can be done with circuit 58a) of a).
  • the average value generation of the reference signal S (ref) can be performed by an average value circuit (circuit 58b in FIG. 11A). This average value is stored across frames.
  • the imaging signal S (img) in the frame is stored in a storage circuit such as a frame memory (the circuit 59b in FIG. 11B)
  • the average value of the reference signals read in k 1H periods in the frame Is generated.
  • the arithmetic processing of the imaging signal stored in the memory circuit for example, the circuit 59b in FIG. 11B
  • the arithmetic circuit the circuit 59a in FIG. 11B
  • the average value generation of the reference signal S (ref) can be performed by an average value circuit (circuit 59c in FIG. 11B).
  • the average value reduces random noise included in the reference signal.
  • the frame rate can be increased. There are the following forms for k readings: (a) repeatedly reading the same reference circuit; (b) sequentially reading different reference circuits; (c) reading a pseudo signal by a desired combination thereof.
  • the column signal processing unit 5 can read the pseudo signal k times (1 ⁇ k) per frame.
  • the signal processing unit 9 may include an average value generation circuit that performs an averaging process on the reference signal S (ref) to generate an average value.
  • the read signal S (OUT) indicates the difference between the imaging signal S (img) and the average value of the reference signal S (ref).
  • FIG. 12 is a drawing showing still another example of the solid-state imaging device and the readout method.
  • the signal processing unit 9 processes each of the reference signals S (ref) of all the columns in the column signal processing unit 5 over m frames to perform each column.
  • a digital filter that generates an average value may be included. According to averaging using digital filter processing, column fixed pattern noise can be reduced without deteriorating the frame rate.
  • the signal processing unit 9 can generate an average value by performing an averaging process over the last consecutive m frames before the nth frame (n> m). By performing the averaging process over the most recent m frames, it is possible to suppress the influence of noise that fluctuates slowly in time.
  • the reference signal S (ref) is averaged over a plurality of frames, the average random noise is reduced by 1 / sqrt (m) from the random noise included in the reference signal S (ref).
  • the read signal S (OUT) is generated using an average value over the most recent m frames.
  • the signal processing unit 9 can generate an average value by performing the averaging process over the initial m frames that are continuous from the first frame to the m frame.
  • the average random noise is reduced by 1 / sqrt (m) from the random noise included in the reference signal S (ref).
  • the read signal S (OUT) is generated using a fixed average value.
  • the averaging process over a plurality of frames is performed as follows, for example.
  • RF (1) to RF (m) in the 1st to mth frames RF (1) ⁇ AV (1) (AV (i ⁇ 1) + RF (i)) / 2 ⁇ AV (i) (2 ⁇ i ⁇ m) Perform the process. If necessary, the same processing can be performed in the (m + 1) th and later.
  • This processing is provided using the signal processing unit shown in FIG.
  • FIG. 13A shows an example of a system using digital filter hardware.
  • the signal processing unit 9 of the solid-state imaging device 1 performs a subtraction process on the digital imaging signal S (img) using the digital filter 60 applied to the digital reference signal S (ref) and the average value AV from the digital filter 60a. And an arithmetic circuit 60b.
  • FIG. 13B shows an example of connection of the digital filter circuit.
  • the digital filter circuit adds the signal y n ⁇ 1 obtained by delaying the filter output y n by the delay circuit D to the output of the arithmetic unit ALU by the adder ADD1 to generate the next filter output, and the signal y n ⁇ 1 is
  • the filter output y n ⁇ 1 is subtracted from the filter input x n on the input side of the arithmetic unit ALU (the complement of the filter output y n ⁇ 1 is added to the filter input x n by the adder ADD2), and the result is sent to the arithmetic unit a. Generate an input signal.
  • the calculation speed when obtaining the average value using the low-pass filter is greatly increased.
  • the hardware implementation becomes easy, and the coefficient can be changed on the hardware using a barrel shifter or the like. . Therefore, it is possible to realize a small scale, high speed and flexible hardware according to the system.
  • FIG. 15 is a drawing showing major steps in a method of reading a signal from a pixel array of a solid-state imaging device.
  • the pixel signal S (pixel) is read from the pixels 11 in the pixel array 3 by using the column signal processing circuit 15 to generate the imaging signal S (img).
  • the pseudo signal S (psd) for reducing the column fixed pattern noise is read using the column signal processing circuit 15 to generate the reference signal S (ref).
  • a calculation process for reducing the column fixed pattern noise related to the column signal processing circuit 15 is performed on the imaging signal S (img) using the reference signal S (ref) to generate a readout signal S (OUT).
  • the imaging signal S (img) and the reference signal S (ref) are generated from the pixel signal S (pixel) and the pseudo signal S (psd) using the same column signal processing circuit 15, respectively. Therefore, the imaging signal S (img) and the reference signal S (ref) include column fixed pattern noise related to the column signal processing circuit 15. Since the above calculation process is performed on the imaging signal S (img) using the reference signal S (ref), the column fixed pattern noise related to the column signal processing circuit 15 is reduced in the read signal S (OUT). Since the pseudo signal source S (psd) does not include a photoelectric conversion element, the column fixed pattern noise reduction process is not affected by leakage light from the pixel array 3 or diffused electrons.
  • the signal processing flow in the solid-state imaging device 1 is a digital imaging signal S (img) obtained by performing A / D conversion after reading out the pixel signal S (pixel) from the pixel 11 in the pixel array 3. That is, a step of generating the first digital data S (ADC1) is performed. Further, after reading the reference signal S (psd) from the reference circuit 7a, a step of generating an A / D converted digital reference signal S (ref), that is, second digital data S (ADC2) is performed. A step of directly providing the first digital data S (ADC1) to the arithmetic processing circuit 60b is performed.
  • a step of providing the second digital data S (ADC2) to the arithmetic processing circuit 60b via the digital filter 60a for averaging processing is performed.
  • the digital filter 60a performs a process of averaging the digital data S (ADC2) for m frames that are sequentially input for each frame.
  • a step of providing the filtered value ⁇ S (ADC2)> to the arithmetic processing circuit 60b is performed.
  • the arithmetic processing circuit 60b performs an arithmetic processing step (for example, S105) for generating a signal indicating a difference between the digital data S (ADC1)) and the average value ⁇ S (ADC2)> after m frames from the start of the operation.
  • the solid-state imaging device which can reduce column fixed pattern noise is received, without receiving the influence of the leak light from a pixel array, or a diffusion electron. Further, according to the present invention, a method for reading a signal from a pixel array of a solid-state imaging device is provided. According to this method, column fixed pattern noise can be reduced.
  • SYMBOLS 1 Solid-state imaging device, 3 ... Pixel array, 11 ... Pixel, 11a ... Photoelectric conversion element, 11b ... Pixel circuit, S (pixel) ... Pixel signal, C ... Column line, 7 ... Reference signal production

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Abstract

L'invention porte sur un dispositif d'imagerie à semi-conducteurs qui peut réduire le bruit cyclique fixe de colonne sans être touché par une diffusion d'électrons ou une fuite de lumière de la matrice de pixels. Un circuit de traitement de signal de colonne d'une unité de traitement de signal de colonne du dispositif d'imagerie à semi-conducteurs génère un signal d'image et un signal de référence à partir d'un signal de pixels provenant des pixels et à partir d'un signal faux provenant du circuit de référence, respectivement. Le signal de pixels et le signal faux contiennent un bruit cyclique fixe de colonne dudit circuit de traitement de signal de colonne. Etant donné que l'unité de traitement de signal effectue un traitement différentiel sur le signal d'image à l'aide du signal de référence, ledit bruit cyclique fixe de colonne diminue dans le signal de lecture. Etant donné que la source de signal faux ne contient pas d'éléments de conversion photoélectrique, le traitement de réduction du bruit cyclique fixe de colonne n'est pas touché par une diffusion d'électrons ni par une fuite de lumière de la matrice de pixels.
PCT/JP2011/051093 2010-01-26 2011-01-21 Dispositif d'imagerie à semi-conducteurs et procédé de lecture de signaux de matrice de pixels de dispositif d'imagerie à semi-conducteurs WO2011093225A1 (fr)

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