WO2011087003A1 - Three-dimensional packaging method and device - Google Patents
Three-dimensional packaging method and device Download PDFInfo
- Publication number
- WO2011087003A1 WO2011087003A1 PCT/JP2011/050304 JP2011050304W WO2011087003A1 WO 2011087003 A1 WO2011087003 A1 WO 2011087003A1 JP 2011050304 W JP2011050304 W JP 2011050304W WO 2011087003 A1 WO2011087003 A1 WO 2011087003A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- upper layer
- alignment
- sequentially
- recognized
- objects
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000004806 packaging method and process Methods 0.000 title abstract 5
- 238000010030 laminating Methods 0.000 abstract description 4
- 235000012431 wafers Nutrition 0.000 description 8
- 238000010586 diagram Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/75252—Means for applying energy, e.g. heating means in the upper part of the bonding apparatus, e.g. in the bonding head
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/75301—Bonding head
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/757—Means for aligning
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/757—Means for aligning
- H01L2224/75753—Means for optical alignment, e.g. sensors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/758—Means for moving parts
- H01L2224/75801—Lower part of the bonding apparatus, e.g. XY table
- H01L2224/75804—Translational mechanism
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/758—Means for moving parts
- H01L2224/75821—Upper part of the bonding apparatus, i.e. bonding head
- H01L2224/75824—Translational mechanism
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
- H01L2224/8113—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Definitions
- the present invention relates to a three-dimensional mounting method and apparatus for sequentially stacking and bonding objects to be bonded such as semiconductor elements in the vertical direction.
- a COC method Chip On Chip
- COW method Chip On Wafer
- a wafer there is a WOW method (Wafer On Wafer) in which wafers are sequentially stacked.
- the upper layer bonded object is sequentially laminated and bonded in a state in which the position of the electrode of the upper bonded object is aligned with the position of the electrode (including the bump) of the lower bonded object.
- the position of the lower object for example, the position of the electrode or the position of the alignment mark
- the position of the upper layer object to be stacked on the lower layer object to be recognized is aligned with the position of the lower object to be recognized by the camera), and the position of the upper layer object to be stacked is recognized from above by the recognition means.
- the upper layer bonded object sequentially laminated on the lowermost layer bonded object usually has one surface formed on the circuit surface and an electrode penetrating from the circuit surface to the back surface. After this circuit surface is the lower surface side, the electrodes are aligned with respect to the object to be bonded located below, and then laminated and bonded. The position of the bonded upper layer object is recognized from the back side opposite to the circuit surface, and the position of the upper layer object is further aligned and bonded based on the recognized position. Therefore, in the middle of stacking a plurality of upper layer bonded objects, the position of the stacked upper layer bonded objects must always be read and recognized from the back side.
- the circuit surface side is usually clean, and it is in a state where the position of the electrode and the position of the alignment mark for alignment can be clearly recognized.
- the mark shape or the like is usually not clearly imprinted or printed, and the mark is very small and is extremely difficult to read. Therefore, in the method of performing position recognition from the back side, recognition errors are likely to occur, and recognition errors such as alignment marks directly lead to deterioration in mounting accuracy. Further, in the case where mounting is performed based on the mark reference on the back surface of the upper layer bonded object, the mark errors are sequentially accumulated, so that the mounting shift with respect to the lowermost layer increases according to the number of layers.
- the object of the present invention is to focus on the problems in the conventional position recognition as described above, and to reliably and easily align the upper layer objects to be sequentially stacked with high accuracy.
- An object of the present invention is to provide a three-dimensional mounting method and apparatus capable of improving the mounting accuracy in a three-dimensional assembly state.
- the three-dimensional mounting method according to the present invention is a state in which a plurality of upper layer bonded objects having through electrodes are placed on the lowermost layer bonded objects having electrodes and the positions of the electrodes are aligned.
- the three-dimensional mounting method of sequentially stacking the position of alignment of the lowermost layer bonded object is recognized, and the electrodes sequentially position all upper layer bonded objects based on the recognized alignment position of the lowermost layer bonded object. It consists of the method characterized by sequentially laminating the upper layer objects to be joined at the predetermined positions while sequentially matching the predetermined positions to be connected.
- the alignment position of the lowermost layer object is recognized, and all the upper layer objects sequentially stacked on the basis of the position of the lowermost layer object.
- the alignment of the joint is performed sequentially. Therefore, no matter how many layers of the upper layer bonded object are stacked, the upper layer bonded object (the upper surface of the upper layer bonded object (the back surface opposite to the circuit surface) side) does not become a reference for alignment, There is no need to recognize the position on the hard-to-read surface.
- the alignment position of the upper-layer object to be aligned only needs to be recognized on the lower surface side (circuit surface side) and can be recognized with high accuracy.
- the first recognition means recognizes (recognizes from above) and stores the alignment position of the lowermost layer bonded object, and stores a plurality of upper layers.
- the second recognition means sequentially recognizes the alignment position of the object to be bonded (recognized from below), and the upper layer object whose alignment position has been recognized is stored in the alignment of the lowermost layer object to be stored. Stacking may be performed sequentially while aligning with the predetermined position sequentially with reference to the use position.
- the first recognizing unit and the second recognizing unit may be configured as a two-field recognizing unit having a visual field in the vertical direction, or may be configured as separate recognizing units.
- the alignment position of each object to be bonded it is possible to recognize the position of the electrode and the outer position of the object to be bonded, but formed in a specific shape (for example, a cross shape, etc.) If the mark given for alignment is recognized, it can contribute to the improvement of recognition accuracy.
- the alignment position of the lowermost layer bonded object is recognized by an alignment mark attached to the upper surface of the lowermost layer bonded object, and the alignment position of the plurality of upper layer bonded objects is determined for each upper layer bonded object. It can be recognized by an alignment mark attached to the lower surface of the object.
- each upper layer bonded object since the height of each upper layer bonded object sequentially changes as the stacking progresses, the upper layer bonded object held by the head or the like is stacked on the lowermost layer bonded object or the lowermost layer bonded object.
- the alignment position of the upper layer bonded object is preferably recognized by, for example, the second recognizing means when the upper layer bonded object is on the mounting position.
- the position for alignment of the upper layer bonded object (for example, the position of the upper layer bonded object with respect to the head holding the upper layer bonded object) is recognized in the middle of conveying the upper layer bonded object to the mounting position, and the Implementation can also be performed based on the recognition position. In this case, it is possible to eliminate the advance / retreat operation of the recognition means for recognizing the alignment position of the upper-layer workpiece at the mounting position, so that the time required for a series of processes from conveyance to mounting can be reduced. is there.
- an object to be bonded all forms and all kinds of objects to be bonded may be used as long as a plurality of upper layer bonded objects having through electrodes are three-dimensionally mounted on a lowermost layer bonded object having electrodes.
- An object can be used, and typically, an object to be bonded is made of a chip or a wafer. In this case, any of the above-described COC method, COW method, and WOW method can be applied.
- the present invention also provides a three-dimensional mounting apparatus. That is, the three-dimensional mounting apparatus according to the present invention is a three-dimensional mounting in which a plurality of upper layer objects having through electrodes are sequentially stacked on the lowermost object having electrodes.
- first recognition means for recognizing an alignment position of the lowermost layer bonded object held on a stage, a head for holding the upper layer bonded object sequentially stacked, and the lowermost layer bonded object Is recognized by the first recognizing means
- the second recognizing means for recognizing the alignment position of the upper layer object held by the head, and the first recognizing means.
- the position of all the upper layer objects to be recognized by the second recognizing means with respect to the alignment position of the lowermost object to be bonded is sequentially adjusted to a predetermined position where the electrodes are sequentially connected, position A mounting control means for stacking the Align obtained upper joining target sequence consists of those characterized by having a.
- the three-dimensional mounting apparatus includes a storage unit that stores the alignment position of the lowermost layer object recognized by the first recognition unit, and the mounting control unit sequentially uses the second recognition unit.
- the upper layer object to be recognized is sequentially stacked with the position of the recognized upper layer object being sequentially aligned with the predetermined position with reference to the alignment position of the lowermost layer object stored in the storage means. it can.
- the alignment position of the lowermost layer bonded object is recognized by an alignment mark attached to the upper surface of the lowermost layer bonded object
- the alignment positions of the plurality of upper layer bonded objects are It can be configured to be recognized by an alignment mark attached to the lower surface of the object.
- the mounting control means for each upper layer object to be sequentially stacked, the upper layer object to be mounted is changed so that the mounting height with respect to the position of the lowermost layer object in the stacking direction or the reference position corresponding thereto is changed. It is preferable to be configured to control the position in the stacking height direction.
- the second recognizing means preferably comprises means for recognizing the upper layer bonded object when the head holding the upper layer bonded object is on the mounting position.
- a typical object to be bonded can be a chip or a wafer.
- the three-dimensional mounting method and apparatus since all upper layer objects are sequentially aligned and stacked based on the recognition position of the lowermost layer object, each upper layer that is difficult to read as in the prior art. It becomes unnecessary to read the upper surface of the object to be joined, and high-precision positioning can be easily performed, so that the mounting accuracy can be greatly improved and the reliability of high-precision three-dimensional mounting can be improved.
- FIG. 1 shows a three-dimensional mounting apparatus according to an embodiment of the present invention.
- the three-dimensional mounting apparatus 1 includes a plurality of upper-layer chips 5 as upper-layer objects to be bonded, each having a through-electrode 4, and electrodes 2, 4, on a lower-layer chip 3 as a lower-layer object having electrodes 2. It consists of what laminates
- the three-dimensional mounting apparatus 1 recognizes the alignment position (for example, the position of the alignment mark) of the lowermost layer chip 3 held on the stage 6 (for example, held by suction).
- First recognition means and second recognition means for recognizing the alignment position (for example, the position of the alignment mark) of the upper chip 5 held by the head 7 (for example, the pressure / heating head).
- the first recognizing unit and the second recognizing unit are configured as a two-field camera 8 as a two-field recognizing unit having a field of view in two directions.
- the two-field camera 8 is provided between the lowermost lower layer chip 3 and the upper upper layer chip 5, that is, with respect to the mounting position of the upper layer chip 5, so that it can advance and retreat as necessary.
- the three-dimensional mounting apparatus 1 has moving means capable of controlling the relative position between the head 7 holding the upper layer chips 5 stacked sequentially and the stage 6 holding the lowermost layer chip 3.
- the upper layer chip 5 is aligned with the lowermost layer chip 3 by the control of the moving means.
- the position on the stage 6 side is controlled for this alignment, but the position on the head 7 side may be controlled, and the positions on both sides are controlled. You may comprise.
- the three-dimensional mounting apparatus 1 penetrates through the positions of all the upper layer chips 5 recognized by the second recognition unit with reference to the alignment position of the lowermost layer chip 3 recognized by the first recognition unit.
- a mounting control means 9 is provided for sequentially stacking the upper layer chip 5 aligned with the predetermined position on the lower layer while sequentially aligning with the predetermined position where the electrodes 4 are sequentially connected.
- the three-dimensional mounting is performed as shown in FIG. 3, for example.
- the alignment position (position of the alignment mark) of the lowermost chip 3 held on the stage 6 is recognized by the first recognition means (a camera having a field of view below the two-field camera 8), and the position. Information is stored in storage means in the mounting control means 9. Based on the alignment position information of the lowermost layer chip 3 stored in the storage means, the alignment of all the upper layer chips 5 that are sequentially stacked is sequentially performed.
- the alignment position of the upper chip 5 (the position of the alignment mark) is recognized by the second recognition means (a camera having a field of view above the two-field camera 8), and this recognition position information is stored in the storage means.
- the position of the upper layer chip 5 is controlled such that the positions of the electrodes 2 and 4 are matched with the alignment position information of the lowermost layer chip 3. Actually, since the position on the stage 6 side is controlled in this embodiment, the position control of the stage 6 is performed based on both position information.
- the upper layer chip 5 that is the uppermost layer does not necessarily have to be the through electrode 4 similar to the intermediate layer.
- the position recognition by the second recognition means (the camera having a field of view above the two-field camera 8) of the upper layer chip 5 is performed from the chip lower surface side at the mounting position.
- second recognition means having a configuration different from the above (for example, a camera having a field of view only upward) while the upper layer chip 5 held by the head 7 is being transported to the mounting position. It is also possible to recognize the alignment position in 11) and align the position of the lowermost layer chip 3 at the mounting position with reference to the recognized position information. In this way, since the reading time of the upper layer chip 5 can be reduced, the time of the entire three-dimensional mounting process having a series of operations can be shortened.
- the three-dimensional mounting method and apparatus according to the present invention can be applied to any three-dimensional mounting in which workpieces having electrodes are stacked in the vertical direction.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Supply And Installment Of Electrical Components (AREA)
Abstract
Disclosed is a three-dimensional packaging method for sequentially laminating a plurality of upper layers to be joined including feedthrough electrodes on a lowest layer to be joined including electrodes while the positions of the electrodes are adjusted with respect to each other, which comprises recognizing positions for alignment on the lowest layer to be joined; and sequentially adjusting the positions of all the upper layers to be joined at predetermined positions where the electrodes are sequentially connected with reference to the recognized positions for alignment on the lowest layer to be joined, and sequentially laminating the upper layers to be joined disposed at the predetermined positions. Also disclosed is a three-dimensional packaging device. Since all the upper layers to be joined are sequentially positioned and laminated with reference to the recognized positions on the lowest layer to be joined, the need for reading the upper surfaces of the upper layers to be joined, which are not easily read using conventional technology, is eliminated, and the layers can be easily and accurately positioned. As a result, packaging accuracy is significantly improved, and reliability of highly accurate three-dimensional packaging is also improved.
Description
本発明は、半導体素子等の被接合物を上下方向に順次積層して接合していく3次元実装方法および装置に関する。
The present invention relates to a three-dimensional mounting method and apparatus for sequentially stacking and bonding objects to be bonded such as semiconductor elements in the vertical direction.
半導体素子の3次元実装方法として、チップの上にチップを順次積層していくCOC工法(Chip On Chip)、ウエハーの上にチップを順次積層していくCOW工法(Chip On Wafer)、 ウエハーの上にウエハーを順次積層していくWOW工法(Wafer On Wafer)等がある。いずれの3次元実装方法においても、下層の被接合物の電極(バンプを含む)の位置に対し上層の被接合物の電極の位置を合わせた状態で上層被接合物を順次積層、接合していく必要がある(例えば特許文献1)。
As a three-dimensional mounting method of semiconductor elements, a COC method (Chip On Chip) in which chips are sequentially stacked on a chip, a COW method (Chip On Wafer) in which chips are sequentially stacked on a wafer, and a wafer In addition, there is a WOW method (Wafer On Wafer) in which wafers are sequentially stacked. In any of the three-dimensional mounting methods, the upper layer bonded object is sequentially laminated and bonded in a state in which the position of the electrode of the upper bonded object is aligned with the position of the electrode (including the bump) of the lower bonded object. (For example, patent document 1).
このような3次元実装においては、従来、上層被接合物を順次積層するに際し、下層の被接合物の位置(例えば、その電極の位置やアライメントマークの位置)を上方から認識手段(例えば、CCDカメラ)で認識し、認識した下層の被接合物の位置を基準にその上に積層される上層被接合物の位置を合わせ、積層した上層被接合物の位置を上方から認識手段で認識し、認識した被接合物の位置を基準にその上に積層される上層被接合物の位置を合わせ、これらの動作を必要回数順次繰り返すことで、順次積層されていく上層被接合物の位置合わせを行っていた。
In such a three-dimensional mounting, conventionally, when the upper layer objects are sequentially stacked, the position of the lower object (for example, the position of the electrode or the position of the alignment mark) is recognized from above (for example, a CCD). The position of the upper layer object to be stacked on the lower layer object to be recognized is aligned with the position of the lower object to be recognized by the camera), and the position of the upper layer object to be stacked is recognized from above by the recognition means. By aligning the position of the upper layer object to be laminated on the recognized position of the object to be joined and repeating these operations as many times as necessary, the position of the upper layer object to be sequentially laminated is adjusted. It was.
ところが、上記のように順次積層された上層被接合物の位置を基準にその上に積層されていく被接合物の位置合わせを行う方法には、以下のような問題がある。
すなわち、最下層の被接合物に対し順次積層されていく上層被接合物は、通常、一面が回路面に形成され、この回路面から裏面へと貫通する電極を有している。この回路面を下面側にして、その下方に位置している被接合物に対し電極同士の位置合わせを行った後、積層し接合していく。接合されたこの上層被接合物の位置を上記回路面とは反対側の裏面側から認識し、認識した位置を基準にさらに上層の被接合物の位置を合わせて、積層、接合していく。したがって、複数の上層被接合物を積層していく途中の段階では、積層された上層被接合物の位置を常に裏面側から読み取って認識しなければならない。 However, there are the following problems in the method of aligning the objects to be bonded stacked on the upper layer bonded objects sequentially stacked as described above.
That is, the upper layer bonded object sequentially laminated on the lowermost layer bonded object usually has one surface formed on the circuit surface and an electrode penetrating from the circuit surface to the back surface. After this circuit surface is the lower surface side, the electrodes are aligned with respect to the object to be bonded located below, and then laminated and bonded. The position of the bonded upper layer object is recognized from the back side opposite to the circuit surface, and the position of the upper layer object is further aligned and bonded based on the recognized position. Therefore, in the middle of stacking a plurality of upper layer bonded objects, the position of the stacked upper layer bonded objects must always be read and recognized from the back side.
すなわち、最下層の被接合物に対し順次積層されていく上層被接合物は、通常、一面が回路面に形成され、この回路面から裏面へと貫通する電極を有している。この回路面を下面側にして、その下方に位置している被接合物に対し電極同士の位置合わせを行った後、積層し接合していく。接合されたこの上層被接合物の位置を上記回路面とは反対側の裏面側から認識し、認識した位置を基準にさらに上層の被接合物の位置を合わせて、積層、接合していく。したがって、複数の上層被接合物を積層していく途中の段階では、積層された上層被接合物の位置を常に裏面側から読み取って認識しなければならない。 However, there are the following problems in the method of aligning the objects to be bonded stacked on the upper layer bonded objects sequentially stacked as described above.
That is, the upper layer bonded object sequentially laminated on the lowermost layer bonded object usually has one surface formed on the circuit surface and an electrode penetrating from the circuit surface to the back surface. After this circuit surface is the lower surface side, the electrodes are aligned with respect to the object to be bonded located below, and then laminated and bonded. The position of the bonded upper layer object is recognized from the back side opposite to the circuit surface, and the position of the upper layer object is further aligned and bonded based on the recognized position. Therefore, in the middle of stacking a plurality of upper layer bonded objects, the position of the stacked upper layer bonded objects must always be read and recognized from the back side.
しかし、このように順次積層されていく被接合物においては、通常、回路面側はきれいで、電極の位置や位置合わせ用のアライメントマークの位置を鮮明に認識することが可能な状態にあるが、裏面側は、通常、マーク形状等がきれいに刻印あるいはプリントされていないことが多く、そのマークも微小であり、極めて読み取りにくい状態にある。したがって、裏面側から位置認識を行う方法では、認識誤差が発生しやすく、アライメントマーク等の認識誤差は、直接、実装精度の悪化につながることとなっている。また、上層被接合物の裏面のマーク基準で実装した場合では、マーク誤差は順次累積されている形となるので積層数に従い、最下層に対する実装ズレも大きくなってくる。
However, in such an object to be sequentially laminated, the circuit surface side is usually clean, and it is in a state where the position of the electrode and the position of the alignment mark for alignment can be clearly recognized. On the back side, the mark shape or the like is usually not clearly imprinted or printed, and the mark is very small and is extremely difficult to read. Therefore, in the method of performing position recognition from the back side, recognition errors are likely to occur, and recognition errors such as alignment marks directly lead to deterioration in mounting accuracy. Further, in the case where mounting is performed based on the mark reference on the back surface of the upper layer bonded object, the mark errors are sequentially accumulated, so that the mounting shift with respect to the lowermost layer increases according to the number of layers.
そこで本発明の課題は、上記のような従来の位置認識における問題点に着目し、順次積層されていく上層被接合物を確実にかつ容易に高精度で位置合わせできるようにし、最終的な3次元組立状態での実装精度を向上可能な3次元実装方法および装置を提供することにある。
Accordingly, the object of the present invention is to focus on the problems in the conventional position recognition as described above, and to reliably and easily align the upper layer objects to be sequentially stacked with high accuracy. An object of the present invention is to provide a three-dimensional mounting method and apparatus capable of improving the mounting accuracy in a three-dimensional assembly state.
上記課題を解決するために、本発明に係る3次元実装方法は、電極を備えた最下層被接合物上に貫通電極を備えた複数の上層被接合物を電極同士の位置を合わせた状態で順次積層する3次元実装方法において、前記最下層被接合物のアライメント用位置を認識し、認識した最下層被接合物のアライメント用位置を基準にして全ての上層被接合物の位置を電極が順次接続されていく所定の位置に順次合わせつつ、所定の位置に合わせられた上層被接合物を順次積層することを特徴とする方法からなる。
In order to solve the above-described problem, the three-dimensional mounting method according to the present invention is a state in which a plurality of upper layer bonded objects having through electrodes are placed on the lowermost layer bonded objects having electrodes and the positions of the electrodes are aligned. In the three-dimensional mounting method of sequentially stacking, the position of alignment of the lowermost layer bonded object is recognized, and the electrodes sequentially position all upper layer bonded objects based on the recognized alignment position of the lowermost layer bonded object. It consists of the method characterized by sequentially laminating the upper layer objects to be joined at the predetermined positions while sequentially matching the predetermined positions to be connected.
このような本発明に係る3次元実装方法においては、まず、最下層被接合物のアライメント用位置が認識され、その最下層被接合物の位置を基準に、順次積層されていく全ての上層被接合物の位置合わせが順次行われる。したがって、上層被接合物が何層積層されても、上層被接合物が(上層被接合物の上面〔回路面とは反対側の裏面〕側が)位置合わせのための基準となることはなく、この読み取りにくい側の面に関して位置を認識する必要はない。位置合わせのための上層被接合物のアライメント用位置は、下面側(回路面側)の読み取りやすい面で、認識されればよく、高精度の認識が可能である。その結果、全ての上層被接合物が同一の最下層被接合物のアライメント用位置を基準にして位置合わせされ、かつ、それぞれの上層被接合物の位置合わせに際して各上層被接合物のアライメント用位置を読み取りやすい下面側(回路面側)で認識すればよいことになるので、位置合わせのための認識誤差の生じる余地が無くなり、実装誤差の発生が抑制されて、安定して極めて高精度の3次元実装が可能になる。
In such a three-dimensional mounting method according to the present invention, first, the alignment position of the lowermost layer object is recognized, and all the upper layer objects sequentially stacked on the basis of the position of the lowermost layer object. The alignment of the joint is performed sequentially. Therefore, no matter how many layers of the upper layer bonded object are stacked, the upper layer bonded object (the upper surface of the upper layer bonded object (the back surface opposite to the circuit surface) side) does not become a reference for alignment, There is no need to recognize the position on the hard-to-read surface. The alignment position of the upper-layer object to be aligned only needs to be recognized on the lower surface side (circuit surface side) and can be recognized with high accuracy. As a result, all the upper layer objects are aligned with reference to the alignment position of the same lower layer object, and each upper layer object is aligned for alignment. Can be recognized on the lower surface side (circuit surface side) that is easy to read, so that there is no room for recognition errors for alignment, the occurrence of mounting errors is suppressed, and stable and extremely accurate 3 Dimension implementation becomes possible.
上記本発明に係る3次元実装方法において、より具体的には、上記最下層被接合物のアライメント用位置を第1の認識手段で認識して(上方から認識して)記憶し、複数の上層被接合物のアライメント用位置を第2の認識手段で順次認識して(下方から認識して)、アライメント用位置が認識された上層被接合物を、記憶されている最下層被接合物のアライメント用位置を基準にして順次上記所定の位置に合わせつつ順次積層するようにすることができる。第1の認識手段と第2の認識手段は、上下方向に視野を有する2視野の認識手段に構成してもよく、別々の認識手段に構成してもよい。
In the three-dimensional mounting method according to the present invention, more specifically, the first recognition means recognizes (recognizes from above) and stores the alignment position of the lowermost layer bonded object, and stores a plurality of upper layers. The second recognition means sequentially recognizes the alignment position of the object to be bonded (recognized from below), and the upper layer object whose alignment position has been recognized is stored in the alignment of the lowermost layer object to be stored. Stacking may be performed sequentially while aligning with the predetermined position sequentially with reference to the use position. The first recognizing unit and the second recognizing unit may be configured as a two-field recognizing unit having a visual field in the vertical direction, or may be configured as separate recognizing units.
また、各被接合物のアライメント用位置の認識については、電極の位置や被接合物の外形位置を認識することも可能であるが、特定の形状(例えば、十字形状など)に形成された、アライメント用に付されたマークを認識するようにすれば、認識精度の向上に寄与できる。例えば、上記最下層被接合物のアライメント用位置を、該最下層被接合物の上面に付されたアライメント用マークにより認識し、上記複数の上層被接合物のアライメント用位置を、各上層被接合物の下面に付されたアライメント用マークにより認識するようにすることができる。
In addition, for the recognition of the alignment position of each object to be bonded, it is possible to recognize the position of the electrode and the outer position of the object to be bonded, but formed in a specific shape (for example, a cross shape, etc.) If the mark given for alignment is recognized, it can contribute to the improvement of recognition accuracy. For example, the alignment position of the lowermost layer bonded object is recognized by an alignment mark attached to the upper surface of the lowermost layer bonded object, and the alignment position of the plurality of upper layer bonded objects is determined for each upper layer bonded object. It can be recognized by an alignment mark attached to the lower surface of the object.
また、各上層被接合物の高さは、積層が進むにつれて順次変化していくので、ヘッド等に保持された上層被接合物を最下層被接合物上にまたは最下層被接合物に積層された上層被接合物上に積層する際の加圧等のための基準高さについては、積層の進行に伴って順次変更することが好ましい。すなわち、順次積層されていく上層被接合物毎に、積層方向における上記最下層被接合物の位置またはそれに相当する基準位置に対する実装高さを制御できるようにしておくことが好ましい。
In addition, since the height of each upper layer bonded object sequentially changes as the stacking progresses, the upper layer bonded object held by the head or the like is stacked on the lowermost layer bonded object or the lowermost layer bonded object. In addition, it is preferable to sequentially change the reference height for pressurization or the like when laminating on the upper layer bonded object as the lamination proceeds. That is, it is preferable to control the mounting height with respect to the position of the lowermost layer bonded object in the stacking direction or the reference position corresponding to the upper layer bonded object sequentially stacked.
また、上層被接合物のアライメント用位置の認識は、上層被接合物が実装位置上にあるときに上層被接合物を例えば上記第2の認識手段で認識することが好ましい。実装位置上で認識して、その認識にしたがって続いて実装することにより、実装誤差の入り込む余地が殆ど無くなり、実装精度の向上に寄与できる。ただし、例えば、上層被接合物を実装位置に搬送する途中で上層被接合物のアライメント用位置(例えば、上層被接合物を保持しているヘッドに対する上層被接合物の位置)を認識し、その認識位置に基づいて実装を行うようにすることもできる。この場合には、実装位置において上層被接合物のアライメント用位置の認識のための認識手段の進退動作を不要化可能であるので、搬送から実装までの一連の工程に要する時間の短縮が可能である。
Also, the alignment position of the upper layer bonded object is preferably recognized by, for example, the second recognizing means when the upper layer bonded object is on the mounting position. By recognizing on the mounting position and subsequently mounting according to the recognition, there is almost no room for mounting errors, which can contribute to improvement of mounting accuracy. However, for example, the position for alignment of the upper layer bonded object (for example, the position of the upper layer bonded object with respect to the head holding the upper layer bonded object) is recognized in the middle of conveying the upper layer bonded object to the mounting position, and the Implementation can also be performed based on the recognition position. In this case, it is possible to eliminate the advance / retreat operation of the recognition means for recognizing the alignment position of the upper-layer workpiece at the mounting position, so that the time required for a series of processes from conveyance to mounting can be reduced. is there.
本発明において、被接合物としては、電極を備えた最下層被接合物上に貫通電極を備えた複数の上層被接合物を3次元実装するものであれば、あらゆる形態、あらゆる種類の被接合物を使用可能であり、代表的には、被接合物がチップまたはウエハーからなる場合である。この場合、前述のCOC工法、COW工法、WOW工法のいずれも適用できる。
In the present invention, as an object to be bonded, all forms and all kinds of objects to be bonded may be used as long as a plurality of upper layer bonded objects having through electrodes are three-dimensionally mounted on a lowermost layer bonded object having electrodes. An object can be used, and typically, an object to be bonded is made of a chip or a wafer. In this case, any of the above-described COC method, COW method, and WOW method can be applied.
本発明は、3次元実装装置についても提供する。すなわち、本発明に係る3次元実装装置は、電極を備えた最下層被接合物上に貫通電極を備えた複数の上層被接合物を電極同士の位置を合わせた状態で順次積層する3次元実装装置において、ステージ上に保持された前記最下層被接合物のアライメント用位置を認識する第1の認識手段と、前記順次積層されていく上層被接合物を保持するヘッドと前記最下層被接合物を保持した前記ステージとの相対位置を制御可能な移動手段と、前記ヘッドに保持された上層被接合物のアライメント用位置を認識する第2の認識手段と、前記第1の認識手段で認識された最下層被接合物のアライメント用位置を基準にして前記第2の認識手段で認識される全ての上層被接合物の位置を電極が順次接続されていく所定の位置に順次合わせつつ、所定の位置に合わせられた上層被接合物を順次積層する実装制御手段と、を有することを特徴とするものからなる。
The present invention also provides a three-dimensional mounting apparatus. That is, the three-dimensional mounting apparatus according to the present invention is a three-dimensional mounting in which a plurality of upper layer objects having through electrodes are sequentially stacked on the lowermost object having electrodes. In the apparatus, first recognition means for recognizing an alignment position of the lowermost layer bonded object held on a stage, a head for holding the upper layer bonded object sequentially stacked, and the lowermost layer bonded object Is recognized by the first recognizing means, the second recognizing means for recognizing the alignment position of the upper layer object held by the head, and the first recognizing means. The position of all the upper layer objects to be recognized by the second recognizing means with respect to the alignment position of the lowermost object to be bonded is sequentially adjusted to a predetermined position where the electrodes are sequentially connected, position A mounting control means for stacking the Align obtained upper joining target sequence consists of those characterized by having a.
この3次元実装装置においては、上記第1の認識手段で認識された最下層被接合物のアライメント用位置を記憶する記憶手段を有し、上記実装制御手段は、上記第2の認識手段で順次認識される上層被接合物の位置をこの記憶手段に記憶されている最下層被接合物のアライメント用位置を基準にして順次前記所定の位置に合わせつつ上層被接合物を順次積層するように構成できる。
The three-dimensional mounting apparatus includes a storage unit that stores the alignment position of the lowermost layer object recognized by the first recognition unit, and the mounting control unit sequentially uses the second recognition unit. The upper layer object to be recognized is sequentially stacked with the position of the recognized upper layer object being sequentially aligned with the predetermined position with reference to the alignment position of the lowermost layer object stored in the storage means. it can.
また、上記最下層被接合物のアライメント用位置が、該最下層被接合物の上面に付されたアライメント用マークにより認識され、上記複数の上層被接合物のアライメント用位置が、各上層被接合物の下面に付されたアライメント用マークにより認識されるように構成できる。
In addition, the alignment position of the lowermost layer bonded object is recognized by an alignment mark attached to the upper surface of the lowermost layer bonded object, and the alignment positions of the plurality of upper layer bonded objects are It can be configured to be recognized by an alignment mark attached to the lower surface of the object.
また、上記実装制御手段としては、順次積層されていく上層被接合物毎に、積層方向における前記最下層被接合物の位置またはそれに相当する基準位置に対する実装高さを変えるように上層被接合物の積層高さ方向の位置を制御するように構成されていることが好ましい。
In addition, as the mounting control means, for each upper layer object to be sequentially stacked, the upper layer object to be mounted is changed so that the mounting height with respect to the position of the lowermost layer object in the stacking direction or the reference position corresponding thereto is changed. It is preferable to be configured to control the position in the stacking height direction.
また、上記第2の認識手段は、上層被接合物を保持するヘッドが実装位置上にあるときに上層被接合物を認識する手段からなることが好ましい。
The second recognizing means preferably comprises means for recognizing the upper layer bonded object when the head holding the upper layer bonded object is on the mounting position.
このような3次元実装装置においても、代表的な被接合物としてがチップまたはウエハーを挙げることができる。
Also in such a three-dimensional mounting apparatus, a typical object to be bonded can be a chip or a wafer.
本発明に係る3次元実装方法および装置によれば、最下層被接合物の認識位置を基準に全ての上層被接合物が順次位置合わせされ積層されていくので、従来のように読み取りにくい各上層被接合物の上面を読み取る必要がなくなり、高精度の位置合わせを容易に行うことができるようになり、実装精度の大幅な向上と高精度3次元実装の確実性の向上が可能になる。
According to the three-dimensional mounting method and apparatus according to the present invention, since all upper layer objects are sequentially aligned and stacked based on the recognition position of the lowermost layer object, each upper layer that is difficult to read as in the prior art. It becomes unnecessary to read the upper surface of the object to be joined, and high-precision positioning can be easily performed, so that the mounting accuracy can be greatly improved and the reliability of high-precision three-dimensional mounting can be improved.
以下に、本発明の望ましい実施の形態について、図面を参照しながら説明する。
図1は、本発明の一実施態様に係る3次元実装装置を示している。3次元実装装置1は、電極2を備えた最下層被接合物としての最下層チップ3上に、貫通電極4を備えた複数の上層被接合物としての上層チップ5を複数、電極2、4同士の位置を合わせた状態で順次積層するものからなる。3次元実装装置1は、図2にも示すように、ステージ6上に保持された(例えば、吸着保持された)最下層チップ3のアライメント用位置(例えば、アライメント用マークの位置)を認識する第1の認識手段と、ヘッド7(例えば、加圧・加熱ヘッド)に保持された上層チップ5のアライメント用位置(例えば、アライメント用マークの位置)を認識する第2の認識手段とを有しており、本実施態様では、第1の認識手段と第2の認識手段が上下2方向に視野を有する2視野認識手段としての2視野カメラ8として構成されている。2視野カメラ8は、下方の最下層チップ3と上方の上層チップ5との間に、つまり、上層チップ5の実装位置に対し、必要に応じて進退できるように設けられている。 Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a three-dimensional mounting apparatus according to an embodiment of the present invention. The three-dimensional mounting apparatus 1 includes a plurality of upper-layer chips 5 as upper-layer objects to be bonded, each having a through-electrode 4, and electrodes 2, 4, on a lower-layer chip 3 as a lower-layer object having electrodes 2. It consists of what laminates | stacks sequentially in the state which mutually adjusted the position. As shown also in FIG. 2, the three-dimensional mounting apparatus 1 recognizes the alignment position (for example, the position of the alignment mark) of the lowermost layer chip 3 held on the stage 6 (for example, held by suction). First recognition means and second recognition means for recognizing the alignment position (for example, the position of the alignment mark) of the upper chip 5 held by the head 7 (for example, the pressure / heating head). In this embodiment, the first recognizing unit and the second recognizing unit are configured as a two-field camera 8 as a two-field recognizing unit having a field of view in two directions. The two-field camera 8 is provided between the lowermost lower layer chip 3 and the upper upper layer chip 5, that is, with respect to the mounting position of the upper layer chip 5, so that it can advance and retreat as necessary.
図1は、本発明の一実施態様に係る3次元実装装置を示している。3次元実装装置1は、電極2を備えた最下層被接合物としての最下層チップ3上に、貫通電極4を備えた複数の上層被接合物としての上層チップ5を複数、電極2、4同士の位置を合わせた状態で順次積層するものからなる。3次元実装装置1は、図2にも示すように、ステージ6上に保持された(例えば、吸着保持された)最下層チップ3のアライメント用位置(例えば、アライメント用マークの位置)を認識する第1の認識手段と、ヘッド7(例えば、加圧・加熱ヘッド)に保持された上層チップ5のアライメント用位置(例えば、アライメント用マークの位置)を認識する第2の認識手段とを有しており、本実施態様では、第1の認識手段と第2の認識手段が上下2方向に視野を有する2視野認識手段としての2視野カメラ8として構成されている。2視野カメラ8は、下方の最下層チップ3と上方の上層チップ5との間に、つまり、上層チップ5の実装位置に対し、必要に応じて進退できるように設けられている。 Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a three-dimensional mounting apparatus according to an embodiment of the present invention. The three-dimensional mounting apparatus 1 includes a plurality of upper-
3次元実装装置1は、上記順次積層されていく上層チップ5を保持する上記ヘッド7と上記最下層チップ3を保持した上記ステージ6との相対位置を制御可能な移動手段を有しており、該移動手段の制御により、最下層チップ3に対して上層チップ5が位置合わせされる。本実施態様では、この位置合わせのために、ステージ6側の位置が制御されるようになっているが、ヘッド7側の位置が制御されるように構成してもよく、両側の位置が制御されるように構成してもよい。
The three-dimensional mounting apparatus 1 has moving means capable of controlling the relative position between the head 7 holding the upper layer chips 5 stacked sequentially and the stage 6 holding the lowermost layer chip 3. The upper layer chip 5 is aligned with the lowermost layer chip 3 by the control of the moving means. In this embodiment, the position on the stage 6 side is controlled for this alignment, but the position on the head 7 side may be controlled, and the positions on both sides are controlled. You may comprise.
そして、3次元実装装置1は、上記第1の認識手段で認識された最下層チップ3のアライメント用位置を基準にして上記第2の認識手段で認識される全ての上層チップ5の位置を貫通電極4が順次接続されていく所定の位置に順次合わせつつ、所定の位置に合わせられた上層チップ5をその下層に順次積層していく実装制御手段9を有している。
Then, the three-dimensional mounting apparatus 1 penetrates through the positions of all the upper layer chips 5 recognized by the second recognition unit with reference to the alignment position of the lowermost layer chip 3 recognized by the first recognition unit. A mounting control means 9 is provided for sequentially stacking the upper layer chip 5 aligned with the predetermined position on the lower layer while sequentially aligning with the predetermined position where the electrodes 4 are sequentially connected.
3次元実装は、例えば図3に示すように行われる。
まず、ステージ6上に保持されている最下層チップ3のアライメント用位置(アライメント用マークの位置)が第1の認識手段(2視野カメラ8の下方に視野を有するカメラ)で認識され、その位置情報が実装制御手段9内の記憶手段に記憶される。この記憶手段に記憶された最下層チップ3のアライメント用位置情報を基準に、順次積層されていく全ての上層チップ5の位置合わせが順次行われる。上層チップ5のアライメント用位置(アライメント用マークの位置)は、第2の認識手段(2視野カメラ8の上方に視野を有するカメラ)で認識され、この認識位置情報が上記記憶手段に記憶された最下層チップ3のアライメント用位置情報と突き合わされ、電極2、4同士の位置が合うように、上層チップ5の位置が制御される。実際には、本実施態様ではステージ6側の位置が制御されるので、両位置情報に基づいて、ステージ6の位置制御が行われる。 The three-dimensional mounting is performed as shown in FIG. 3, for example.
First, the alignment position (position of the alignment mark) of thelowermost chip 3 held on the stage 6 is recognized by the first recognition means (a camera having a field of view below the two-field camera 8), and the position. Information is stored in storage means in the mounting control means 9. Based on the alignment position information of the lowermost layer chip 3 stored in the storage means, the alignment of all the upper layer chips 5 that are sequentially stacked is sequentially performed. The alignment position of the upper chip 5 (the position of the alignment mark) is recognized by the second recognition means (a camera having a field of view above the two-field camera 8), and this recognition position information is stored in the storage means. The position of the upper layer chip 5 is controlled such that the positions of the electrodes 2 and 4 are matched with the alignment position information of the lowermost layer chip 3. Actually, since the position on the stage 6 side is controlled in this embodiment, the position control of the stage 6 is performed based on both position information.
まず、ステージ6上に保持されている最下層チップ3のアライメント用位置(アライメント用マークの位置)が第1の認識手段(2視野カメラ8の下方に視野を有するカメラ)で認識され、その位置情報が実装制御手段9内の記憶手段に記憶される。この記憶手段に記憶された最下層チップ3のアライメント用位置情報を基準に、順次積層されていく全ての上層チップ5の位置合わせが順次行われる。上層チップ5のアライメント用位置(アライメント用マークの位置)は、第2の認識手段(2視野カメラ8の上方に視野を有するカメラ)で認識され、この認識位置情報が上記記憶手段に記憶された最下層チップ3のアライメント用位置情報と突き合わされ、電極2、4同士の位置が合うように、上層チップ5の位置が制御される。実際には、本実施態様ではステージ6側の位置が制御されるので、両位置情報に基づいて、ステージ6の位置制御が行われる。 The three-dimensional mounting is performed as shown in FIG. 3, for example.
First, the alignment position (position of the alignment mark) of the
全ての上層チップ5の位置が同様に位置合わせされるので、たとえ上層チップ5が何層積層される場合にあっても、全ての上層チップ5が、同一の最下層チップ3のアライメント用位置を基準に位置合わせされることになる。したがって、従来のように、順次積層されていく各上層チップ5の各上面側からの読み取り位置情報(つまり、きれいでないので読み取りにくい位置の情報)が位置合わせのために用いられることは必要なくなる。各上層チップ5の位置情報としては、読み取りやすい下面側を第2の認識手段で読み取った位置情報が用いられるので、上記位置合わせの際の誤差の発生が抑制され、位置合わせ精度、ひいてはヘッド7を下降させて行う実装の精度が大幅に向上されるとともに、所望の3次元実装を行うための確実性が大幅に向上し、実装工程の安定性、信頼性向上にも寄与できる。
Since the positions of all the upper layer chips 5 are aligned in the same manner, even if the upper layer chips 5 are stacked, all the upper layer chips 5 have the same position for alignment of the lowermost layer chip 3. It will be aligned with the reference. Therefore, unlike the conventional technique, it is not necessary to use the read position information from each upper surface side of each upper layer chip 5 that is sequentially stacked (that is, information on a position that is difficult to read because it is not clean) for alignment. As the position information of each upper layer chip 5, position information obtained by reading the lower surface side that is easy to read by the second recognition means is used, so that the occurrence of errors during the above-described alignment is suppressed, and the alignment accuracy and thus the head 7. The accuracy of mounting performed by lowering the height is greatly improved, the certainty for performing desired three-dimensional mounting is greatly improved, and it is possible to contribute to the stability and reliability of the mounting process.
なお、最上層となる上層チップ5については、必ずしも途中層と同様の貫通電極4である必要はない。
Note that the upper layer chip 5 that is the uppermost layer does not necessarily have to be the through electrode 4 similar to the intermediate layer.
また、上記実施態様においては、上層チップ5の第2の認識手段(2視野カメラ8の上方に視野を有するカメラ)による位置認識を実装位置にてチップ下面側から行うようにしたが、例えば図4に示すように、ヘッド7に保持された上層チップ5が実装位置へと搬送されてくる途中で、上記とは別の構成を有する第2の認識手段(例えば、上方にのみ視野を有するカメラ11)でアライメント用位置を認識し、その認識位置情報を用いて実装位置で最下層チップ3のアライメント用位置を基準に位置合わせすることも可能である。このようにすれば、上層チップ5の読み取り時間を低減可能であるので、一連の動作を有する3次元実装工程全体の時間短縮が可能となる。
In the above embodiment, the position recognition by the second recognition means (the camera having a field of view above the two-field camera 8) of the upper layer chip 5 is performed from the chip lower surface side at the mounting position. 4, second recognition means having a configuration different from the above (for example, a camera having a field of view only upward) while the upper layer chip 5 held by the head 7 is being transported to the mounting position. It is also possible to recognize the alignment position in 11) and align the position of the lowermost layer chip 3 at the mounting position with reference to the recognized position information. In this way, since the reading time of the upper layer chip 5 can be reduced, the time of the entire three-dimensional mounting process having a series of operations can be shortened.
本発明に係る3次元実装方法および装置は、電極を備えた被接合物を上下方向に積層していくあらゆる3次元実装に適用可能である。
The three-dimensional mounting method and apparatus according to the present invention can be applied to any three-dimensional mounting in which workpieces having electrodes are stacked in the vertical direction.
1 3次元実装装置
2 電極
3 最下層被接合物としての最下層チップ
4 貫通電極
5 上層被接合物としての上層チップ
6 ステージ
7 ヘッド
8 第1の認識手段と第2の認識手段を備えた2視野認識手段としての2視野カメラ
9 実装制御手段
11 第2の認識手段としてのカメラ DESCRIPTION OF SYMBOLS 13D mounting apparatus 2 Electrode 3 Lower layer chip | tip 4 as a lower layer to-be-joined object Through electrode 5 Upper layer chip | tip as an upper layer to-be-joined object 6 Stage 7 Head 8 2 provided with the 1st recognition means and the 2nd recognition means Two-view camera 9 as field recognition means Mounting control means 11 Camera as second recognition means
2 電極
3 最下層被接合物としての最下層チップ
4 貫通電極
5 上層被接合物としての上層チップ
6 ステージ
7 ヘッド
8 第1の認識手段と第2の認識手段を備えた2視野認識手段としての2視野カメラ
9 実装制御手段
11 第2の認識手段としてのカメラ DESCRIPTION OF SYMBOLS 1
Claims (12)
- 電極を備えた最下層被接合物上に貫通電極を備えた複数の上層被接合物を電極同士の位置を合わせた状態で順次積層する3次元実装方法において、前記最下層被接合物のアライメント用位置を認識し、認識した最下層被接合物のアライメント用位置を基準にして全ての上層被接合物の位置を電極が順次接続されていく所定の位置に順次合わせつつ、所定の位置に合わせられた上層被接合物を順次積層することを特徴とする3次元実装方法。 In a three-dimensional mounting method of sequentially stacking a plurality of upper layer objects having through electrodes on a lower layer object having electrodes, with the positions of the electrodes aligned, for alignment of the lower layer object Recognize the position and adjust the position of all upper layer objects to the predetermined position while sequentially aligning the positions of all the upper layer objects to the predetermined positions where the electrodes are sequentially connected based on the recognized position for alignment of the lowest layer object. In addition, a three-dimensional mounting method characterized by sequentially stacking upper layer objects.
- 前記最下層被接合物のアライメント用位置を第1の認識手段で認識して記憶し、複数の上層被接合物のアライメント用位置を第2の認識手段で順次認識して、アライメント用位置が認識された上層被接合物を、記憶されている最下層被接合物のアライメント用位置を基準にして順次前記所定の位置に合わせつつ順次積層する、請求項1に記載の3次元実装方法。 The first recognition means recognizes and stores the alignment position of the lowermost layer bonded object, and the second recognition means sequentially recognizes the alignment positions of the plurality of upper layer bonded objects to recognize the alignment position. The three-dimensional mounting method according to claim 1, wherein the upper layer bonded objects are sequentially stacked while being sequentially aligned with the predetermined position with reference to the stored alignment position of the lowermost layer bonded object.
- 前記最下層被接合物のアライメント用位置を、該最下層被接合物の上面に付されたアライメント用マークにより認識し、前記複数の上層被接合物のアライメント用位置を、各上層被接合物の下面に付されたアライメント用マークにより認識する、請求項1または2に記載の3次元実装方法。 The position for alignment of the lowermost layer bonded object is recognized by an alignment mark attached to the upper surface of the lowermost layer bonded object, and the alignment position of the plurality of upper layer bonded objects is determined for each upper layer bonded object. The three-dimensional mounting method according to claim 1, wherein the three-dimensional mounting method is recognized by an alignment mark attached to the lower surface.
- 順次積層されていく上層被接合物毎に、積層方向における前記最下層被接合物の位置またはそれに相当する基準位置に対する実装高さを制御する、請求項1~3のいずれかに記載の3次元実装方法。 The three-dimensional according to any one of claims 1 to 3, wherein a mounting height with respect to a position of the lowermost layer bonded object in the stacking direction or a reference position corresponding thereto is controlled for each upper layer bonded object sequentially stacked. Implementation method.
- 上層被接合物が実装位置上にあるときに上層被接合物を第2の認識手段で認識する、請求項2~4のいずれかに記載の3次元実装方法。 5. The three-dimensional mounting method according to claim 2, wherein the upper layer object is recognized by the second recognition means when the upper layer object is on the mounting position.
- 前記被接合物がチップまたはウエハーからなる、請求項1~5のいずれかに記載の3次元実装方法。 The three-dimensional mounting method according to any one of claims 1 to 5, wherein the object to be joined is made of a chip or a wafer.
- 電極を備えた最下層被接合物上に貫通電極を備えた複数の上層被接合物を電極同士の位置を合わせた状態で順次積層する3次元実装装置において、ステージ上に保持された前記最下層被接合物のアライメント用位置を認識する第1の認識手段と、前記順次積層されていく上層被接合物を保持するヘッドと前記最下層被接合物を保持した前記ステージとの相対位置を制御可能な移動手段と、前記ヘッドに保持された上層被接合物のアライメント用位置を認識する第2の認識手段と、前記第1の認識手段で認識された最下層被接合物のアライメント用位置を基準にして前記第2の認識手段で認識される全ての上層被接合物の位置を電極が順次接続されていく所定の位置に順次合わせつつ、所定の位置に合わせられた上層被接合物を順次積層する実装制御手段と、を有することを特徴とする3次元実装装置。 In the three-dimensional mounting apparatus for sequentially stacking a plurality of upper layer bonded objects having through electrodes on a lower layer bonded object having electrodes, with the positions of the electrodes aligned, the lowermost layer held on a stage The relative position between the first recognition means for recognizing the alignment position of the object to be bonded, the head that holds the sequentially stacked upper layer objects to be bonded, and the stage that holds the lowermost layer object can be controlled. And a second recognition means for recognizing the alignment position of the upper-layer workpiece held by the head, and the alignment position of the lower-layer workpiece to be recognized recognized by the first recognition means. In this manner, the upper layer objects to be recognized that are recognized by the second recognition means are sequentially aligned with the predetermined positions where the electrodes are sequentially connected, and the upper layer objects to be aligned at the predetermined positions are sequentially stacked. Do 3-dimensional mounting apparatus comprising: the instrumentation control means.
- 前記第1の認識手段で認識された最下層被接合物のアライメント用位置を記憶する記憶手段を有し、前記実装制御手段は、前記第2の認識手段で順次認識される上層被接合物の位置を前記記憶手段に記憶されている最下層被接合物のアライメント用位置を基準にして順次前記所定の位置に合わせつつ上層被接合物を順次積層する、請求項7に記載の3次元実装装置。 Storage means for storing the alignment position of the lowermost layer object recognized by the first recognition means; and the mounting control means for the upper layer object to be sequentially recognized by the second recognition means. The three-dimensional mounting apparatus according to claim 7, wherein the upper layer objects are sequentially stacked while the positions are sequentially adjusted to the predetermined position with reference to the alignment position of the lowermost layer object stored in the storage means. .
- 前記最下層被接合物のアライメント用位置が、該最下層被接合物の上面に付されたアライメント用マークにより認識され、前記複数の上層被接合物のアライメント用位置が、各上層被接合物の下面に付されたアライメント用マークにより認識される、請求項7または8に記載の3次元実装装置。 The alignment position of the lowermost layer bonded object is recognized by an alignment mark attached to the upper surface of the lowermost layer bonded object, and the alignment position of the plurality of upper layer bonded objects is the position of each upper layer bonded object. The three-dimensional mounting apparatus according to claim 7 or 8, which is recognized by an alignment mark attached to a lower surface.
- 前記実装制御手段は、順次積層されていく上層被接合物毎に、積層方向における前記最下層被接合物の位置またはそれに相当する基準位置に対する実装高さを変えるように上層被接合物の積層高さ方向の位置を制御する、請求項7~9のいずれかに記載の3次元実装装置。 The mounting control means is configured to change the stacking height of the upper layer bonded object so as to change the mounting height with respect to the position of the lowermost layer bonded object in the stacking direction or a reference position corresponding thereto for each upper layer bonded object sequentially stacked. The three-dimensional mounting apparatus according to any one of claims 7 to 9, which controls a position in a vertical direction.
- 前記第2の認識手段は、上層被接合物を保持するヘッドが実装位置上にあるときに上層被接合物を認識する、請求項7~10のいずれかに記載の3次元実装装置。 The three-dimensional mounting apparatus according to any one of claims 7 to 10, wherein the second recognizing means recognizes the upper layer bonded object when the head holding the upper layer bonded object is on the mounting position.
- 前記被接合物がチップまたはウエハーからなる、請求項7~11のいずれかに記載の3次元実装装置。 The three-dimensional mounting apparatus according to any one of claims 7 to 11, wherein the object to be joined is made of a chip or a wafer.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011549979A JP5984394B2 (en) | 2010-01-15 | 2011-01-12 | Three-dimensional mounting method and apparatus |
KR1020127015218A KR101802173B1 (en) | 2010-01-15 | 2011-01-12 | Three-dimensional packaging method and device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010-006897 | 2010-01-15 | ||
JP2010006897 | 2010-01-15 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2011087003A1 true WO2011087003A1 (en) | 2011-07-21 |
Family
ID=44304277
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2011/050304 WO2011087003A1 (en) | 2010-01-15 | 2011-01-12 | Three-dimensional packaging method and device |
Country Status (4)
Country | Link |
---|---|
JP (1) | JP5984394B2 (en) |
KR (1) | KR101802173B1 (en) |
TW (1) | TWI506717B (en) |
WO (1) | WO2011087003A1 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2013187292A1 (en) * | 2012-06-11 | 2013-12-19 | 株式会社新川 | Bonding device and method for producing semiconductor device |
JP2014187220A (en) * | 2013-03-25 | 2014-10-02 | Toshiba Corp | Semiconductor device manufacturing method |
WO2015079991A1 (en) * | 2013-11-27 | 2015-06-04 | 東レエンジニアリング株式会社 | Three-dimensional mounting method and three-dimensional mounting device |
CN110383446A (en) * | 2017-03-16 | 2019-10-25 | Ev 集团 E·索尔纳有限责任公司 | The method for being adapted to couple to few three substrates |
JP2020136389A (en) * | 2019-02-15 | 2020-08-31 | 日本放送協会 | Stacked semiconductor integrated circuit and its manufacturing method |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014187185A (en) * | 2013-03-22 | 2014-10-02 | Renesas Electronics Corp | Semiconductor device manufacturing method |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004273525A (en) * | 2003-03-05 | 2004-09-30 | Seiko Epson Corp | Semiconductor device manufacturing method, semiconductor device, and electronic equipment |
JP2005183580A (en) * | 2003-12-18 | 2005-07-07 | Seiko Epson Corp | Semiconductor device manufacturing method, semiconductor device, circuit board, electronic device |
JP2007194491A (en) * | 2006-01-20 | 2007-08-02 | Renesas Technology Corp | Semiconductor device, manufacturing method thereof, and interposer chip |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8367471B2 (en) * | 2007-06-15 | 2013-02-05 | Micron Technology, Inc. | Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies and stacked semiconductor devices |
-
2011
- 2011-01-12 WO PCT/JP2011/050304 patent/WO2011087003A1/en active Application Filing
- 2011-01-12 KR KR1020127015218A patent/KR101802173B1/en active Active
- 2011-01-12 JP JP2011549979A patent/JP5984394B2/en active Active
- 2011-01-14 TW TW100101395A patent/TWI506717B/en active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004273525A (en) * | 2003-03-05 | 2004-09-30 | Seiko Epson Corp | Semiconductor device manufacturing method, semiconductor device, and electronic equipment |
JP2005183580A (en) * | 2003-12-18 | 2005-07-07 | Seiko Epson Corp | Semiconductor device manufacturing method, semiconductor device, circuit board, electronic device |
JP2007194491A (en) * | 2006-01-20 | 2007-08-02 | Renesas Technology Corp | Semiconductor device, manufacturing method thereof, and interposer chip |
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9385104B2 (en) | 2012-06-11 | 2016-07-05 | Shinkawa Ltd. | Bonding apparatus |
JP2014017471A (en) * | 2012-06-11 | 2014-01-30 | Shinkawa Ltd | Bonding apparatus and bonding method |
KR20140117543A (en) * | 2012-06-11 | 2014-10-07 | 가부시키가이샤 신가와 | Bonding device and method for producing semiconductor device |
WO2013187292A1 (en) * | 2012-06-11 | 2013-12-19 | 株式会社新川 | Bonding device and method for producing semiconductor device |
KR101630249B1 (en) | 2012-06-11 | 2016-06-14 | 가부시키가이샤 신가와 | Bonding device and method for producing semiconductor device |
JP2014187220A (en) * | 2013-03-25 | 2014-10-02 | Toshiba Corp | Semiconductor device manufacturing method |
JPWO2015079991A1 (en) * | 2013-11-27 | 2017-03-16 | 東レエンジニアリング株式会社 | 3D mounting method and 3D mounting apparatus |
KR20160090842A (en) | 2013-11-27 | 2016-08-01 | 토레이 엔지니어링 컴퍼니, 리미티드 | Three-dimensional mounting method and three-dimensional mounting device |
WO2015079991A1 (en) * | 2013-11-27 | 2015-06-04 | 東レエンジニアリング株式会社 | Three-dimensional mounting method and three-dimensional mounting device |
US9673166B2 (en) | 2013-11-27 | 2017-06-06 | Toray Engineering Co., Ltd. | Three-dimensional mounting method and three-dimensional mounting device |
CN110383446A (en) * | 2017-03-16 | 2019-10-25 | Ev 集团 E·索尔纳有限责任公司 | The method for being adapted to couple to few three substrates |
JP2020511784A (en) * | 2017-03-16 | 2020-04-16 | エーファウ・グループ・エー・タルナー・ゲーエムベーハー | Method for joining at least three substrates |
JP7177781B2 (en) | 2017-03-16 | 2022-11-24 | エーファウ・グループ・エー・タルナー・ゲーエムベーハー | Method for bonding at least three substrates |
CN110383446B (en) * | 2017-03-16 | 2024-07-16 | Ev集团E·索尔纳有限责任公司 | Method for joining at least three substrates |
JP2020136389A (en) * | 2019-02-15 | 2020-08-31 | 日本放送協会 | Stacked semiconductor integrated circuit and its manufacturing method |
JP7253402B2 (en) | 2019-02-15 | 2023-04-06 | 日本放送協会 | Stacked semiconductor integrated circuit and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
TWI506717B (en) | 2015-11-01 |
KR20120118458A (en) | 2012-10-26 |
KR101802173B1 (en) | 2017-11-28 |
JP5984394B2 (en) | 2016-09-06 |
JPWO2011087003A1 (en) | 2013-05-20 |
TW201140739A (en) | 2011-11-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2011087003A1 (en) | Three-dimensional packaging method and device | |
JP5989313B2 (en) | Die bonder and bonding method | |
JP6454283B2 (en) | 3D mounting method and 3D mounting apparatus | |
JP5344145B2 (en) | Method for aligning electronic component and substrate in bonding apparatus | |
JP4618859B2 (en) | Laminated wafer alignment method | |
CN102901920A (en) | Electronic component carrying device and electronic component carrying method | |
JP7045891B2 (en) | Semiconductor manufacturing method, semiconductor manufacturing equipment and semiconductor equipment | |
CN109314065B (en) | Mounting device and mounting method | |
TW201633441A (en) | Bonding device and bonding method | |
JP2024045175A5 (en) | ||
KR102336342B1 (en) | Systems and methods for bonding semiconductor elements | |
JP2006100656A (en) | Overlapping method at wafer lamination | |
JP2013162082A (en) | Component lamination accuracy measurement jig set and usage thereof, and component lamination accuracy measurement device of component mounting machine and production method of three-dimensional mounting substrate | |
TW201711085A (en) | Method and apparatus for manufacturing a semiconductor device including a plurality of semiconductor chips connected with bumps | |
JP2010192817A (en) | Pickup method and pickup device | |
JP2006073814A (en) | Semiconductor chip mounting apparatus and mounting method | |
JP2009260008A (en) | Semiconductor device manufacturing device, and method of manufacturing semiconductor device | |
JP5702114B2 (en) | Chip stacking apparatus and stacking method | |
CN115461287A (en) | Lamination device | |
JP4861690B2 (en) | Chip mounting device | |
CN113985773B (en) | Control system and method for substrate lamination, electronic equipment and storage medium | |
JP5656609B2 (en) | Method of stacking semiconductor device chips using jig plates | |
JP2010212299A (en) | Method of manufacturing laminated semiconductor device | |
JP6596653B2 (en) | Component mounting apparatus, component mounting method, and component mounting system | |
JP6167412B2 (en) | Stacked package manufacturing system and manufacturing method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 2011549979 Country of ref document: JP |
|
ENP | Entry into the national phase |
Ref document number: 20127015218 Country of ref document: KR Kind code of ref document: A |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 11732873 Country of ref document: EP Kind code of ref document: A1 |