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WO2011072001A2 - Gestion thermique dans un processeur à noyaux multiples - Google Patents

Gestion thermique dans un processeur à noyaux multiples Download PDF

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Publication number
WO2011072001A2
WO2011072001A2 PCT/US2010/059436 US2010059436W WO2011072001A2 WO 2011072001 A2 WO2011072001 A2 WO 2011072001A2 US 2010059436 W US2010059436 W US 2010059436W WO 2011072001 A2 WO2011072001 A2 WO 2011072001A2
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WO
WIPO (PCT)
Prior art keywords
processor
temperature reading
temperature
scheduling interval
task
Prior art date
Application number
PCT/US2010/059436
Other languages
English (en)
Other versions
WO2011072001A3 (fr
Inventor
Andrew Wolfe
Original Assignee
Empire Technology Development Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Empire Technology Development Llc filed Critical Empire Technology Development Llc
Priority to DE112010004717T priority Critical patent/DE112010004717T5/de
Priority to JP2012542245A priority patent/JP5559891B2/ja
Publication of WO2011072001A2 publication Critical patent/WO2011072001A2/fr
Publication of WO2011072001A3 publication Critical patent/WO2011072001A3/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/20—Cooling means
    • G06F1/206—Cooling means comprising thermal management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5094—Allocation of resources, e.g. of the central processing unit [CPU] where the allocation takes into account power or heat criteria
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates generally to processor technologies and more specifically to thermal management in multi-core processors. BACKGROUND OF THE DISCLOSURE
  • a conventional multi-core processor includes two or more independent processor cores arranged in an array. Each processor core generally shares the same voltage control circuit and clock signal control circuit to simplify the interfaces among the processor cores.
  • the present disclosure recognizes that having such shared control circuits may limit the power management capabilities for the multi-core processor. Moreover, when the processor cores are unequally utilized, one processor core in one region of the die of the multi-core processor may become substantially hotter than another processor core on the same die. The unequal temperatures may cause physical stress on the die.
  • One embodiment of the present disclosure may generally relate to a thermal management method for a multi-core processor having a first processor core and a second processor core.
  • One example method may include retrieving a first temperature reading for the first processor core during a first portion of a scheduling interval, retrieving a second temperature reading for the second processor core during a second portion of the scheduling interval, and assigning a first task to the first processor core to be executed based on a comparison of the first temperature reading and the second temperature reading retrieved during the scheduling interval.
  • Another embodiment of the present disclosure may generally relate to a computer readable medium containing instructions for managing thermal environment in a multi-core processor.
  • the processor When example instructions are executed by a processor, the processor may be configured to retrieve a first temperature reading during a first portion of a scheduling interval, retrieve a second temperature reading during a second portion of the scheduling interval, and assign a first task to the first processor core to be executed based on a comparison of the first temperature reading and the second temperature reading retrieved during the scheduling interval.
  • Yet another embodiment of the present disclosure may generally relate to a thermal management system for a multi-core processor having a first processor core and a second processor core.
  • One example thermal management system may include a first thermal sensor configured to output a set of first temperature measurements, a second thermal sensor configured to output a set of second temperature measurements, a memory subsystem that is configured to store the set of first temperature measurements and the set of second temperature measurements, and a processor.
  • the processor may be configured to retrieve a first temperature reading for the first processor core from the memory
  • FIG. 1 illustrates an example thermal management system for a multi-core processor
  • FIG. 2 is a flow chart illustrating a method for processing temperature measurements associated with one or more processor cores in a multi-core processor
  • FIG. 3 is a flow chart illustrating a method for assigning one or more tasks to one or more processor cores in a multi-core processor
  • FIG. 4 is a flow chart illustrating a method 400 for reassigning one or more tasks to one or more processor cores in a multi-core processor
  • FIG. 5 is a schematic diagram illustrating a computer program product for assigning one or more tasks to one or more processor cores in a multi-core processor based on the temperature readings of the one or more processor cores;
  • FIG. 6 is a block diagram of an example computing device having a multi-core processor and a processor; all arranged in accordance with at least some embodiments of present disclosure.
  • This disclosure is drawn, inter alia, to devices, methods, and computer programs related to thermal management in a multi-core processor as will be described herein.
  • temperature reading may broadly refer to a representation of temperature resulting from processing one or more temperature measurements collected by one or more thermal sensors.
  • the temperature measurements may be collected as an analog signal such as a voltage or current, or a digital signal such as a binary code representative of the measurement.
  • Example embodiments may set forth devices, systems, methods, and/or computer programs related to thermal management in the multi-core processor. Some example methods may include retrieving a first temperature reading for the first processor core during a scheduling interval, retrieving a second temperature reading for the second processor core also during the scheduling interval, and assigning a first task to the first processor core to be executed based on a comparison of the first temperature reading and the second temperature reading retrieved during the scheduling interval.
  • FIG. 1 illustrates an example thermal management system 100 for a multi-core processor 102, arranged in accordance with at least some embodiments of the present disclosure.
  • the multi-core processor 102 may include multiple processor cores, such as a processor core 104, a processor core 105, and a processor core 107, arranged in rows and columns in a 2-dimensional array on an integrated circuit.
  • the processor cores may be adapted to execute programs, processes, threads, or portions thereof.
  • the thermal management system 100 may include one or more thermal sensors 106 coupled to the processor cores, one or more quantization circuits 108, a thermal processing subsystem 1 10, a task distributor 1 12, and a memory subsystem 1 14.
  • the thermal sensors 106 may generally be on the same die as the processor cores.
  • each thermal sensors 106 may be configured to measure temperatures at various physical locations of a processor core and generate analog output signals corresponding to the measured temperatures.
  • one of the thermal sensors 106 may be coupled to the processor core 105 as shown in FIG. 1 and may be configured to measure the surrounding temperatures at or near the location of the thermal sensor 106 (e.g., the upper left corner of the processor core 105).
  • multiple thermal sensors 106 may be coupled to the same processor core 105 (not shown), so that the surrounding temperatures at or near multiple hot spots associated with the processor core 105 may be measured.
  • the quantization circuit 108 may be placed in between two processor cores.
  • Examples of the quantization circuit 108 may include an analog-to-digital converter (or ADC), so that the analog temperature measurements (e.g., analog currents or voltage measurements) of the thermal sensors 106 may be converted to discrete digital values.
  • Some example quantization circuits 108 may include one or more buffers, amplifiers, or attenuators to buffer and/or adjust the signal gain of the analog temperature measurements as may be desired. The gain or attenuation may be provided with linear characteristics, non-linear characteristics, or some combination thereof.
  • Some additional example quantization circuits 108 may include active and/or passive filters adapted to prevent instabilities and/or to reduce noise related issues in the analog temperature measurements.
  • quantization circuits 108 may include limiters or clamps to prevent the analog temperature measurements exceeding a particular level that may be undesirable. Some examples quantization circuits 108 may include sample and hold, track and hold, and/or switched capacitor circuits adapted to sample the analog signal levels associated with the analog temperature measurements. Some other example quantization circuits 108 may use analog multiplexers to couple to one or more thermal sensors 106. In some other implementations, a single example quantization circuit 108 may monitor every processor core.
  • the thermal processing subsystem 1 10 may be configured to process the temperature measurements of the thermal sensors 106.
  • the thermal processing system 1 10 may include a variety of circuits configured to assist in capturing measurements from one or more of the quantization circuits, including but not limited to one or more general or special purpose processor cores, multiplexers, and/or buffers.
  • the thermal processing subsystem 1 10 may be configured to collect (e.g., via a processor and/or a multiplexer) and aggregate successive temperature measurements (e.g., via a processor) for a particular processing core over a period of time and utilize a function such as, without limitation, minimum, maximum, median, or average, to calculate a temperature reading for the processing core. For the same processing core, the thermal processing subsystem 1 10 may collect temperature measurements from one or more thermal sensors 106. After having calculated the temperature reading based on the collected temperature measurements, the thermal processing subsystem 1 10 may be configured to store the calculated temperature reading for the processor core in the memory subsystem 1 14.
  • the task distributor 1 12 may be configured to assign one or more tasks to one or more processor cores of the multi-core processor 102 based on the temperature readings retrieved from the memory subsystem 1 14.
  • the task distributor 1 12 may be a service provided by an operating system that executes on one or more general or special processor cores.
  • the task distributor 1 12 may be configured to select a set of tasks from a task buffer (which may reside in the memory subsystem 1 14) and/or may be configured to assign one or more tasks from the set of tasks to be executed by one or more processor cores of the multi-core processor 102 based on a set of parameters such as, without limitation, the level of workload associated with the tasks and the temperature readings of the processor cores. Subsequent discussions found herein, with their related drawings, will further detail some operations of the task distributor 1 12.
  • the memory subsystem 1 14 may be configured to be accessible by both the thermal processing subsystem 1 10 and the task distributor 1 12.
  • the memory subsystem 1 14 may include different levels of caches to store, for example, without limitation, the processed results of the thermal processing subsystem 1 10 and/or the aforementioned task buffer.
  • the task distributor 1 12 may be arranged to retrieve and utilize such processed results in assigning one or more such tasks from the task buffer to one or more processor cores in the multi-core processor 102.
  • FIG. 2 is a flow chart illustrating a method 200 for processing temperature
  • Method 200 may include one or more operations, functions or actions as illustrated by one or more of blocks 202, 204, 206, and/or 208. Although the blocks are illustrated in a sequential order, these blocks may also be performed in parallel, and/or in a different order than those described herein. Also, the various blocks may be combined into fewer blocks, divided into additional blocks, and/or eliminated based upon the desired implementation.
  • Processing for the method 200 may begin at block 202, "Collect first temperature measurements for first processor core.”
  • Block 202 may be followed by block 204, “Collect second temperature measurements for second processor core.”
  • Block 204 may be followed by block 206, "Process collected first temperature measurements and collected second temperature measurements.”
  • Block 206 may be followed by block 208, "Store first temperature reading and second temperature reading.”
  • one or more temperature measurements for a first processor core in a multi-core processor may be collected from one or more thermal sensors coupled to the first processor core.
  • the temperature measurements of the thermal sensor 106 for a first processor core e.g., the processor core 105 may be collected, by the thermal processing subsystem 1 10, one or more times during a scheduling interval. If multiple thermal sensors 106 are coupled to the processor core 105, then the temperature measurements of the multiple thermal sensors 106 may be collected for the processor core 105.
  • one or more temperature measurements for a second processor core in the same multi-core processor may also be collected from one or more thermal sensors coupled to the second processor core.
  • the temperature measurements for the first processor core and the second processor core may be collected during the same scheduling interval. In some other implementations, the temperature measurements for the first processor core and the second processor core may be collected from the thermal sensors during different scheduling intervals.
  • the collected first temperature measurements and the collected second temperature measurements may be processed by a thermal processing subsystem.
  • the processing of block 206 may be initiated also by the thermal processing subsystem after a certain number of the first temperature measurements and/or the second temperature measurements have been collected.
  • a function may be applied, by the thermal processing subsystem 1 10, to the collected first temperature measurements and the collected second temperature measurements to establish the first temperature reading for the first processor core and the second temperature reading for the second processor core, respectively.
  • Some example functions may include, without limitation, establishing a minimum, a maximum, a median, and an average value based on the collected temperature measurements.
  • the first temperature reading for the first processor core and the second temperature reading for the second processor core may be stored by the thermal processing subsystem for further processing.
  • the method 200 may be performed repeatedly to collect multiple temperature measurements at different times, process the collected temperature measurements, and store the resulting temperature readings.
  • one or more first temperature readings for the first processor core and one or more second temperature readings for the second processor core may be stored.
  • Each temperature reading may correspond to a set of temperature measurements that are collected at a certain time or over a certain time interval.
  • a first temperature reading associated with time 1 may correspond to the first temperature measurements collected at time 1 and may be denoted as a first-temperature-reading_f/me 1.
  • a second temperature reading associated with also time 1 may correspond to the second temperature measurements collected at time 1 and may be denoted as a second-temperature- reading f/me 1.
  • the method 200 may also be performed in either an analog domain or a digital domain.
  • the first temperature measurements and the second temperature measurements collected in blocks 202 and 204, respectively may correspond to sets of discrete analog values or discrete digital values, depending on the specific implementation.
  • One or more quantization circuits such as the quantization circuits 108 described with reference to FIG. 1 , may be utilized to generate such measurement values.
  • FIG. 3 is a flow chart illustrating a method 300 for assigning one or more tasks to one or more processor cores in a multi-core processor, arranged in accordance with at least some embodiments of the present disclosure.
  • Method 300 may include one or more operations, functions or actions as illustrated by one or more of blocks 302, 304, 306, and/or 308. Although the blocks are illustrated in a sequential order, these blocks may also be performed in parallel, and/or in a different order than those described herein. Also, the various blocks may be combined into fewer blocks, divided into additional blocks, and/or eliminated based upon the desired implementation.
  • Processing for the method 300 may begin at block 302, "Retrieve first temperature reading for first processor core.”
  • Block 302 may be followed by block 304, "Retrieve second temperature reading for second processor core.”
  • Block 204 may be followed by block 306, "Assign task based on comparison between first temperature reading and second
  • Block 306 may be followed by block 308, "Periodically reassign task.”
  • the first temperature reading for the first processor core which results from the processing of the first temperature measurements for the same first processor core, may be retrieved by a task distributor, which may be executed by one or more general or special purpose processor core, from a memory subsystem, such as the memory
  • the retrieval of the first temperature reading may take place during a first portion of a scheduling interval that differs from the scheduling interval in which the first temperature reading is established and stored. In another implementation, the retrieval of the first temperature reading and the storing of the first temperature reading may occur in the same scheduling interval. [0030] In block 304, the second temperature reading for the second processor core, which results from the processing of the second temperature measurements for the same second processor core, may also be retrieved by the task distributor from the same memory subsystem during a second portion of the scheduling interval.
  • the first portion of the scheduling interval associated with the first temperature readings for the first processor core and the second portion of the scheduling interval associated with the second temperature readings for the second processor core may be substantially the same portion of the scheduling interval.
  • the first portion and the second portion may be overlapping portions of the scheduling interval.
  • the first portion and the second portion may be different portions of the scheduling interval.
  • the first temperature reading and the second temperature reading may be respectively based on the first temperature measurements and the second temperature measurements that are collected at the same or approximately the same time, time 1.
  • one or more tasks may be assigned to one or more processor cores.
  • the comparison may be to identify the processor core with the lowest temperature reading, so that the one or more tasks may be assigned to such a processor core, which may have the least amount of workload to handle.
  • the task assignment may be performed by the task distributor during the same scheduling interval as the retrieval of the first temperature reading and the second temperature reading.
  • the one or more tasks may be reassigned by the task distributor periodically to one or more processor cores.
  • tasks initially assigned to the first processor core may be reassigned to the second processor core and vice-versa. Subsequent discussions associated with FIG. 4 will further detail some operations of task reassignment.
  • FIG. 4 is a flow chart illustrating a method 400 for reassigning one or more tasks to one or more processor cores in a multi-core processor, arranged in accordance with at least some embodiments of the present disclosure.
  • Method 400 may include one or more operations, functions or actions as illustrated by one or more of blocks 402, 404, 406, 408, 410, and/or 412. Although the blocks are illustrated in a sequential order, these blocks may also be performed in parallel, and/or in a different order than those described herein. Also, the various blocks may be combined into fewer blocks, divided into additional blocks, and/or eliminated based upon the desired implementation.
  • Processing for the method 400 may begin at block 402, "Retrieve first temperature reading for first processor core.”
  • Block 402 may be followed by block 404, "Retrieve second temperature measurement for second processor core.”
  • Block 404 may be followed by block 406, "Has reassignment event occurred.”
  • block 406 may be followed by block 408, "Suspend task,” which may be followed by block 410, "Analyze workload associated with task.”
  • Block 410 may be followed by block 412, "Reassign task based on temperature reading comparison and/or workload.” If on the other hand, no reassignment event has been determined to occur in block 406, then processing may continue at block 402, where another set of temperature readings may be retrieved.
  • the first temperature reading for the first processor core may be retrieved by a task distributor, which may be executed by one or more general or special purpose processor cores, from a memory subsystem, such as the memory subsystem 1 14 as shown in FIG. 1 .
  • the retrieved first temperature reading may be for the first temperature measurements collected at time 2, which may be subsequent to the collection time of time 1 as described in the aforementioned method 300.
  • the second temperature reading for the second processor core may also be retrieved by the task distributor from the same memory subsystem.
  • the second temperature reading may be based on the second temperature measurements that may also be collected at the same or approximately the same time 2.
  • the retrieval operations of block 402 and 404 may occur during substantially the same portions, overlapping portions, or different portions of the same scheduling interval.
  • method 400 may be configured to determine by the task distributor whether a reassignment event has occurred. In some implementations, a reassignment event may be deemed to have occurred, when a temperature differential between the first temperature reading and the second temperature reading exceeds a predetermined threshold value.
  • the temperature differential may be between the temperature readings of two adjacent processor cores (e.g., the processor core 104 and the processor core 105 as shown in FIG. 1 ) or between the temperature readings of two non-adjacent processor cores (e.g., the processor core 104 and the processor core 107 as shown in FIG. 1 ).
  • a reassignment event may be deemed to have occurred, when the relationship between the first temperature reading and the second temperature reading may have changed. For example, suppose the first temperature reading is initially lower than the second temperature reading. When this relationship between the temperature readings changes, e.g., the first temperature reading becomes higher than the second temperature reading, the reassignment event may be deemed to have occurred. When a reassignment event may be deemed by the task distributor to have occurred in block 406, method 400 may proceed to block 408. Otherwise, method 400 may go back to block 402 and block 404 to retrieve another first temperature reading and another second temperature reading, respectively.
  • the task may be suspended.
  • the two processor cores may use a shared virtual memory space supported by known memory coherency protocols, such as, without limitation, the MESI protocol.
  • the workload associated with the task to be evaluated for reassignment may be analyzed by the task distributor.
  • the task distributor may analyze the workload associated with the task to be evaluated for reassignment.
  • performance counters which may be a set of special-purpose registers, may be utilized to measure and gather performance-related activities of the multi-core processor.
  • the one or more performance counters may be configured to track the number of floating point operations within a given time interval.
  • the performance counters may track the average number of operations waiting for completion in a reorder buffer.
  • the performance counters may track the average memory access time.
  • the performance counters may also track the percentage of instruction issue slots that are utilized.
  • a task initially assigned to one processor core may be reassigned by the task distributor to another processor core (e.g., the second processor core).
  • the first task may be reassigned by the task distributor to another processor core (e.g., the second processor core).
  • the first task may be reassigned to the second processor core having the lower temperature reading, so that the second processor core may be adapted to process a computationally intensive first task.
  • FIG. 5 is a schematic diagram illustrating a computer program product 500 for assigning one or more tasks to one or more processor cores in a multi-core processor based on the temperature readings of the one or more processor cores, arranged in accordance with at least some embodiments of present disclosure.
  • the computer program product 500 may include one or more sets of executable instructions 502 for executing the methods described herein, such as described previously and illustrated in FIG. 2, FIG. 3, and FIG. 4.
  • the computer program product 500 may be transmitted in a signal bearing medium 504 or another similar communication medium 506.
  • the computer program product 500 may also be recorded in a computer readable medium 508 or another similar recordable medium 510.
  • FIG. 6 is a block diagram of an example computing device having a multi-core processor and a processor, arranged in accordance with at least some embodiments of the present disclosure.
  • computing device 600 typically includes one or more processors 604 and a system memory 606.
  • a memory bus 608 may be used for communicating between processor 604 and system memory 606.
  • processor 604 here may refer to a general purpose processor.
  • processor 604 may be of any type including but not limited to a microprocessor ( ⁇ ), a microcontroller ( ⁇ ), a digital signal processor (DSP), or any combination thereof.
  • Processor 604 may include one more levels of caching, such as a level one cache 610 and a level two cache 612, a processor core 614, and registers 616. Registers 616 may be utilized to implement the aforementioned performance counters to track the levels of workload associated with various tasks to be assigned.
  • An example processor core 614 may include an arithmetic logic unit (ALU), a floating point unit (FPU), a digital signal processing core (DSP Core), or any combination thereof.
  • An example memory controller 618 may also be used with processor 604, or in some implementations memory controller 618 may be an internal part of processor 604.
  • system memory 606 may be of any type including but not limited to volatile memory (such as RAM), non-volatile memory (such as ROM, flash memory, etc.) or any combination thereof.
  • System memory 606 may include an operating system 620, one or more applications 622, and program data 624.
  • the operating system 620 may include a thermal processing subsystem 625, such as the thermal processing subsystem 1 10 shown in FIG. 1 , and a scheduler 626, which may include a task distributor, such as the task distributor 1 12 shown in FIG. 1 .
  • the thermal processing subsystem 625 may be arranged to perform the functions as described herein including those described with respect to at least method 200 of FIG. 2.
  • the scheduler 626 may be arranged to perform the functions as described herein including those described with respect to at least method 300 of FIG. 3 and method 400 of FIG. 4.
  • application 622 may include the thermal processing subsystem 625 and the scheduler 626 (not shown in FIG. 6), and application 622 may be arranged to operate with program data 624 on operating system 620.
  • Program data 624 may include task related information, such as, without limitation, a task buffer including a set of task for the scheduler 626 to assign to the one or more processor cores in the multi-core processor 664, the temperature readings as discussed in the method 200 of FIG. 2, method 300 of FIG. 3, and method 400 of FIG. 4 that the scheduler 626 may rely upon for the task assignments, and others.
  • This described basic configuration 602 is illustrated in FIG. 6 by those components within the inner dashed line.
  • Computing device 600 may have additional features or functionality, and additional interfaces to facilitate communications between basic configuration 602 and any required devices and interfaces.
  • a bus/interface controller 630 may be used to facilitate communications between basic configuration 602 and one or more data storage devices 632 via a storage interface bus 634.
  • Data storage devices 632 may be removable storage devices 636, non-removable storage devices 638, or a combination thereof.
  • removable storage and non-removable storage devices include magnetic disk devices such as flexible disk drives and hard-disk drives (HDD), optical disk drives such as compact disk (CD) drives or digital versatile disk (DVD) drives, solid state drives (SSD), and tape drives to name a few.
  • Example computer storage media may include volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules, or other data.
  • System memory 606, removable storage devices 636 and non-removable storage devices 638 are examples of computer storage media.
  • Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD- ROM, digital versatile disks (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which may be used to store the desired information and which may be accessed by computing device 600. Any such computer storage media may be part of computing device 600.
  • Computing device 600 may also include an interface bus 640 for facilitating communication from various interface devices (e.g., output devices 642, peripheral interfaces 644, and communication devices 646) to basic configuration 602 via bus/interface controller 630.
  • Example output devices 642 include a graphics processing unit 648 and an audio processing unit 650, which may be configured to communicate to various external devices such as a display or speakers via one or more A/V ports 652.
  • Example peripheral interfaces 644 include a serial interface controller or a parallel interface controller, which may be configured to communicate with external devices such as input devices (e.g., keyboard, mouse, pen, voice input device, touch input device, etc.) or other peripheral devices (e.g., printer, scanner, etc.) via one or more I/O ports 658.
  • input devices e.g., keyboard, mouse, pen, voice input device, touch input device, etc.
  • other peripheral devices e.g., printer, scanner, etc.
  • communication device 646 includes a network controller, which may be arranged to facilitate communications with one or more other computing devices 662 over a network
  • computing device 600 includes a multi-core processor 664, which may communicate with the processor 604 through the interface bus 640.
  • the network communication link may be one example of a communication media.
  • Communication media may typically be embodied by computer readable instructions, data structures, program modules, or other data in a modulated data signal, such as a carrier wave or other transport mechanism, and may include any information delivery media.
  • a "modulated data signal" may be a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal.
  • communication media may include wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, radio frequency (RF), microwave, infrared (IR) and other wireless media.
  • RF radio frequency
  • IR infrared
  • the term computer readable media as used herein may include both storage media and communication media.
  • Computing device 600 may be implemented as a portion of a small-form factor portable (or mobile) electronic device such as a cell phone, a personal data assistant (PDA), a personal media player device, a wireless web-watch device, a personal headset device, an application specific device, or a hybrid device that include any of the above functions.
  • a small-form factor portable (or mobile) electronic device such as a cell phone, a personal data assistant (PDA), a personal media player device, a wireless web-watch device, a personal headset device, an application specific device, or a hybrid device that include any of the above functions.
  • PDA personal data assistant
  • Computing device 600 may also be implemented as a personal computer including both laptop computer and non-laptop computer configurations.
  • embodiments disclosed herein, in whole or in part, can be equivalently implemented in integrated circuits, as one or more computer programs running on one or more computers (e.g., as one or more programs running on one or more computer systems), as one or more programs running on one or more processors (e.g., as one or more programs running on one or more microprocessors), as firmware, or as virtually any combination thereof, and that designing the circuitry and/or writing the code for the software and or firmware would be well within the skill of one of skill in the art in light of this disclosure.
  • a signal bearing medium examples include, but are not limited to, the following: a recordable type medium such as a floppy disk, a hard disk drive, a Compact Disc (CD), a Digital Video Disk (DVD), a digital tape, a computer memory, etc.; and a transmission type medium such as a digital and/or an analog communication medium (e.g., a fiber optic cable, a waveguide, a wired communications link, a wireless communication link, etc.).
  • a typical data processing system generally includes one or more of a system unit housing, a video display device, a memory such as volatile and non-volatile memory, processors such as microprocessors and digital signal processors, computational entities such as operating systems, drivers, graphical user interfaces, and applications programs, one or more interaction devices, such as a touch pad or screen, and/or control systems including feedback loops and control motors (e.g., feedback for sensing position and/or velocity; control motors for moving and/or adjusting components and/or quantities).
  • a typical data processing system may be implemented utilizing any suitable commercially available components, such as those typically found in data computing/communication and/or network computing/communication systems.
  • any two components so associated can also be viewed as being “operably connected”, or “operably coupled”, to each other to achieve the desired functionality, and any two components capable of being so associated can also be viewed as being “operably couplable”, to each other to achieve the desired functionality.
  • operably couplable include but are not limited to physically mateable and/or physically interacting components and/or wirelessly interactable and/or wirelessly interacting components and/or logically interacting and/or logically interactable components.

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Abstract

Les techniques décrites concernent généralement des processeurs à noyaux multiples comprenant deux noyaux de processeur ou plus. Des modes de réalisation illustratifs peuvent présenter des dispositifs, des procédés, et des programmes d'ordinateur relatifs à la gestion thermique dans le processeur à noyaux multiples. Certains procédés illustratifs peuvent comprendre la récupération d'une première lecture de température pour le premier noyau de processeur pendant un intervalle de planification, la récupération d'une seconde lecture de température pour le second noyau de processeur également pendant l'intervalle de planification, et l'attribution d'une première tâche au premier noyau de processeur à exécuter sur la base d'une comparaison de la première lecture de température et de la seconde lecture de température récupérées pendant l'intervalle de planification.
PCT/US2010/059436 2009-12-08 2010-12-08 Gestion thermique dans un processeur à noyaux multiples WO2011072001A2 (fr)

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DE112010004717T DE112010004717T5 (de) 2009-12-08 2010-12-08 Wärmemanagement in mehrkernprozessor
JP2012542245A JP5559891B2 (ja) 2009-12-08 2010-12-08 マルチコアプロセッサにおける熱管理

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US12/632,811 US20110138395A1 (en) 2009-12-08 2009-12-08 Thermal management in multi-core processor
US12/632,811 2009-12-08

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US20110138395A1 (en) 2011-06-09
DE112010004717T5 (de) 2012-10-04
JP5559891B2 (ja) 2014-07-23
WO2011072001A3 (fr) 2014-03-27
JP2013513169A (ja) 2013-04-18

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