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WO2010137167A1 - Dispositif à semi-conducteur - Google Patents

Dispositif à semi-conducteur Download PDF

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Publication number
WO2010137167A1
WO2010137167A1 PCT/JP2009/059886 JP2009059886W WO2010137167A1 WO 2010137167 A1 WO2010137167 A1 WO 2010137167A1 JP 2009059886 W JP2009059886 W JP 2009059886W WO 2010137167 A1 WO2010137167 A1 WO 2010137167A1
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WO
WIPO (PCT)
Prior art keywords
region
body region
semiconductor device
insulated gate
high concentration
Prior art date
Application number
PCT/JP2009/059886
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English (en)
Japanese (ja)
Inventor
浩佐 馬場
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トヨタ自動車株式会社
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Publication date
Application filed by トヨタ自動車株式会社 filed Critical トヨタ自動車株式会社
Priority to PCT/JP2009/059886 priority Critical patent/WO2010137167A1/fr
Publication of WO2010137167A1 publication Critical patent/WO2010137167A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/016—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • the present invention relates to a semiconductor device including a first insulated gate semiconductor element and a second insulated gate semiconductor element.
  • Patent Document 1 discloses a semiconductor device including a main element and a current detection element.
  • the main element and the current detection element are vertical field effect transistors (MOS-FETs).
  • the current detection element operates in the same manner as the main element.
  • the current flowing through the current detection element has a value corresponding to the current flowing through the main element. By detecting the current flowing through the current detection element, the current flowing through the main element can be detected.
  • a leakage current may flow between the main element and the current detection element.
  • the ratio of the current between the main element and the current detection element varies depending on the magnitude of the leakage current. Since manufacturing variation occurs in the magnitude of the leakage current, manufacturing variation also occurs in the current ratio between the main element and the current detection element. If the current ratio varies, the current flowing through the main element cannot be accurately detected. Therefore, it is necessary to electrically isolate the main element and the current detection element so that no leakage current occurs between the main element and the current detection element.
  • a high resistance region is formed between the main element and the current detection element.
  • Crystal defects in the high resistance region are formed by injecting helium into the semiconductor substrate. A leakage current between the main element and the current detection element is suppressed by the high resistance region.
  • the present specification can suppress a current flowing between the first insulated gate semiconductor element and the second insulated gate semiconductor element, and can be manufactured by a general manufacturing process, and manufactured with high manufacturing efficiency.
  • a semiconductor device Provided is a semiconductor device.
  • the semiconductor device provided in this specification includes a semiconductor substrate on which a first insulated gate semiconductor element and a second insulated gate semiconductor element are formed.
  • the first insulated gate semiconductor element has a first region, a first body region, a first degree lift region, a first electrode, and a first gate electrode.
  • the first region is a first conductivity type region facing the first surface of the semiconductor substrate.
  • the first body region is a region of the second conductivity type that faces the first surface of the semiconductor substrate and covers the first region.
  • the first drift region is a first conductivity type region separated from the first region by the first body region.
  • the first electrode is formed on the first surface of the semiconductor substrate and is electrically connected to the first region and the first body region.
  • the first gate electrode faces the first body region in a range separating the first region and the first drift region via an insulating film.
  • the second insulated gate semiconductor element has a second region, a second body region, a second drift region, a second electrode, and a second gate electrode.
  • the second region is a first conductivity type region facing the first surface of the semiconductor substrate.
  • the second body region is a region of the second conductivity type that faces the first surface of the semiconductor substrate and covers the second region.
  • the second drift region is a first conductivity type region separated from the second region by the second body region.
  • the second electrode is formed on the first surface of the semiconductor substrate and is electrically connected to the second region and the second body region.
  • the second gate electrode is opposed to the body region in a range separating the second region and the second drift region via an insulating film.
  • a high concentration region having a first conductivity type impurity concentration higher than that of the first drift region and the second drift region is formed in a region facing the first surface between the first body region and the second body region.
  • An insulated gate semiconductor element refers to a semiconductor element that includes a gate electrode facing a semiconductor layer with an insulating film interposed therebetween, and that is switched by controlling the potential of the gate electrode.
  • Insulated gate semiconductor elements include MOS-FETs, IGBTs, and the like.
  • the first conductivity type and the second conductivity type mean either n-type or p-type. That is, when the first conductivity type is n-type, the second conductivity type is p-type, and when the second conductivity type is p-type, the first conductivity type is n-type.
  • a high concentration region of the first conductivity type is formed between the first body region of the second conductivity type and the second body region of the second conductivity type.
  • the first conductivity type is n-type
  • a pnp structure is formed by the first body region, the high concentration region, and the second body region. Since the n-type impurity concentration in the high concentration region is high, the energy barrier of the pn junction included in the pnp structure is high. For this reason, the leakage current is suppressed from flowing between the first body region and the second body region.
  • an npn structure is formed by the first body region, the high concentration region, and the second body region.
  • the leakage current is suppressed from flowing between the first body region and the second body region.
  • the leakage current is suppressed from flowing between the first insulated gate semiconductor element and the second insulated gate semiconductor element.
  • the high concentration region can be formed by implanting n-type or p-type impurities. Therefore, the high concentration region can be formed by a general manufacturing process. Further, the concentration of the n-type or p-type impurity in the high concentration region can be accurately controlled. Therefore, it is not necessary to implant n-type or p-type impurities more than necessary. For this reason, this semiconductor device can be manufactured with high manufacturing efficiency.
  • the first drift region and the second drift region may be separated by a high concentration region.
  • the high concentration region may be formed not only in the vicinity of the first surface of the semiconductor substrate but also in a deeper position.
  • the high concentration region may be formed in a region adjacent to the lower side of the first body region and a region adjacent to the lower side of the second body region.
  • the high concentration region when the high concentration region is formed below the body region, carriers can be accumulated in the drift region.
  • the insulated gate semiconductor element can be operated with high efficiency.
  • Sectional drawing of the semiconductor device 10 of an Example Sectional drawing of the semiconductor device of a 1st modification. Sectional drawing of the semiconductor device of a 2nd modification. The figure which shows the cross section and upper surface of the semiconductor device of the 3rd modification in the state which removed the electrode and insulating film of the upper surface of a semiconductor substrate.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor device 10 according to an embodiment.
  • the semiconductor device 10 includes a semiconductor substrate 12 mainly made of silicon.
  • a main element region 20 and a current detection element region 40 are formed in the semiconductor substrate 12.
  • a plurality of trenches are formed on the upper surface of the semiconductor substrate 12 in the main element region 20.
  • a gate insulating film 32 is formed on the wall surface of the trench.
  • a gate electrode 34 is formed in the trench.
  • a cap insulating film 36 is formed on the gate electrode 34.
  • An n-type emitter region 22 and a p-type body contact region 24a are selectively formed in a region of the main element region 20 facing the upper surface of the semiconductor substrate 12.
  • the emitter region 22 is formed in contact with the gate insulating film 32.
  • the body contact region 24 a is in contact with the emitter region 22.
  • a low concentration body region 24b is formed below the emitter region 22 and the body contact region 24a.
  • the p-type impurity concentration in the low-concentration body region 24b is lower than the p-type impurity concentration in the body contact region 24a.
  • the low concentration body region 24b is in contact with the emitter region 22 and the body contact region 24a.
  • the low-concentration body region 24 b is in contact with the gate insulating film 32 below the emitter region 22.
  • An end body region 24c is formed at the end of the main element region 20 on the current detection element region 40 side.
  • the p-type impurity concentration of the end body region 24c is substantially equal to the p-type impurity concentration of the low-concentration body region 24b.
  • the end body region 24 c is formed so as to surround the main element region 20.
  • the end body region 24 c is a p-type region for suppressing electric field concentration in the main element region 20.
  • the end body region 24c is formed from the upper surface of the semiconductor substrate 12 to a position deeper than the lower end of the low concentration body region 24b.
  • the end body region 24c is in contact with the low concentration body region 24b.
  • a body region 24 that covers the emitter region 22 is formed by the body contact region 24a, the low-concentration body region 24b, and the end body region 24c.
  • An n-type drift layer 26 is formed below the body region 24.
  • the drift layer 26 is separated from the emitter region 22 by the body region 24.
  • a p-type collector layer 28 is formed in a region below the drift layer 26 and facing the lower surface of the semiconductor substrate 12.
  • the collector layer 28 is separated from the body region 24 by the drift layer 26.
  • a large number of IGBTs are formed in the main element region 20 by the emitter region 22, the body region 24, the drift layer 26, the collector layer 28, and the gate electrode 34.
  • the IGBT formed in the main element region 20 is referred to as an IGBT 21.
  • the current detection element region 40 includes an emitter region 42, a body contact region 44a, a low concentration body region 44b, an end body region 44c, a drift layer 46, a collector layer 48, a gate electrode 54, a gate.
  • An insulating film 52 and a cap insulating film 56 are formed.
  • the drift layer 46 is a layer that is continuous with the drift layer 26 in the main element region 20.
  • the collector layer 48 is a layer that is continuous with the collector layer 28 in the main element region 20.
  • a large number of IGBTs are formed in the current detection element region 40 by the emitter region 42, the body region 44, the drift layer 46, the collector layer 48, and the gate electrode 54.
  • the IGBT formed in the current detection element region 40 is referred to as an IGBT 41.
  • a collector electrode 60 is formed on the entire lower surface of the semiconductor substrate 12.
  • the collector electrode 60 is in ohmic contact with the collector layers 28 and 48.
  • An emitter electrode 66 is formed on the upper surface of the semiconductor substrate 12 in the main element region 20.
  • the emitter electrode 66 is formed so as to cover the cap insulating film 36 and is insulated from the gate electrode 34.
  • the emitter electrode 66 is in ohmic contact with the emitter region 22 and the body contact region 24a of the main element region 20.
  • An emitter electrode 68 is formed on the upper surface of the semiconductor substrate 12 in the current detection element region 40.
  • the emitter electrode 68 is separated from the emitter electrode 66 in the main element region 20.
  • the emitter electrode 68 is formed so as to cover the cap insulating film 56 and is insulated from the gate electrode 54.
  • the emitter electrode 68 is in ohmic contact with the emitter region 42 and the body contact region 44a of the current detection element region 40.
  • a high concentration region 58 is formed between the body region 24 of the main element region 20 and the body region 44 of the current detection element region 40.
  • the high concentration region 58 is formed in a range facing the upper surface of the semiconductor substrate 12.
  • the high concentration region 58 has one end in contact with the body region 24 of the main element region 20 and the other end in contact with the body region 44 of the current detection element region 40.
  • the high concentration region 58 is an n-type region.
  • the n-type impurity concentration of the high concentration region 58 is higher than that of the drift layers 26 and 46.
  • the high concentration region 58 extends along the depth direction (direction perpendicular to the paper surface) of FIG. 1, and the body region 24 and the body region 44 are separated by the high concentration region 58.
  • the collector electrode 60 is connected to the power supply potential VDD, and the emitter electrodes 66 and 68 are connected to the ground potential GND.
  • the emitter electrode 66 in the main element region 20 is directly connected to the ground potential GND.
  • the emitter electrode 68 of the current detection element region 40 is connected to the ground potential GND through the resistor Rs.
  • the potentials of the gate electrodes 34 and 54 are controlled, so that the IGBT 21 and the IGBT 41 are switched. Note that the potential of the gate electrode 54 is controlled similarly to the gate electrode 34.
  • the IGBTs 21 and 41 are off.
  • the IGBTs 21 and 41 are turned on.
  • a channel is formed in the low concentration body region 24 b in the range in contact with the gate insulating film 32.
  • electrons flow from the emitter electrode 66 to the collector electrode 60 through the emitter region 22, the channel of the low-concentration body region 24 b, the drift layer 26, and the collector layer 28.
  • holes flow from the collector electrode 60 through the collector layer 28 into the drift layer 26. Then, the conductivity modulation phenomenon occurs in the drift layer 26, and the loss in the drift layer 26 is suppressed.
  • the holes flow from the drift layer 26 to the emitter electrode 66 through the low-concentration body region 24b and the body contact region 24a.
  • a channel is formed in the low-concentration body region 44b in the range in contact with the gate insulating film 52.
  • electrons flow from the emitter electrode 68 to the collector electrode 60 through the emitter region 42, the channel of the low-concentration body region 44 b, the drift layer 46, and the collector layer 48.
  • holes flow from the collector electrode 60 to the drift layer 46 through the collector layer 48. Then, the conductivity modulation phenomenon occurs in the drift layer 46, and the loss in the drift layer 46 is suppressed.
  • the holes flow from the drift layer 46 to the emitter electrode 68 through the low concentration body region 44b and the body contact region 44a.
  • the IGBTs 21 and 41 are turned on. Therefore, a current flows from the terminal of the power supply potential VDD toward the terminal of the ground potential GND. The current flowing through the IGBT 41 passes through the resistor Rs. For this reason, a potential difference corresponding to the current flowing through the IGBT 41 is generated at both ends of the resistor Rs. The current flowing through the IGBT 41 can be detected by detecting the potential difference between both ends of the resistor Rs. When the current flowing through the IGBT 41 is detected, the current flowing through the IGBT 21 can be detected from the current ratio between the IGBT 41 and the IGBT 21. By detecting the current flowing through the IGBT 21, the IGBT 21 can be turned off instantaneously when an overcurrent flows through the IGBT 21. As a result, damage to the device can be prevented.
  • the area of the current detection element region 40 is much smaller than the area of the main element region 20. Therefore, the current flowing through the IGBT 41 is much smaller than the current flowing through the IGBT 21.
  • the electric resistance of the resistor Rs is set to a small value. Therefore, the loss caused by the resistor Rs is extremely small. As described above, by providing the IGBT 41 for current detection, the current of the IGBT 21 can be detected without causing high loss. Note that since the current flowing through the resistor Rs is small and the electric resistance of the resistor Rs is small, the potential difference generated at both ends of the resistor Rs is a very small potential difference.
  • a potential difference is generated between both ends of the resistor Rs.
  • This potential difference is very small, but affects the operation of the semiconductor device 10. That is, when a potential difference occurs between both ends of the resistor Rs, the potential of the emitter electrode 68 becomes higher than the potential of the emitter electrode 66. For this reason, the potential of the body region 44 becomes higher than the potential of the body region 24. Then, due to the potential difference between the body region 44 and the body region 24, an electric field from the body region 44 toward the body region 24 is generated in the region between the body region 44 and the body region 24, as indicated by an arrow 80 in FIG. . When a leakage current flows due to this electric field, the current detection accuracy of the IGBT 21 decreases.
  • a high concentration region 58 is formed between the body region 44 and the body region 24. That is, a pnp structure is formed by the body region 44, the high concentration region 58, and the body region 24. Since the n-type impurity concentration in the high concentration region 58 is high, the energy barrier of the pn junction in this pnp structure is very high. For this reason, even if the electric field shown by the arrow 80 arises, a leakage current is suppressed by the energy barrier of the pn junction between the high concentration area
  • the semiconductor device 10 when the semiconductor device 10 is mass-produced, there is almost no manufacturing variation in the ratio between the current of the IGBT 21 and the current of the IGBT 41. According to the semiconductor device 10, the current of the IGBT 21 can be accurately detected by detecting the current of the IGBT 41.
  • the above-described high concentration region 58 can be formed by implanting n-type impurity ions and thermally diffusing the implanted n-type impurities. That is, it can be formed by a technique used in a general semiconductor manufacturing process.
  • the n-type impurity concentration in the high concentration region 58 can be accurately controlled, it is not necessary to implant more n-type impurities than necessary.
  • the high concentration region 58 can be formed simultaneously with the emitter regions 22 and 42. For this reason, the semiconductor device 10 can be manufactured without increasing the number of manufacturing steps as compared with the conventional semiconductor device. Therefore, the semiconductor device 10 can be manufactured efficiently.
  • the semiconductor device 10 since the leakage current is suppressed by the high concentration region 58, the separation region between the main element region 20 and the current detection element region 40 (that is, the region between the body region 24 and the body region 44). Can be narrowed. Therefore, the semiconductor device 10 can be reduced in size as compared with the conventional semiconductor device.
  • the semiconductor device 10 can be made smaller than the semiconductor device of Patent Document 1 as will be described below.
  • a high resistance region is formed by injecting helium. Since helium ions penetrate the photoresist, the helium implantation range cannot be controlled using the photoresist.
  • the helium implantation range is controlled using a metal mask. The error in alignment between the metal mask and the semiconductor substrate is large, and an error of about 100 ⁇ m may occur. For this reason, the formation range of the high resistance region cannot be accurately controlled. Therefore, it is necessary to provide a wide separation region so that the position of the high resistance region is not affected even if a positional shift occurs. Since the separation region is wide, the semiconductor device of Patent Document 1 is large.
  • the high concentration region 58 is formed by implanting an n-type impurity.
  • the implantation range of the n-type impurity can be controlled by forming a photoresist on the semiconductor substrate. If a photoresist is used, the n-type impurity implantation range can be accurately controlled. For this reason, the formation range of the high concentration region 58 can be accurately controlled. Therefore, the separation region between the main element region 20 and the current detection element region 40 can be narrowed. Since the separation region can be narrowed, the semiconductor device 10 can be downsized.
  • the depth of the high concentration region 58 can be adjusted as appropriate.
  • the depth of the high concentration region 58 may be shallower or deeper than the example shown in FIG.
  • the high concentration region 58 may be formed to a depth reaching the collector layers 28 and 48, and the drift layer 26 may be separated from the drift layer 46.
  • the leakage current between the main element region 20 and the current detection element region 40 can be further suppressed.
  • a high concentration region 58 a is formed between the body region 24 and the body region 44, and a high concentration region 58 b adjacent to the lower side of the body region 24 and a lower portion of the body region 44 are formed.
  • a high concentration region 58c adjacent to the side may be formed.
  • the positions of the lower ends of the high concentration regions 58a, 58b, and 58c are substantially equal.
  • the high concentration region 58b suppresses the holes in the drift layer 26 from moving to the low concentration body region 24b. For this reason, more holes are accumulated in the drift layer 26 and the electric resistance of the drift layer 26 becomes smaller. Therefore, the loss generated in the IGBT 21 is reduced.
  • the high concentration region 58c functions in the same manner, and the loss generated in the IGBT 41 is reduced. Further, at the time of manufacturing the semiconductor device of FIG. 3, the high concentration regions 58a, 58b and 58c can be formed simultaneously. For this reason, this semiconductor device can be manufactured with high manufacturing efficiency.
  • the high concentration region 58 is formed over the entire region between the body region 24 and the body region 44.
  • the high concentration region 58 may be partially formed between the body region 24 and the body region 44.
  • a region where the high concentration region 58 is not formed among the regions between the body region 24 and the body region 44 is a drift region. Also in the semiconductor device of FIG. 4, leakage current can be suppressed.
  • the semiconductor device in which the IGBT 21 and the IGBT 41 are formed has been described.
  • the insulated gate semiconductor element included in the semiconductor device may be a MOS-FET.
  • the semiconductor device in which the insulated gate semiconductor element is a MOS-FET has a configuration in which the collector layers 28 and 48 are removed from the configuration in FIGS. 1 to 4 and the electrode 60 is in ohmic contact with the drift layers 26 and 46. be able to. Even when the insulated gate semiconductor device is a MOS-FET, the high concentration region 58 can suppress the leakage current between the main element region 20 and the current detection element region 40.

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Abstract

L'invention porte sur un dispositif à semi-conducteur capable de supprimer un courant électrique circulant entre un premier élément à semi-conducteur à grille isolée et un second élément à semi-conducteur à grille isolée, et fabriqué dans un processus de fabrication général avec un haut rendement de fabrication. Le dispositif à semi-conducteur comprend un substrat semi-conducteur dans lequel le premier élément à semi-conducteur à grille isolée et le second élément à semi-conducteur à grille isolée sont formés. Une région à concentration élevée est formée dans une région faisant face à une première surface du substrat semi-conducteur entre une région de corps du premier élément à semi-conducteur à grille isolée et une région de corps du second élément à semi-conducteur à grille isolée. La concentration en impureté du premier type de conductivité de la région à concentration élevée est supérieure à celle d'une région de migration du premier élément à semi-conducteur à grille isolée et d'une région de migration du second élément à semi-conducteur à grille isolée.
PCT/JP2009/059886 2009-05-29 2009-05-29 Dispositif à semi-conducteur WO2010137167A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014118859A1 (fr) * 2013-01-31 2014-08-07 株式会社デンソー Dispositif à semi-conducteur au carbure de silicium

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0637262A (ja) * 1992-05-18 1994-02-10 Toyota Autom Loom Works Ltd 半導体装置
JPH08188541A (ja) 1995-01-10 1996-07-23 Res Dev Corp Of Japan 静電結合型高分子ミセル薬物担体とその薬剤
JPH10326897A (ja) * 1997-03-25 1998-12-08 Hitachi Ltd 電流検出セル付トレンチゲート半導体装置
WO1999061512A1 (fr) 1998-05-23 1999-12-02 University Of Strathclyde Vesicules formees a partir d'acide polyamine
JP2001014556A (ja) 1999-06-29 2001-01-19 Toshiba Corp 電気機器の報知音作製方法、コンピュータを利用した電気機器の報知音作製支援方法、電気機器の報知音作製支援装置および電気機器の報知音作製支援プログラムを記録したコンピュータ読取り可能な媒体
JP2004221162A (ja) * 2003-01-10 2004-08-05 Renesas Technology Corp デュアル半導体装置
JP2006100690A (ja) * 2004-09-30 2006-04-13 Matsushita Electric Ind Co Ltd パワートランジスタ温度保護装置
JP2008205500A (ja) * 2008-04-14 2008-09-04 Toshiba Corp 絶縁ゲート型半導体装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0637262A (ja) * 1992-05-18 1994-02-10 Toyota Autom Loom Works Ltd 半導体装置
JPH08188541A (ja) 1995-01-10 1996-07-23 Res Dev Corp Of Japan 静電結合型高分子ミセル薬物担体とその薬剤
JPH10326897A (ja) * 1997-03-25 1998-12-08 Hitachi Ltd 電流検出セル付トレンチゲート半導体装置
WO1999061512A1 (fr) 1998-05-23 1999-12-02 University Of Strathclyde Vesicules formees a partir d'acide polyamine
JP2001014556A (ja) 1999-06-29 2001-01-19 Toshiba Corp 電気機器の報知音作製方法、コンピュータを利用した電気機器の報知音作製支援方法、電気機器の報知音作製支援装置および電気機器の報知音作製支援プログラムを記録したコンピュータ読取り可能な媒体
JP2004221162A (ja) * 2003-01-10 2004-08-05 Renesas Technology Corp デュアル半導体装置
JP2006100690A (ja) * 2004-09-30 2006-04-13 Matsushita Electric Ind Co Ltd パワートランジスタ温度保護装置
JP2008205500A (ja) * 2008-04-14 2008-09-04 Toshiba Corp 絶縁ゲート型半導体装置

Non-Patent Citations (17)

* Cited by examiner, † Cited by third party
Title
A. DE FOUGEROLLES ET AL., NATURE REVIEW DRUG DISCOVERY, vol. 6, 2007, pages 443 - 453
B. THOMPSON ET AL., BIOCONJUGATE CHEMISTRY, vol. 16, 2005, pages 608 - 614
C. NICOLAZZI ET AL., JOURNAL OF CONTROLLED RELEASE, vol. 88, 2003, pages 429 - 443
C.D. NOVINA ET AL., NATURE, vol. 430, 2004, pages 161 - 164
D. OUPICKY ET AL., GENE THERAPY, vol. 8, 2001, pages 713 - 724
E. WALTER ET AL., JOURNAL OF CONTROLLED RELEASE, vol. 61, 1999, pages 361 - 374
H.K. DE WOLF ET AL., INTERNATIONAL JOURNAL OF PHARMACEUTICS, vol. 331, 2007, pages 167 - 175
HU-LIESKOVAN ET AL., CANCER RESEARCH, vol. 65, 2005, pages 8984 - 8992
J.D. HEIDEL ET AL., PROCEEDINGS OF THE NATIONAL ACADEMY OF SCIENCES, vol. 104, 2007, pages 5715 - 5721
R.G. CRYSTAL ET AL., SCIENCE, vol. 270, 1995, pages 404 - 410
R.M. SCHIFFELERS ET AL., NUCLEIC ACIDS RESEARCH, vol. 32, 2004, pages E149
S. AKHTAR ET AL., JOURNAL OF CLINICAL INVESTIGATION, vol. 117, 2007, pages 3623 - 3632
S.K. TRIPATHY ET AL., NATURE MEDICINE, vol. 2, 1996, pages 545 - 550
W. PUN ET AL., JOURNAL OF CELLULAR BIOCHEMISTRY, vol. 98, 2006, pages 14 - 35
Y. TAKAKURA ET AL., INTERNATIONAL JOURNAL OF PHARMACEUTICS, vol. 105, 1994, pages 19 - 29
Y. WANG ET AL., BIOMATERIALS, vol. 28, 2007, pages 5358 - 5368
Y. YAMASAKI ET AL., JOURNAL OF PHARMACOLOGY AND EXPERIMENTAL THERAPEUTICS, vol. 301, 2002, pages 467 - 477

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* Cited by examiner, † Cited by third party
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WO2014118859A1 (fr) * 2013-01-31 2014-08-07 株式会社デンソー Dispositif à semi-conducteur au carbure de silicium
JP2014150126A (ja) * 2013-01-31 2014-08-21 Denso Corp 炭化珪素半導体装置
US10446649B2 (en) 2013-01-31 2019-10-15 Denso Corporation Silicon carbide semiconductor device
DE112013006558B4 (de) 2013-01-31 2023-10-12 Denso Corporation Siliziumcarbidhalbleitervorrichtung

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