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WO2010128361A1 - Dispositif à semi-conducteurs pour application haute tension - Google Patents

Dispositif à semi-conducteurs pour application haute tension Download PDF

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Publication number
WO2010128361A1
WO2010128361A1 PCT/IB2009/051918 IB2009051918W WO2010128361A1 WO 2010128361 A1 WO2010128361 A1 WO 2010128361A1 IB 2009051918 W IB2009051918 W IB 2009051918W WO 2010128361 A1 WO2010128361 A1 WO 2010128361A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
substrate
semiconductor
drift
regions
Prior art date
Application number
PCT/IB2009/051918
Other languages
English (en)
Inventor
Alexander Hoelke
Deb Kumar Pal
Kia Yaw Kee
Yang HAO
Uta Kuniss
Original Assignee
X-Fab Semiconductor Foundries Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by X-Fab Semiconductor Foundries Ag filed Critical X-Fab Semiconductor Foundries Ag
Priority to PCT/IB2009/051918 priority Critical patent/WO2010128361A1/fr
Publication of WO2010128361A1 publication Critical patent/WO2010128361A1/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/421—Insulated-gate bipolar transistors [IGBT] on insulating layers or insulating substrates, e.g. thin-film IGBTs

Definitions

  • This invention relates to the field of high voltage semiconductor devices, more specifically to, lateral high voltage devices suitable for power integrated circuit technologies.
  • High voltage (HV) semiconductor devices contain a pn junction, which is capable of blocking the voltage.
  • a central part of this junction is the so-call drift region, which depletes in the off-state thereby allowing the high voltage to be dropped.
  • this drift region is fully depleted and the electric field is homogeneous, which allows for the shortest drift region length possible.
  • Fig. 1 shows a vertical HV semiconductor device 10 having a base region 12, a drift region 14 and an upper semiconductor region 16.
  • a - terminal 17 and a + terminal 18 are provided on the upper region 16 and the substrate 12, respectively.
  • the semiconductor base region has an n + type conductivity
  • the drift or depletion region 14 has a n " type conductivity
  • the upper semiconductor region 16 has a p+ type conductivity.
  • the drift region can be described by a one- dimensional pn junction.
  • the lines A and B show the border lines of the before mentioned regions.
  • Fig. 1 also shows the electric field and space charge region for this case.
  • the electric field is not homogeneous but trapezoidal, so the drift region 14 must be longer than for the case of a uniform field. Yet there is no penalty in terms of device area as the drift region 14 extends into the depth of the semiconductor.
  • Such a device is difficult to integrate into a semiconductor technology with all electrical terminals located on the wafer surface. The bottom terminal of the vertical device needs to be routed to the surface and isolated from the other terminals, which increases the device area.
  • the thickness and doping concentration of the drift region determine the voltage rating, see Hu, Optimum doping profile for minimum ohmic resistance and high-breakdown voltage", IEEE Trans.
  • FIG. 2 shows a so-called reduced surface field or RESURF device 20 of the lateral type.
  • the device 20 comprises a substrate 21 of p " type conductivity and a top semiconductor layer 22 with a first semiconductor region 23 of p+ type conductivity and a second semiconductor region 24 of n+ type conductivity and a drift region 25 extending between the p+ region 23 and the n+ region 24.
  • a depletion region 26 is formed in the substrate 21 as shown.
  • a - terminal 27 is connected with the p+ region 23, and a + terminal 28 is connected to the region 24.
  • the vertical lines A and B in the Fig. 2 graph of the surface electrical field represent the border lines of the mentioned regions.
  • the method of Reduced Surface Field allows realisation of integrated HV devices because it is a lateral construction with all the electric terminals at the wafer surface. It utilises a two- dimensional depletion of the drift pn-junction laterally and vertically to result in a fundamentally homogenous electric field distribution along the surface.
  • Fig. 2 also shows the field distribution and space charge region of a RESURF diode. The drift region is fully depleted and the electric field is substantially homogeneous, with only two peaks near the terminals.
  • This homogeneous field ensures a high voltage rating with a low on-resistance. Similar to the vertical devices the voltage rating demands a specific doping concentration and drift layer thickness for optimum RESURF devices. Devices with substantially different voltage rating can be integrated but require individual drift regions, which increases process complexity. Generally, different processes are set up for different voltage classes.
  • Fig. 3 shows a silicon-on insulator (SOI) RESURF device 30 having a first layer 31 , a buried oxide (BOX) layer 32 as an insulating layer on top of the first layer 31.
  • a top silicon layer 33 is provided on the top of the BOX-layer 32 comprising a first region of p+ type conductivity, a second region 35 of n+ type conductivity and a depletion region 36 of n- type conductivity.
  • a - terminal 37 and a + terminal 38 are in contact with the regions 34 and 35 respectively.
  • a further - terminal 39 is connected with the first layer 31.
  • the lines A and B show the border lines of the before mentioned regions.
  • the “substrate” may be one of the handle wafer itself or the top silicon layer. More generally the "first layer” was used above.
  • SOI Silicon-On-lnsulator
  • Field Plate RESURF is used to maintain a uniform field along the drift region.
  • the MOS capacitor formed by the first layer e.g. a substrate), a buried oxide (BOX) and a top silicon, helps to deplete the drift region, see Merchant et. al., "Realization of High Breakdown Voltage (larger than 700V) in Thin SOI Devices", Proc. 3 rd Intl. Symp. Power Semiconductor Devices & Integrated Circuits, April 1991 , Baltimore, USA, pp.
  • Fig. 3 shows the schematic cross-section and electric field with the depletion region of the SOI RESURF diode.
  • the drift region is fully depleted and the electric field uniform.
  • the voltage rating dictates the doping and thickness of the drift region and additionally the voltage determines a minimum thickness for the BOX.
  • differently rated HV voltage devices require a specific process technology.
  • Fig. 4 shows a partial SOI HV semiconductor device 40 having a substrate 41 of p- type conductivity and an insulator layer 42 on top of the substrate 41.
  • the insulator layer 42 only partially covers the upper surface of the substrate 41.
  • a top silicon layer 43 is provided comprising a first region 44 of p+ type conductivity, a second region 45 of n+ type conductivity and a depletion region 46 in between regions 44 and 45 respectively.
  • the region 45 is in contact with the upper surface of the substrate 41.
  • a - terminal 47 is connected to the region 44
  • a+ terminal 48 is connected to the region 45
  • a - terminal 49 is connected to the substrate.
  • the region 45 thereby forms a contact to the substrate, a so-called handle wafer contact.
  • the lines A and B represent the border lines of the before mentioned regions.
  • Partial SOI is a technique where handle wafer depletion is used to suppress the field plate effect in SOI, see Lu, Ratnam, Salama, "High Voltage Silicon-On-lnsulator (SOI) MOSFETs", Proc. 3 rd Intl. Symp. Power Semiconductor Devices & Integrated Circuits, April 1991 , Baltimore, USA, pp. 36 to 39. It is similar to RESURF depletion as a vertical junction and a lateral junction work together to create a uniform surface field, see Fig. 4. A means of handle wafer contact must be provided in close proximity to the device. As in bulk RESURF, the voltage rating determines the doping concentration of the drift region.
  • FIG. 5 shows a lateral super junction HV semiconductor device 50 comprising an insulator layer 51 and a top silicon layer 52 on top of the insulator layer 51.
  • the top silicon layer 52 comprises a first region 53 of p+ type conductivity, a second region 54 of n+ type conductivity and a depletion region 53 comprising an upper region 54 of n- type conductivity and a lower region 55 of p- type conductivity in between the regions 53 and 54 respectively.
  • a - terminal 57 is connected to the p+ region 53 and a + terminal 58 is connected to the n+ region 54.
  • the lines A and B represent the border lines of the before mentioned regions.
  • Fig. 6 shows another example of a super junction HV semiconductor device 60 comprising an insulator layer 61 and, on top of the insulator layer 61 a top silicon layer 62 which has a region 63 of p+ type conductivity and a region 64 of n+ type conductivity and a depletion region 65 between the p+ region 63 and the n+ region 64.
  • the depletion region consists of two layers 66a, 66b of n- type conductivity and two layers 67a, 67b of p- type conductivity where the layers 66 and 67 are provided alternatively in the top silicone layer 62.
  • a - terminal 68 and a + terminal 69 are connected with the p+ region 63 and the n+ region 64 respectively.
  • the lines A and B represent the border lines of the before mentioned regions.
  • Figs. 5 and 6 show two implementation of a Super Junction with two and four horizontal regions of alternating doping type, both placed on a thick BOX. Other arrangements are possible and known to those skilled in the art.
  • a lateral high voltage semiconductor device comprises a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type arranged laterally to the first semiconductor region and a drift region there between, wherein the drift region comprises at least one first drift sub-region of the first conductivity type and at least one second drift sub-region of the second conductivity type, and wherein the first and the second drift sub-regions are arranged such that, when a reverse voltage is applied across the first and second semiconductor regions, they mutually deplete.
  • the device further comprises an insulating layer on a substrate, the insulating layer being arranged between the substrate and the super junction arrangement, thereby forming a SOI arrangement.
  • the features of the lateral high voltage semiconductor device according to the invention are voltage-independent, in particular the doping concentrations and the dimensions (thickness) of the various regions in the device.
  • the only requirement is that the handle wafer doping is low enough to support the highest voltage of the application.
  • the voltage rating of the lateral Super Junction device is set by the drift region length only.
  • a lateral high voltage semiconductor device comprises a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type arranged laterally to the first semiconductor region and a drift region there between, wherein the drift region comprises at least one first drift sub-region of the first conductivity type and at least one second drift sub-region of the second conductivity type, and wherein the first and the second drift sub-regions are arranged such that, when a reverse voltage is applied across the first and second semiconductor regions, the sub regions mutually deplete, whereby a super junction arrangement is formed.
  • the regions receive a balanced charge.
  • the behavior of this device is representing the structural design. Applying the reverse voltage is characterizing the device. Not necessarily this is a feature of use, it more or less is a result of a measuring step, allowing to determine the inner type or structure of a device.
  • the (claimed) device further comprises an insulating layer on a substrate, the insulating layer being arranged between the substrate and the super junction arrangement comprising the first semiconductor region and the second semiconductor region and the drift region, thereby forming a SOI arrangement.
  • the insulating layer is formed with an extension extending around the super junction arrangement thereby completely insulating the super junction arrangement from the substrate.
  • the device further comprises a further semiconductor region of the second conductivity type extending from an outer level of the super junction arrangement past the insulating layer to the substrate and being insulated from the super junction arrangement.
  • a reverse voltage is applied across the first and second semiconductor regions, a substrate drift region in the substrate is formed.
  • the features of the lateral high voltage semiconductor device according to the second implementation of the invention are voltage-independent, in particular the doping concentrations and the dimensions (thickness) of the various regions in the device.
  • SOI-typical operation is maintained.
  • the length of the drift region is selected to comply with the required voltage rating, whereas any thickness dimensions and doping concentrations of the substrate, the insulating layer and the super junction arrangement are left unchanged.
  • the semiconductor device comprises a plurality of first drift sub-regions and second drift sub-region which can improve device performance.
  • the first and the second drift sub- regions of the semiconductor device are arranged on top of each other as seen from the substrate, or, alternatively, the first and the second drift sub-regions are arranged laterally to each other as seen from the substrate.
  • the invention is feasible for both available arrangements of the drift sub-regions which give some additional freedom in the design.
  • the semiconductor device comprises electrical terminals on the first semiconductor region of the first conductivity type and the second semiconductor region of the second conductivity type, wherein the terminals are arranged on an outer level of the super junction arrangement which facilitates access (or making electrical contact) to the elements of the device.
  • a substrate terminal is provided on a reverse side of the substrate of the semiconductor device as viewed from the super junction arrangement as may be desired in some applications.
  • side substrate contacts are used, see Fig. 9. This is even preferred to substrate contact from the back. Both are covered by the general conception.
  • the semiconductor device comprises a further electrical terminal on the further semiconductor region of the first conductivity type which further terminal is arranged on an outer level of the super junction arrangement which is advantageous in the contact design and the controllability of the handle wafer diode.
  • the first semiconductor region has a p+ type conductivity and the second semiconductor region has a n+ type conductivity, and wherein the at least one first drift sub-region has an p type conductivity and the at least one second drift sub-region has a n type conductivity, and the substrate has a p- type conductivity.
  • Fig. 1 is a vertical HV semiconductor device according to prior art.
  • Fig. 2 is a RESURF HV semiconductor device according to prior art.
  • Fig. 3 is a SOI HV semiconductor device, a so-called SOI RESURF or field plate RESURF device, according to prior art.
  • Fig. 4 is a partial SOI HV semiconductor device according to prior art.
  • Fig. 5 shows a lateral super junction HV semiconductor device according to prior art.
  • Fig. 6 shows another example of a lateral super junction HV semiconductor device according to prior art.
  • Fig. 7 shows a lateral HV semiconductor device according to a first embodiment of the invention.
  • Fig. 8 shows a lateral HV semiconductor device according to another embodiment of the present invention.
  • Fig. 9 shows a lateral HV semiconductor device according to another embodiment of the present invention.
  • Fig. 7 is a lateral HV semiconductor device 70 according to a first embodiment of the invention.
  • the semiconductor device 70 comprises a substrate 71 of p- type conductivity which is partially covered by an insulator layer 72.
  • a top silicon layer 73 is provided on top of the insulator layer 72 and the portion of the substrate 71 which is not covered by the insulator layer 72.
  • the top silicon layer 73 has a first semiconductor region 74 of p+ type conductivity and a second semiconductor region 75 of n+ type conductivity which is literally arranged to the first semiconductor region 74.
  • a depletion or drift region 76 is provided between the first semiconductor region 74 and the second semiconductor region 75 respectively.
  • the drift region 76 comprises a first drift sub-region 77 of n- type conductivity and a second drift sub-region 78 of p- type conductivity.
  • the first and second drift sub- regions 77, 78 are arranged such that, when a reverse voltage is applied across the first and the second semiconductor regions 74, 75, they mutually deplete, whereby the super junction arrangement is formed.
  • the insulation layer 72 on the substrate 71 is therefore, arranged between the substrate 71 and the super junction arrangement thereby forming an SOI arrangement.
  • a substrate drift or depletion region 79 is formed.
  • a - terminal 80 is connected to the p+ region 74, a + terminal 81 is connected to the n+ region 75 and a further - terminal 82 is connected to the substrate 71.
  • the n+ region 75 extends from the + terminal 81 to the upper surface of the substrate 71.
  • the lines A and B represent the border lines of the before mentioned regions.
  • the length of the drift region 76 is selected to a comply with the required voltage rating, whereas any thickness dimensions and doping concentrations of the substrate 71 , the insulation layer 72 and the super junction arrangement 74 to 78 are left unchanged or can be selected to be the same for a range of voltage ratings or breakdown voltages. Therefore, the HV semiconductor device 70 is very advantageous for device integration of different devices on one and the same handle wafer or substrate.
  • the substrate or handle wafer depletes under the super junction formed in the top silicon layer 73.
  • the handle wafer diode thus suppresses the field plate effect, which otherwise disturbs the charge balance in the super junction.
  • the BOX thickness, top silicon thickness and super junction doping are independent of the voltage rating. The only requirement is that the handle wafer diode supports the highest voltage rating.
  • the super junction is then scalable to any voltage by drift length variation only.
  • Fig. 7 only two regions 77 and 78 form the depletion region 76.
  • a plurality of first and second drift sub-regions can be provided to improve device performance.
  • the first and second drift sub-regions 77 and 78 are arranged one on top of the other as seen from the substrate 71.
  • the first and second drift sub-regions 77 and 78 can also be arranged laterally to each other as seen from the substrate 71.
  • the HV semiconductor device 90 shown in Fig. 8 is another embodiment of the semiconductor device of the invention.
  • Fig. 7 therefore, the same reference numbers are used for corresponding features already shown in Fig. 7, and the like features are not explained again.
  • the embodiment of the HV (high voltage) semiconductor device 90 of Fig. 8 differs, first of all, from the embodiment of Fig. 7 in that the insulating layer 91 is formed with an extension 92, e.g. a trench.
  • the trench type extension 92 extends around the super junction arrangement which is formed, in this embodiment, by the first region 74 of p+ type conductivity, the drift region 76 and a second semiconductor region 93 and is dielectrically insulated from the substrate 71.
  • the insulator layer 91 only partially covers the upper surface of the substrate 71 , and a further semiconductor region 94 with n+ type conductivity is provided between the upper level of the device 90 and the portion of the upper surface of the substrate 71 which is not covered by the insulator layer 91.
  • a + terminal 95 is connected to the semiconductor region 93 such that the reverse voltage between the regions 74 and 93 can be controlled independently from the voltage applied to the substrate through a + terminal 95 via the semiconductor region 94.
  • the contact to the + terminal 95 and the region 94 to the substrate 71 is dielectrically isolated from the super junction.
  • the handle diode can thus be biased independently.
  • the super junction HV device formed in the top silicon layer 73 is thus fully dielectrically isolated, just as in a standard SOI technology, i.e. as in a non-partial SOI. This construction allows SOI- typical operation and devices, such as rectifier diodes, high-side IGBT integration and below ground potential robustness.
  • the semiconductor device of Fig. 9 is similar to the one of Fig. 8, but having a top side contact W. This contact replaces the substrate contact 82 from the reverse side.
  • the structure is modified correspondingly.
  • the insulating layer 91 is formed with a second trench type extension Y and the top side substrate contact terminal W is provided at an additional region X, here of p+ type, connecting to the substrate 71.
  • the second trench type extension Y dielectrically isolates the substrate connection X from the super junction.

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Abstract

L'invention concerne un dispositif à semi-conducteurs haute tension latéral comprenant une première zone semi-conductrice, une seconde zone semi-conductrice disposée latéralement par rapport à la première zone semi-conductrice, et une zone de dérive placée entre les deux. La zone de dérive présente une sous-zone de dérive n et une sous-zone de dérive p formant une superjonction. Le dispositif comprend une couche isolante sur un substrat, entre le substrat et la superjonction, une zone d'appauvrissement du substrat étant ainsi formée, et la première et/ou la seconde zone semi-conductrice s'étendant au-delà de la couche isolante jusqu'au substrat. La couche isolante peut également être formée avec une extension isolant entièrement du substrat l'agencement formant la superjonction, et le dispositif comprend en outre une zone semi-conductrice supplémentaire d'un second type de conductivité s'étendant à partir du niveau extérieur de l'agencement formant la superjonction au-delà de la couche isolante jusqu'au substrat et isolée de l'agencement formant la superjonction.
PCT/IB2009/051918 2009-05-08 2009-05-08 Dispositif à semi-conducteurs pour application haute tension WO2010128361A1 (fr)

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Application Number Priority Date Filing Date Title
PCT/IB2009/051918 WO2010128361A1 (fr) 2009-05-08 2009-05-08 Dispositif à semi-conducteurs pour application haute tension

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Application Number Priority Date Filing Date Title
PCT/IB2009/051918 WO2010128361A1 (fr) 2009-05-08 2009-05-08 Dispositif à semi-conducteurs pour application haute tension

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10529866B2 (en) 2012-05-30 2020-01-07 X-Fab Semiconductor Foundries Gmbh Semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5525824A (en) * 1993-11-09 1996-06-11 Nippondenso Co., Ltd. Semiconductor device with isolation regions
US6551937B2 (en) * 2001-08-23 2003-04-22 Institute Of Microelectronics Process for device using partial SOI
US6858884B2 (en) * 2002-06-26 2005-02-22 Cambridge Semiconductor Limited Lateral semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5525824A (en) * 1993-11-09 1996-06-11 Nippondenso Co., Ltd. Semiconductor device with isolation regions
US6551937B2 (en) * 2001-08-23 2003-04-22 Institute Of Microelectronics Process for device using partial SOI
US6858884B2 (en) * 2002-06-26 2005-02-22 Cambridge Semiconductor Limited Lateral semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10529866B2 (en) 2012-05-30 2020-01-07 X-Fab Semiconductor Foundries Gmbh Semiconductor device

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