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WO2010116402A1 - Processeur d'informations - Google Patents

Processeur d'informations Download PDF

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Publication number
WO2010116402A1
WO2010116402A1 PCT/JP2009/001464 JP2009001464W WO2010116402A1 WO 2010116402 A1 WO2010116402 A1 WO 2010116402A1 JP 2009001464 W JP2009001464 W JP 2009001464W WO 2010116402 A1 WO2010116402 A1 WO 2010116402A1
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WO
WIPO (PCT)
Prior art keywords
data
memory area
update information
virtual machine
address
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Application number
PCT/JP2009/001464
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English (en)
Japanese (ja)
Inventor
稲垣淳一
大塚裕朗
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to PCT/JP2009/001464 priority Critical patent/WO2010116402A1/fr
Publication of WO2010116402A1 publication Critical patent/WO2010116402A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]

Definitions

  • the present invention relates to an information processing apparatus that realizes one or more virtual machines.
  • FIG. 1 is a diagram showing an overview of server virtualization technology.
  • the server 101 operates software called a VMM (Virtual Machine Monitor) 102.
  • the VMM 102 manages hardware resources related to the memory and IO (Input / Output) of the server 101. Further, the VMM 102 provides each VM # 0 to # 2 with emulation (imitation) of hardware resources required by each VM.
  • exclusive control of the memory is performed so that the plurality of VMs do not use the same memory area of the physical memory provided in the server 101 redundantly. This exclusive control is performed by memory management of the VMM 102.
  • FIG. 2 is a diagram showing an outline of memory management by the VMM 102.
  • the memory recognized by the VM is called guest physical memory.
  • This guest physical memory is recognized as a continuous memory area from the VM.
  • the guest physical memory is grasped as a separate memory space existing for each VM.
  • FIG. 2 shows the guest physical memory when two VMs, VM # 0 and VM # 1, are operating on the VMM102.
  • there are two guest physical memories the guest physical memory # 0 of VM # 0 and the guest physical memory # 1 of VM # 1.
  • one address X exists in each of the guest physical memories # 0 and # 1. If this address X is assigned as it is to the real memory provided in the server 101, that is, the host physical memory, a conflict occurs.
  • the VMM 102 assigns the address X of the guest physical memory # 0 to the address Z of the host physical memory, and assigns the address X of the guest physical memory # 1 to the address Y of the host physical memory. In this way, the VMM 102 avoids memory contention by allocating host physical memory to different host physical memories.
  • DMA Direct Memory Access
  • the VM # 0 sets the address X as the DMA address in the IO adapter
  • the DMA write is performed on the address X of the host physical memory. Since the address X of the host physical memory is a memory area unrelated to the address X of the guest physical memory # 0, memory destruction is caused. If memory corruption is triggered, the system panics and then shuts down.
  • execution of DMA write by VM # 0 is performed according to the following procedure.
  • the VM # 0 requests the IO adapter to perform a DMA write to the address X of the guest physical memory # 0.
  • the VMM 102 traps the request for the DMA write of VM # 0 and converts the address X of the guest physical memory # 0 into the address W of the buffer area of the host physical memory. Then, the VMM 102 sets the converted address W in the DMA address setting register of the IO adapter.
  • VM # 0 instructs the IO adapter to start DMA.
  • the IO adapter executes DMA write for the address W.
  • the IO adapter When the DMA write is completed, the IO adapter notifies the completion of the DMA write by a DMA completion interrupt. (6) The VMM 102 copies the data stored at the address W of the host physical memory to the address X of the guest physical memory # 0. (7) The VMM 102 notifies the VM # 0 of the completion of the DMA write by a DMA completion interrupt. (8) The VM # 0 extracts data from the address X of the guest physical memory # 0.
  • live migration is a technique for migrating a VM running on a certain server to another server without stopping the operation.
  • FIG. 3 is a diagram showing an outline of live migration.
  • live migration includes two servers # 0 and # 1, a storage 320 shared by servers # 0 and # 1, and a network 330 to which servers # 0 and # 1 are connected. It is possible to perform in the environment provided. Live migration is performed according to the following procedure. (1) The VMM 311 operating on the migration destination server # 1 prepares the VM 312. (2) The migration source VM 302 transfers the contents of the memory used by the migration source VM 302 to the migration destination VM 310 while the migration source VM 302 continues the business. This process is called “pre-copy”.
  • the task of the migration source VM 302 is temporarily stopped, and the migration source VM 301 transfers the memory contents used by the migration source VM 302 to the migration destination VM 310. This process is referred to as “stop and copy”.
  • the migration destination VM 312 resumes the business.
  • VMM performs all memory copies such as pre-copy and stop-and-copy.
  • the VMM can execute the memory copy because the VMM manages the host physical memory.
  • the VMM mediates not only the write processing from the CPU (Central Processing Unit) to the host physical memory but also the DMA write, and detects the memory data change of the migration source VM.
  • CPU Central Processing Unit
  • IOMMU Input / Output Memory Management Unit
  • This IOMMU is a technique for increasing the speed by reducing the memory access overhead caused by the VMM as described above.
  • the IOMMU is a memory management unit that is connected to the IO adapter and the host physical memory and performs conversion between the guest physical memory address and the host physical memory address.
  • the IOMMU is mounted, as shown in FIG. 4, it is possible to execute DMA directly from the IO device to the guest physical memory of the VM.
  • this technology it is not necessary to intervene the VMM when accessing the guest physical memory by the DMA. Further, it is not necessary for the VMM to copy data between the host physical memory and the guest physical memory.
  • a bridge for a multiprocessor system having a dirty RAM mechanism in which a predetermined value is set when a memory area is written by DMA access is known.
  • a mechanism for temporarily stopping a DMA operation selected in a physical I / O adapter in order to enable data migration between physical pages that are accessed by the physical I / O adapter is known.
  • a virtualization system for a host computer having at least one host processor and system resources including memory divided into system memory having the highest privilege and user memory having the lower privilege is known.
  • the present information processing apparatus has been made in view of the above-described problems, and the problem to be solved is to provide an information processing apparatus capable of performing live migration even when IOMMU is used. It is.
  • the information processing apparatus includes the following means.
  • the virtual machine realization means realizes one or more virtual machines by managing hardware resources.
  • the data transfer means mutually converts the address of the first memory area allocated to the virtual machine and the address of the second memory area that is the real memory of the first memory area.
  • the data transfer means transfers data directly from the input / output device that controls input / output of data to / from an external device to the first memory area assigned to the virtual machine.
  • the transfer data detection means detects data directly transferred from the input / output device to the first memory area allocated to the virtual machine.
  • the update information registration unit generates update information regarding the first memory area that is changed by the data detected by the transfer data detection unit, and stores the update information in the update information storage unit.
  • the update information output means outputs the update information stored in the update information storage means.
  • the change information registration means changes the first memory changed by the data transfer. Information about the area is stored in the update information storage means.
  • the update information output means outputs update information stored in the update information output means.
  • live migration can be executed even when IOMMU is used.
  • FIG. 5 is a diagram illustrating a configuration example of the information processing apparatus 500.
  • the information processing device 500 includes CPUs 510 and 511 as arithmetic processing devices, a memory 520 as a main storage device, and a north bridge 530 as a memory control device.
  • the information processing apparatus 500 includes IO adapters 540, 541, and 542 as input / output control apparatuses, and a PCIe switch (PCI Express Switch) 550.
  • PCIe switch PCI Express Switch
  • CPUs 510 and 511 are arithmetic processing units that execute programs developed in the memory 520.
  • the CPUs 510 and 511 implement server virtualization by executing predetermined programs.
  • the CPUs 510 and 511 implement the live migration according to the present embodiment by reading and executing a predetermined program from the storage # 0 or # 1.
  • the memory 520 is a volatile memory that stores programs and data executed by the CPUs 510a and 510b.
  • a RAM Random Access Memory
  • a nonvolatile memory may be used as necessary.
  • the north bridge 530 is connected to the CPUs 510a and 510b, the memory 520, and the PCIe switch 550.
  • the north bridge 530 controls the data transfer path so that the CPUs 510a and 510b and the memory 520 and the PCIe switch 550 can communicate with each other.
  • the north bridge 530 includes an IOMMU 531 and an IO table storage unit 532.
  • the IOMMU 531 is a memory management unit that performs memory management such as conversion between the address of the guest physical memory and the address of the host physical memory.
  • guest physical address the address of the guest physical memory
  • host physical address The address of the host physical memory is called “host physical address”.
  • the IO table storage unit 532 is a storage device that stores an IO table used when the IOMMU 531 converts a guest physical address and a host physical address.
  • a cache memory or the like is used as the IO table storage unit 532. The IO table will be described with reference to FIG.
  • the IO adapters 540, 541, and 542 are interfaces with IO devices connected to the information processing device 500.
  • a DMA circuit that performs DMA is provided in each of the IO adapters 540, 541, and 542.
  • the IO device is, for example, an input / output device such as storages # 0 and # 1 that store data shown in FIG. 5 or a network device connected to a network.
  • the PCIe switch 550 is connected to the north bridge 530 and the IO adapters 540, 541, and 542.
  • the PCIe switch 550 performs switching control of a data transfer path connecting between the north bridge 530 and the IO adapters 540, 541, and 542.
  • the information processing apparatus 500 uses “PCI Express 2.0” which is a serial transfer interface standard for the data transfer path.
  • the PCIe switch 550 includes a dirty page management unit 551 and a dirty page storage unit 552.
  • the dirty page management unit 551 detects a packet as data transferred from the IO adapter 540, 541, or 542 to the memory 520 by DMA write. Then, the dirty page management unit 551 stores information regarding data added, changed, or updated by the DMA write in the dirty page storage unit 552 in units of pages.
  • dirty page information Information about dirty pages is referred to as “dirty page information”.
  • the dirty page storage unit 552 is a storage device that stores dirty page information.
  • a static RAM or the like is used as the dirty page storage unit 552.
  • the information processing apparatus 500 is connected to the information processing apparatus 501 via a network in order to perform live migration. Further, the information processing apparatus 500 and the information processing apparatus 501 share the storages # 0 and # 1.
  • the information processing apparatus 501 includes CPUs 560 and 561, a memory 570, a north bridge 580, IO adapters 590, 591 and 592, and a PCIe switch 600.
  • CPUs 560, 561, memory 570, north bridge 580, IO adapters 590, 591, 592 and PCIe switch 600 are CPU 510, 511, memory 520, north bridge 530, IO adapters 540, 541, 542 and PCIe switch 550, It is the same.
  • the north bridge 580 may not include the IOMMU 531 and the IO table storage unit 532.
  • the PCIe switch 600 may not include the dirty page management unit 551 and the dirty page storage unit 552.
  • the information processing apparatus 501 connected to the information processing apparatus 500 only needs to be able to execute the general live migration shown in FIG.
  • the configuration illustrated in FIG. 5 is an example of the information processing apparatus 500 according to the present embodiment. Therefore, the configuration of the information processing apparatus 500 is not limited to the configuration illustrated in FIG.
  • the number of CPUs, the number of IO adapters, the arrangement of units constituting the information processing apparatus 500, and the like are not limited to those illustrated in FIG.
  • the information processing apparatus 500 may include a medium driving device that drives a portable storage medium such as a CD or a DVD.
  • a medium driving device that drives a portable storage medium such as a CD or a DVD.
  • the CPUs 510 and 511 read and execute a predetermined program from the portable storage medium via the medium driving device.
  • the live migration according to the present embodiment is realized.
  • FIG. 6 is a diagram for explaining the DMA processing operation in the north bridge 530.
  • the DMA packets 610 and 611 are packets as data transferred from the IO adapter 540, 541, or 542 to a predetermined transfer destination by DMA processing.
  • the IO table 620 indicates an IO table stored in the IO table storage unit 532.
  • the IO table 620 is an address conversion table between guest physical addresses and host physical addresses.
  • the IO table 620 defines a host physical address corresponding to an address composed of a guest physical address and a source ID.
  • the IO table 620 caches (temporarily holds) some entries that are frequently used among entries in a page table 630 described later.
  • the source ID is an ID (Identification Data) that identifies a packet transfer source unit.
  • a guest physical address is abbreviated as “GPA (Guest Physical Address)”
  • a host physical address is abbreviated as “HPA (Host Physical Address)”
  • a source ID is abbreviated as “SID (Source ID)” as necessary.
  • the page table 630 is an address conversion table for guest physical addresses and host physical addresses.
  • the page table 630 defines a host physical address corresponding to the guest physical address.
  • the IOMMU 531 When detecting the DMA packet 610, the IOMMU 531 acquires the guest physical address and the source ID from the header of the detected DMA packet 610. Then, the IOMMU 531 refers to the IO table 620. Then, the IOMMU 531 determines whether or not an address composed of the guest physical address and the source ID acquired from the DMA packet 610 is registered in the IO table 620.
  • the IOMMU 531 acquires a host physical address corresponding to an address composed of the guest physical address and the source ID.
  • the IOMMU 531 changes the guest physical address indicating the transfer destination set in the header of the DMA packet 610 to the host physical address acquired from the IO table 620.
  • the IOMMU 531 refers to the page table 630 stored in the memory 520.
  • the IOMMU 531 acquires the host physical address registered in the same address as the guest physical address acquired from the DMA packet 610, which is the address of the page table 630.
  • the IOMMU 531 changes the guest physical address indicating the transfer destination set in the header of the DMA packet 610 to the host physical address acquired from the page table 630.
  • FIG. 7 is a diagram for explaining the operation of DMA processing in the PCIe switch 550.
  • the dirty page management unit 551 includes a control I / F (Interface) unit 710, a packet detection unit 720, a write pointer 730, and a read pointer 740.
  • a dirty page storage unit 552 is described in the dirty page management unit 551.
  • the dirty page storage unit 552 includes memories # 0 and # 1 that realize a FIFO (First In First Out).
  • the memories # 0 and # 1 realizing the FIFO are referred to as “FIFO # 0” and “FIFO # 1”, respectively.
  • the control I / F unit 710 is an interface of the dirty page management unit 551.
  • the VMM 102 acquires dirty page information stored in the FIFO # 0 or # 1 via the control I / F unit 710.
  • the control I / F unit 710 includes a status register 711, a data register 712, and a control register 713.
  • the status register 711 is a register that can be read / written by software such as the VMM 102.
  • the status register 711 includes the following status display bits.
  • Overflow information bit # 0 indicates that FIFO # 0 has overflowed.
  • Overflow information bit # 1 indicates that FIFO # 1 has overflowed.
  • Valid data count # 0 In FIFO # 0, a value obtained by dividing the difference between the address indicated by the write pointer 730 and the address indicated by the read pointer 740 by the size of the dirty page information. It shows how much dirty page information that has not yet been read remains in FIFO # 0.
  • Valid data count # 1 In FIFO # 1, a value obtained by dividing the difference between the address indicated by the write pointer and the address indicated by the read pointer by the size of the dirty page information. This indicates how much dirty page information that has not yet been read remains in FIFO # 1.
  • the data register 712 is a register that can be read from software such as the VMM 102. This register is used to read data stored in the FIFO # 0 or # 1 from the VMM 102.
  • the dirty page management unit 551 sets the read pointer 740 to the address where the next dirty page information is stored.
  • the control register 713 is a register that can be read / written by software such as the VMM 102.
  • the control register 713 includes the following control bits.
  • Start bit Starts registration of dirty page information in FIFO # 0 or # 1.
  • Stop bit Stops registration of dirty page information in FIFO # 0 or # 1.
  • Write select bit Selects whether to register dirty page information in two FIFOs # 0 or # 1.
  • Read select bit Selects whether dirty page information is read from two FIFOs # 0 or # 1.
  • the packet detection unit 720 detects the DMA write packet 750 input to the PCIe switch 550 while the start bit of the control register 713 is set to “1”. Then, the packet detection unit 720 acquires the guest physical address and the source ID from the header of the detected DMA write packet 750. Further, the packet detection unit 720 writes the data including the acquired guest physical address and source ID as dirty page information in the currently selected FIFO # 0 or # 1. At the same time, the packet detection unit 720 sets the address of the area where dirty page information is stored next in the write pointer 730.
  • the write pointer 730 indicates the address of dirty page information last written to FIFO # 0 or # 1.
  • write pointers 730 are provided for FIFO # 0 and for FIFO # 1, respectively.
  • the read pointer 740 indicates the address of dirty page information last read from FIFO # 0 or # 1.
  • read pointers 740 are provided for FIFO # 0 and for FIFO # 1, respectively.
  • write pointer and read pointer for FIFO # 0 are stored in write pointer 730 and read pointer 740.
  • write pointer and read pointer for FIFO # 1 are stored in write pointer 730 and read pointer 740.
  • FIG. 8 is a diagram illustrating a configuration example of FIFO # 0.
  • FIG. 8 shows only FIFO # 0, but FIFO # 1 has the same configuration.
  • the FIFO # 0 includes a source ID that indicates an IO adapter that is a transmission source of a DMA packet, and a guest physical address [63:12] that indicates a transfer destination of the DMA packet.
  • the source ID is composed of a DMA packet transmission source bus number and a function number of the DMA packet transmission source.
  • the size of one page is, for example, 4 KB.
  • the lower 12 bits of the 64-bit address data represent an address in the same page. Therefore, in this embodiment, only the data of bits 63 to 12 in the guest physical address is registered in the FIFO # 0.
  • FIG. 9 shows a configuration example of the header of the DMA packet.
  • the header of the DMA packet conforms to the standard “PCI Express 2.0”.
  • the header 1101 of the DMA packet shown in (1) of FIG. 9 shows a configuration example of the header of the DMA packet when address data having a 32-bit width is used for the guest physical address.
  • a DMA packet header 1102 shown in (2) of FIG. 9 shows a configuration example of a DMA packet header when address data having a 64-bit width is used as a guest physical address.
  • R is a reserved area. “0” is always set. “Fmt (Format)” is 2-bit data indicating the presence / absence of data stored in the payload and the header length.
  • Type is 5-bit wide data indicating the type of packet.
  • TC Transaction Class
  • TD Transaction Layer Packet
  • ECRC Extended Cyclic Redundancy Check
  • EP Error Poisoned
  • Attr Attributes
  • AT Address Translation
  • Length 10-bit width data indicating the data length of data stored in the payload.
  • bus number is 8-bit data indicating the bus number of the transmission source of the DMA packet.
  • “Function number” is 8-bit data indicating the function number of the transmission source of the DMA packet.
  • Tag is 8-bit width data indicating the management number of the DMA packet.
  • Last DW BE is 4-bit width data indicating validity / invalidity of the Last DW Byte.
  • 1st DW BE is 4-bit data indicating the validity / invalidity of the 1st DW Byte.
  • Address is 30-bit or 62-bit address data.
  • FIG. 10 is a flowchart showing the registration process of dirty page information by the dirty page management unit 551. 10 indicates the FIFO set in the write select bit of the control register 713 in the FIFO # 0 or # 1.
  • the dirty page management unit 551 starts the registration process of dirty page information (step S1000). .
  • the packet detection unit 720 refers to the header of the DMA packet input to the PCIe switch 550 from an IO adapter such as the IO adapter 540, 541, or 542.
  • the packet detection unit 720 acquires “Fmt” and “Type” from the header of the DMA packet.
  • step S1002 Step S1001 YES.
  • Fmt 10 (binary number)
  • Type 00000 (binary number) indicates a DMA write packet. If the packet detection unit 720 determines that the DMA packet input to the PCIe switch 550 is not a DMA write packet, the packet detection unit 720 executes step S1001 again (NO in step S1001).
  • step S1002 the packet detection unit 720 determines whether the difference between the address pointed to by the write pointer 730 and the address pointed to by the read pointer 740 is equal to a value obtained by dividing the size of the FIFO by the size of the dirty page information. Is determined to be Full.
  • the packet detection unit 720 determines that the FIFO is full (YES in step S1002). In this case, the packet detection unit 720 moves the process to step S1003.
  • step S1003 when the packet detection unit 720 sets “1” in the overflow information bit of the status register 711, the process proceeds to step S1008. Then, the dirty page management unit 551 ends the dirty page information registration process.
  • step S1002 when the difference between the address pointed to by the write pointer 730 and the address pointed to by the read pointer 740 is not equal to the value obtained by dividing the size of the dirty page information by the size of the FIFO, the packet detection unit 720 indicates that the FIFO is not Full. (Step S1002 NO). In this case, the packet detection unit 720 moves the process to step S1004.
  • step S1004 the packet detection unit 720 acquires a source ID and a guest physical address from the header of the DMA write packet.
  • step S1005 the packet detection unit 720 registers data including the source ID and guest physical address acquired in step S1004 as dirty page information in the FIFO address indicated by the write pointer 730.
  • step S1006 the packet detection unit 720 increments the address stored in the write pointer 730 by the area size for storing the dirty page information.
  • step S1007 the packet detection unit 720 refers to the control register 713 provided in the control I / F unit 710. If “1” is set in the stop bit of the control register 713 (YES in step S1007), the packet detection unit 720 moves the process to step S1008. Then, the dirty page management unit 551 ends the dirty page information registration process.
  • step S1007 when the stop bit of the control register 713 is not “1”, the packet detection unit 720 moves the process to step S1001 (NO in step S1007).
  • FIG. 11 is a flowchart showing a process for outputting dirty page information by the dirty page management unit 551. Note that the FIFO described in FIG. 11 indicates the FIFO set in the read select bit of the control register 713 in the FIFO # 0 or # 1.
  • step S1101 when software such as the VMM 102 reads dirty page information from the data register 712 included in the dirty page management unit 551, the control I / F unit 710 shifts the processing to step S1102.
  • step S1102 the control I / F unit 710 increments the address stored in the read pointer 740 by the area size for storing dirty page information.
  • step S1103 the control I / F unit 710 acquires dirty page information from the FIFO address indicated by the read pointer 740 and latches it in the data register 712.
  • FIG. 12 is a diagram for explaining the outline of live migration according to the present embodiment.
  • the information processing system 1200 illustrated in FIG. 12 includes a server # 0, a server # 1 that is communicably connected to the server # 0 via a network, and storages # 0 and # that are shared by the server # 0 and the server # 1. 1.
  • Server # 0 is the information processing apparatus 500 shown in FIG.
  • the server # 0 is the information processing apparatus 501 shown in FIG.
  • the VMM # 0 operates.
  • VMM # 0 implements VM # 0 and VM # 1.
  • VMM # 1 operates on the server # 1.
  • VM # 0 occupies storage # 0
  • VM # 1 occupies storage # 1.
  • FIG. 13 is a flowchart illustrating an outline of live migration according to the present embodiment.
  • the VMM # 0 requests the VMM # 1 that is the migration destination of the VM # 0 to secure a memory area to be allocated to the new VM.
  • the memory area allocated to the VM is referred to as “VM area”.
  • VMM # 1 secures a VM area in a predetermined area of the memory provided in server # 1. Then, the server # 1 notifies the server # 0 that the reservation of the VM area has been completed.
  • step S1302. the VMM # 0 obtains data stored in the area of the host physical memory allocated to the migration target VM # 0 at a certain point in time. This data stored in the area of the host physical memory allocated to the VM at a certain point (check point) is called “snapshot”.
  • step S1303 the VMM # 0 sets the start bit of the control register 713 of the dirty page management unit 551 to “1”, and starts recording dirty page information.
  • step S1304 the VMM # 0 stores the snapshot acquired in step S1302 in a predetermined area of the memory provided in the migration destination server # 1 of the VM # 0, and stores the snapshot in the VM area secured in step S1301. make a copy.
  • step S1305 the VMM # 0 acquires the remaining number of dirty page information from the dirty page management unit 551 through the valid data count of the status register 711 of the control I / F unit 710. Then, VMM # 0 compares the number of remaining dirty page information with a predetermined threshold value.
  • step S1305 If the number of remaining dirty page information is greater than the threshold (YES in step S1305), the VMM # 0 proceeds to step S1306. If the number of remaining dirty page information is less than or equal to the threshold (NO in step S1305), the VMM # 0 moves the process to step S1307.
  • step S1306 the VMM # 0 receives all the dirty page information registered in the dirty page storage unit 552 from the dirty page management unit 551 through the data register 712 of the control I / F unit 710 to date. To get.
  • the VMM # 0 converts the guest physical address of the acquired dirty page information into a host physical address. Then, the VMM # 0 acquires data stored in the converted host physical address from the memory provided in the server # 0. The VMM # 0 then copies the acquired data to the VM area secured in step S1301, which is the memory area of the migration destination server # 1 of the VM # 0.
  • VMM # 0 moves the process to step S1305.
  • the processing in steps S1302 to S1306 described above is “pre-copy”.
  • the pre-copy is performed while VM # 0 continues the business. Therefore, VMM # 0 performs read / write processing for storage # 0 via IOMMU 531 even during pre-copy. Therefore, the following stop and copy is required.
  • step S1307 the VMM # 0 stops the operation of the VM # 0.
  • step S1308 the VMM # 0 executes the same process as in step S1306.
  • step S1309 the VMM # 0 notifies the VMM # 1 operating on the migration destination server # 1 of the VM # 0 that the memory copy has been completed.
  • step S1310 upon receiving a memory copy completion notification from the VMM # 0, the VMM # 1 starts the VM # 0 operation on the VMM # 1.
  • VMM # 1 moves the process to step S1311. Then, the VMMs # 0 and # 1 end the live migration.
  • FIG. 14 is a flowchart showing specific pre-copy processing.
  • the VMM # 0 initializes the FIFOs # 0 and # 1 by setting “1” to the clear bit of the control register 713 provided in the control I / F unit 710.
  • the VMM # 0 sets the FIFO for recording dirty page information to FIFO # 0 by setting the write select bit of the control register 713 to “0”. Similarly, the VMM # 0 sets the FIFO for reading dirty page information to FIFO # 0 by setting the read select bit of the control register 713 to “0”.
  • step S1402 the VMM # 0 starts recording dirty page information by setting the start bit of the control register 713 included in the dirty page management unit 551 to “1”.
  • step S1403 the VMM # 0 executes memory copy.
  • step S1403 the memory copy process described in steps S1302 to S1304 shown in FIG. 13 is performed.
  • step S1404 the VMM # 0 shifts to a wait state for a certain time.
  • the VMM # 0 moves the process to step S1405.
  • step S1405 the VMM # 0 sets “0” or “1” in the write select bit of the control register 713 provided in the control I / F unit 710 to change the FIFO for recording dirty page information.
  • VMM # 0 changes the FIFO for recording dirty page information to FIFO # 1 by setting the write select bit of the control register 713 to “1”. To do.
  • VMM # 0 sets the write select bit of the control register 713 to “0” to change the FIFO for recording dirty page information to FIFO # 0. change.
  • step S1406 the VMM # 0 reads the status register 711 provided in the control I / F unit 710.
  • step S1407 the VMM # 0 determines whether or not the overflow information bit of the currently selected FIFO is set to “1”.
  • step S1407 If the overflow information bit of the currently selected FIFO is set to “1” (step S1407: YES), the VMM # 0 moves the process to step S1408. In this case, the VMM # 0 interrupts the live migration being executed or starts over from the beginning.
  • step S1407 if the overflow information bit of the currently selected FIFO is set to “0” (NO in step S1407), VMM # 0 proceeds to step S1409.
  • step S1409 the VMM # 0 reads the data register 712 by the number set in the valid data count of the status register 711, and acquires dirty page information.
  • step S1410 the VMM # 0 extracts only the dirty page information whose source ID indicates the storage # 0 from the dirty page information read in step S1409.
  • step S1411 The dirty page information extracted in step S1410 or the processing of S1507 described later is referred to as “copyable dirty page information”.
  • step S1411 the VMM # 0 converts the guest physical address of the copy target dirty page information into a host physical address according to the page table 630.
  • step S1412 the VMM # 0 acquires the data stored in the host physical address of the copy target dirty page information from the memory 520 provided in the server # 0. Then, the VMM # 0 transfers the acquired data to the VMM # 1 that is the migration destination of the VM # 0.
  • step S1413 the VMM # 0 changes the FIFO for reading dirty page information by setting “0” or “1” to the read select bit of the control register 713 provided in the control I / F unit 710.
  • VMM # 0 sets the read select bit of the control register 713 to “1” to change the FIFO for reading dirty page information to FIFO # 1. .
  • VMM # 0 changes the FIFO for reading dirty page information to FIFO # 0 by setting the read select bit of the control register 713 to “0”. To do.
  • step S1414 the VMM # 0 determines whether or not the pre-copy completion condition is satisfied. In the process of step S1414, the process of step S1305 shown in FIG. 13 is performed.
  • step S1414 If it is determined that the pre-copy completion condition is satisfied (YES in step S1414), the VMM # 0 proceeds to step S1415. In this case, the VMM # 0 ends the pre-copy.
  • FIG. 15 is a flowchart showing specific processing of stop-and-copy.
  • VMM # 0 starts the stop-and-copy process.
  • the process proceeds to step S1501 (step S1500).
  • step S1501 VMM # 0 shifts to a wait state for a certain time. This is to wait until the DMA write process is completely stopped. When the predetermined time has elapsed, the VMM # 0 moves the process to step S1502.
  • step S1502 the VMM # 0 changes the FIFO for recording dirty page information by setting “0” or “1” to the write select bit of the control register 713 provided in the control I / F unit 710.
  • VMM # 0 changes the FIFO for recording dirty page information to FIFO # 1 by setting the write select bit of the control register 713 to “1”. To do.
  • VMM # 0 sets the write select bit of the control register 713 to “0” to change the FIFO for recording dirty page information to FIFO # 0. change.
  • step S1503 the VMM # 0 reads the status register 711 provided in the control I / F unit 710. Then, the VMM # 0 determines whether or not the overflow information bit of the currently selected FIFO is set to “1”.
  • step S1504 if the overflow information bit of the currently selected FIFO is set to “1” (YES in step S1504), VMM # 0 proceeds to step S1505. In this case, the VMM # 0 interrupts the live migration or starts over from the beginning.
  • step S1504 if the overflow information bit of the currently selected FIFO is set to “0” (NO in step S1504), the VMM # 0 moves the process to step S1506.
  • step S1506 the VMM # 0 reads the data register 712 by the number set in the valid data count of the status register 711, and acquires dirty page information.
  • step S1507 the VMM # 0 extracts from the dirty page information read in step S1506, the copy target dirty page information in which the source ID of the dirty page information indicates the storage # 0.
  • step S1508 the VMM # 0 converts the guest physical address of the copy target dirty page information into a host physical address according to the page table 630.
  • step S1509 the VMM # 0 determines whether there is data page information in the FIFO from the valid data count bit of the status register 711 provided in the control I / F unit 710.
  • step S1509 If the valid data count in the status register 711 is “0” (YES in step S1509), the VMM # 0 determines that the FIFO is empty, and the process proceeds to step S1510.
  • step S1510 the VMM # 0 acquires the data stored in the host physical address of the copy target dirty page information from the memory 520 provided in the server # 0. Then, the VMM # 0 transfers the acquired data to the VMM # 1 that is the migration destination of the VM # 0.
  • step S1511 when the VMM # 1 receives data from the VMM # 0, the VMM # 1 stores the received data in the VM area secured by the process of step S1301 shown in FIG.
  • step S1301 the VMM # 0 moves the process to step S1511. Then, the VMM # 0 ends the stop and copy (step S1511).
  • step S1509 determines that the valid data count of the status register 711 is not “0” in step S1509 (NO in step S1509), the VMM # 0 determines that the FIFO is not empty, and the process proceeds to step S1512.
  • step S1512 the VMM # 0 changes the FIFO for reading dirty page information by setting “0” or “1” to the read select bit of the control register 713 provided in the control I / F unit 710.
  • VMM # 0 sets the read select bit of the control register 713 to “1” to change the FIFO for reading dirty page information to FIFO # 1. .
  • VMM # 0 changes the FIFO for reading dirty page information to FIFO # 0 by setting the read select bit of the control register 713 to “0”. To do.
  • the VMM # 0 moves the process to step S1501.
  • the dirty page management unit 551 detects the DMA packet by the packet detection unit 720. .
  • the dirty page management unit 551 acquires the guest physical memory and the source ID from the header of the DMA packet and registers them in the FIFO # 0 or # 1 as dirty page information. To do.
  • the dirty page management unit 551 includes a CPU 510 or 511, that is, a control I / F unit 710 with the VMM realized by the CPU 510 or 511, and is registered in the FIFO # 0 or # 1 in response to a request from the VMM. Output dirty page information.
  • the VMM operating in the information processing apparatus 500 can acquire data on the memory 520 added, changed, or updated by the DMA write using the IOMMU 531 from the dirty page information.
  • the information processing apparatus 500 includes two FIFOs, FIFO # 0 and # 1, as the dirty page storage unit 552.
  • one of the FIFOs is a write target, it is possible to avoid contention between the read process and the write process for one FIFO by making the other FIFO a read target.
  • the dirty page information registration process to the FIFO and the dirty page information read process from the FIFO can be performed efficiently.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)

Abstract

L'invention porte sur un processeur d'informations équipé d'un moyen de mise en œuvre de processeur d'informations virtuel qui met en œuvre un ou plusieurs processeurs d'informations virtuels par la gestion de ressources matérielles ; un moyen de transmission de données qui transmet des données directement à partir d'un dispositif d'entrée-sortie qui commande une entrée-sortie de données avec un dispositif externe vers la première zone de mémoire affectée au processeur d'informations virtuel, par conversion d'une adresse dans une première zone de mémoire affectée virtuellement à un processeur d'informations virtuel en une adresse dans une seconde zone de mémoire qui est la mémoire réelle de la première zone de mémoire ; un moyen de détection de données transmises qui détecte des données directement transmises à partir du dispositif d'entrée-sortie vers la première zone de mémoire affectée au processeur d'informations virtuel ; un moyen d'enregistrement d'informations de mise à jour qui génère des informations de mise à jour appartenant à la première zone de mémoire qui est modifiée par les données détectées avec le moyen de détection de données transmises, et stocke les informations de mise à jour dans un moyen de stockage d'informations de mise à jour ; et un moyen de d'émission d'informations de mise à jour qui émet les informations de mise à jour stockées avec le moyen de stockage d'informations de mise à jour.
PCT/JP2009/001464 2009-03-30 2009-03-30 Processeur d'informations WO2010116402A1 (fr)

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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011221945A (ja) * 2010-04-14 2011-11-04 Hitachi Ltd データ転送装置、計算機システム及びメモリコピー装置
WO2012063334A1 (fr) * 2010-11-10 2012-05-18 株式会社日立製作所 Dispositif de contrôle de mémoire et commutateur d'e/s pour une aide à la migration en temps réel d'une machine virtuelle
JP2012128807A (ja) * 2010-12-17 2012-07-05 Fujitsu Ltd 情報処理装置
JP2012221063A (ja) * 2011-04-05 2012-11-12 Nippon Telegr & Teleph Corp <Ntt> 仮想マシン同期方法及びシステム及び運用系の仮想マシン及びプログラム
JP2014191752A (ja) * 2013-03-28 2014-10-06 Fujitsu Ltd マイグレーション処理プログラム，マイグレーション方法及びクラウドシステム
US8966480B2 (en) 2011-03-31 2015-02-24 Fujitsu Limited System for migrating a virtual machine between computers
JP2018500646A (ja) * 2014-11-12 2018-01-11 インテル コーポレイション グラフィックス仮想化を用いたホストコンピュータからの／ホストコンピュータへの仮想マシンのライブマイグレーション
CN110931072A (zh) * 2019-11-28 2020-03-27 深信服科技股份有限公司 一种坏道扫描方法、装置、设备及存储介质
CN112099908A (zh) * 2020-08-27 2020-12-18 腾讯科技（深圳）有限公司 虚拟机热迁移方法、装置和计算机设备
JP7497637B2 (ja) 2020-07-16 2024-06-11 富士通株式会社 情報処理装置およびアクセス制御プログラム

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002518734A (ja) * 1998-06-15 2002-06-25 サン・マイクロシステムズ・インコーポレーテッド マルチプロセッサ・システム用のブリッジにおけるメモリ・ページ変更のトラッキング
JP2008269600A (ja) * 2007-04-16 2008-11-06 Internatl Business Mach Corp <Ibm> 論理パーティションのマイグレーションを管理する方法、装置およびプログラム
JP2009217608A (ja) * 2008-03-11 2009-09-24 Hitachi Ltd 仮想計算機システム及びその制御方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002518734A (ja) * 1998-06-15 2002-06-25 サン・マイクロシステムズ・インコーポレーテッド マルチプロセッサ・システム用のブリッジにおけるメモリ・ページ変更のトラッキング
JP2008269600A (ja) * 2007-04-16 2008-11-06 Internatl Business Mach Corp <Ibm> 論理パーティションのマイグレーションを管理する方法、装置およびプログラム
JP2009217608A (ja) * 2008-03-11 2009-09-24 Hitachi Ltd 仮想計算機システム及びその制御方法

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011221945A (ja) * 2010-04-14 2011-11-04 Hitachi Ltd データ転送装置、計算機システム及びメモリコピー装置
WO2012063334A1 (fr) * 2010-11-10 2012-05-18 株式会社日立製作所 Dispositif de contrôle de mémoire et commutateur d'e/s pour une aide à la migration en temps réel d'une machine virtuelle
JPWO2012063334A1 (ja) * 2010-11-10 2014-05-12 株式会社日立製作所 仮想マシンのライブマイグレーションを支援するためのメモリ制御装置及びｉ／ｏスイッチ
US8924624B2 (en) 2010-12-17 2014-12-30 Fujitsu Limited Information processing device
JP2012128807A (ja) * 2010-12-17 2012-07-05 Fujitsu Ltd 情報処理装置
US8966480B2 (en) 2011-03-31 2015-02-24 Fujitsu Limited System for migrating a virtual machine between computers
JP2012221063A (ja) * 2011-04-05 2012-11-12 Nippon Telegr & Teleph Corp <Ntt> 仮想マシン同期方法及びシステム及び運用系の仮想マシン及びプログラム
JP2014191752A (ja) * 2013-03-28 2014-10-06 Fujitsu Ltd マイグレーション処理プログラム，マイグレーション方法及びクラウドシステム
JP2018500646A (ja) * 2014-11-12 2018-01-11 インテル コーポレイション グラフィックス仮想化を用いたホストコンピュータからの／ホストコンピュータへの仮想マシンのライブマイグレーション
CN110931072A (zh) * 2019-11-28 2020-03-27 深信服科技股份有限公司 一种坏道扫描方法、装置、设备及存储介质
CN110931072B (zh) * 2019-11-28 2022-03-22 深信服科技股份有限公司 一种坏道扫描方法、装置、设备及存储介质
JP7497637B2 (ja) 2020-07-16 2024-06-11 富士通株式会社 情報処理装置およびアクセス制御プログラム
CN112099908A (zh) * 2020-08-27 2020-12-18 腾讯科技（深圳）有限公司 虚拟机热迁移方法、装置和计算机设备

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