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WO2010140559A1 - Circuit convertisseur a/n de type à approximations successives - Google Patents

Circuit convertisseur a/n de type à approximations successives Download PDF

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Publication number
WO2010140559A1
WO2010140559A1 PCT/JP2010/059175 JP2010059175W WO2010140559A1 WO 2010140559 A1 WO2010140559 A1 WO 2010140559A1 JP 2010059175 W JP2010059175 W JP 2010059175W WO 2010140559 A1 WO2010140559 A1 WO 2010140559A1
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Prior art keywords
comparison
circuit
voltage
conversion
converter circuit
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PCT/JP2010/059175
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English (en)
Japanese (ja)
Inventor
文裕 井上
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ミツミ電機株式会社
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Publication of WO2010140559A1 publication Critical patent/WO2010140559A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/249—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors using clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter

Definitions

  • the present invention relates to a technique for improving conversion accuracy in a successive approximation AD converter circuit, and more particularly to a technique suitable for use in an AD converter circuit having a chopper comparator.
  • Portable electronic devices such as mobile phones, PDAs (Personal Digital Assistants), and digital cameras are equipped with a microprocessor to control the system inside the device, and the microprocessor monitors the temperature, battery voltage, etc. Control is in progress. Therefore, equipment is provided with sensors for detecting temperature, battery voltage, etc., and a microprocessor with an A / D conversion circuit for converting analog signals from these sensors into digital signals is used. There are many.
  • the A / D conversion circuit built in the microprocessor or the like has a small circuit scale.
  • an A / D conversion circuit for example, an A / D conversion circuit using a so-called chopper type comparator using a CMOS inverter as an amplifier as shown in FIG. 14 is known.
  • a switch (sampling switch) SS1 on the analog signal input side is turned on with the sampling clock short-circuited between the input and output terminals of the CMOS inverter, and the logical threshold voltage of the inverter is used as a reference.
  • the input signal Vin is sampled into the capacitor Cs.
  • the sampling switch SS1 is turned off, the switch SS2 on the comparison voltage input side is turned on, the comparison voltage Vref is applied to the sampling capacitor Cs, and the input and output of the CMOS inverter are shut off, whereby each inverter becomes an amplifier. Operates and changes output.
  • the output since the input is amplified by the three-stage inverter, the output becomes the power supply voltage Vcc or the ground potential GND which is almost at the logic level, and the determination result of the magnitude relation between Vin and Vref is output.
  • the noise generated in the CMOS inverter is represented by 2 kT / 3CL (k is Boltzmann constant, T is absolute temperature), where CL is the inverter load capacitance (parasitic capacitance). From this, it can be understood that the noise of the inverter can be reduced by increasing the load capacitance CL.
  • the size of the load capacity of the CMOS inverter in the chopper type comparator has a great influence on the operation speed, and the operation speed decreases when the load capacity is increased. Therefore, conventionally, the design is generally made so that the load capacity becomes small.
  • thermal noise taken into the sampling capacitor is represented by kT / C, in which the noise VR 2 generated by the resistor is integrated by a low-pass filter as shown in FIG.
  • the present invention has been made paying attention to the above-mentioned problems, and the object of the present invention is to reduce noise in the comparison circuit without reducing the apparent conversion speed in the successive approximation type AD conversion circuit.
  • An object of the present invention is to improve the AD conversion accuracy.
  • Another object of the present invention is to reduce erroneous comparison and determination and improve AD conversion accuracy in a successive approximation AD converter circuit.
  • Still another object of the present invention is to make it possible to correct errors due to noise and improve AD conversion accuracy in a successive approximation AD converter circuit.
  • a comparison circuit that includes a plurality of amplification stages connected in cascade via a coupling capacitor, determines the magnitude of the input analog voltage and the comparison voltage, a register that sequentially captures and holds the determination result of the comparison circuit, and a value of the register
  • a successive approximation AD converter circuit comprising a local DA converter circuit that converts the voltage into a voltage and generates the comparison voltage,
  • Load capacity adjustment means connected to the output terminal of the amplification stage of the comparison circuit;
  • a control circuit for generating a signal for changing the capacity value of the load capacity adjusting means; The capacity value of the load capacity adjusting means is reduced when converting the upper bits, and the capacity value of the load capacity adjusting means is increased when converting the lower bits.
  • the output voltage of the amplification stage of the conventional comparator circuit is longer in the initial stage of conversion, that is, in the upper bit comparison operation, until the target level is reached.
  • a comparison operation is performed at a high speed in order to reduce the load capacity of the amplification stage during the conversion of the upper bits, while the load capacity is increased during the conversion of the lower bits. Therefore, the settling time is longer than in the conventional case, but the noise reduction effect is enhanced.
  • the period of the clock for operating the comparison circuit is determined by the settling time of the most significant bit, even if the settling time of the lower bits becomes longer than before, the AD conversion time as a whole is not extended, Noise can be reduced and the occurrence of errors can be suppressed.
  • the settling time of the output voltage of the amplification stage to which the load capacity adjusting unit is connected is the same as the maximum settling time when the upper bit is converted.
  • the capacity value of the load capacity adjusting means is changed. As a result, it is possible to achieve both high speed comparison and low noise in a balanced manner, that is, maximum noise reduction within a range in which the apparent conversion speed is not lowered at all.
  • the load capacitance adjusting means includes one or more capacitive elements and a switch element connected in series with any one of the capacitive elements, and the switch element is turned on or off.
  • the capacity value is changed.
  • a comparison circuit that includes a plurality of amplification stages connected in cascade via a coupling capacitor, determines the magnitude of the input analog voltage and the comparison voltage, a register that sequentially captures and holds the determination result of the comparison circuit, and a value of the register
  • a successive approximation AD converter circuit comprising a local DA converter circuit that converts the voltage into a voltage and generates the comparison voltage, Load capacity adjustment means connected to the output terminal of the amplification stage of the comparison circuit
  • a switch capable of switching between one or more capacitors having one terminal connected to the input terminal of the first amplification stage of the comparison circuit and a voltage applied to the other terminal of the capacitor based on the output of the comparison circuit
  • a sub-DA conversion circuit having means; Generates a control signal for the sub-D / A converter circuit in accordance with the output of the comparison circuit, causes the comparison circuit to perform a redundant comparison, averages the output of the comparison circuit, and generates a correction signal for the register value
  • the comparison operation is performed at a high speed to reduce the load capacity of the amplification stage when converting the upper bits, while the load capacity is increased when converting the lower bits, so that the AD conversion time is not extended. It is possible to reduce noise and suppress the occurrence of errors, and obtain an AD conversion value in which an error due to switching noise is corrected by a redundancy comparison performed after a normal AD conversion operation.
  • control circuit causes the redundant comparison using the sub DA conversion circuit to be executed a plurality of times, and the result of the normal AD conversion operation using the local DA conversion circuit and the redundant comparison of the plurality of times are performed.
  • An averaging process with the result is performed, and the value of the register can be changed according to the result of the averaging process. This makes it possible to obtain a more accurate AD conversion value in which an error due to switching of the amplification stage is corrected.
  • a comparison circuit that includes a plurality of amplification stages connected in cascade via a coupling capacitor, determines the magnitude of the input analog voltage and the comparison voltage, a register that sequentially captures and holds the determination result of the comparison circuit, and a value of the register
  • a local DA converter circuit that converts the voltage into a voltage and generates the comparison voltage
  • a load capacity adjustment means connected to the output terminal of the amplification stage of the comparison circuit
  • the comparison circuit is A first comparison stage having a first amplification stage and a second comparison stage having a second amplification stage, each having a first amplification stage in common among the plurality of amplification stages and connected to each subsequent stage via a coupling capacitor;
  • a first comparison point shift circuit connected to the input terminal of the first amplification stage and a second comparison point shift circuit connected to the input terminal of the second amplification stage;
  • the comparison operation is performed at a high speed to reduce the load capacity of the amplification stage when converting the upper bits, while the load capacity is increased when converting the lower bits, so that the AD conversion time is not extended. Noise can be reduced and the occurrence of errors can be suppressed.
  • comparison is performed at two comparison points that avoid the original comparison point, erroneous determination is less likely to occur, and a first comparison unit and a second comparison unit are provided, and determination is performed in parallel by the two comparison units. As a result, the time required for conversion does not have to be long.
  • the local DA converter circuit performs the previous comparison operation in the next comparison operation.
  • the local DA converter circuit generates the same voltage as the comparison voltage in the previous comparison operation when the second code is generated.
  • the third code is generated, in the next comparison operation, the local DA converter circuit is configured to generate a voltage lower than the comparison voltage in the previous comparison operation.
  • the comparison voltage in the next comparison operation changes according to the previous comparison result, so that even if a comparison error occurs, the determination can be led in the direction of correcting the error in the subsequent comparison operation. A conversion result with few errors can be obtained.
  • each of the first comparison point shift circuit and the second comparison point shift circuit includes a first capacitor having one terminal connected to an input terminal of the first amplification stage or an input terminal of the second amplification stage.
  • the first comparison point shift circuit and the second comparison point shift circuit can be realized with a relatively simple circuit.
  • the successive approximation type AD converter circuit it is possible to improve the AD conversion accuracy by reducing noise in the comparison circuit without reducing the apparent conversion speed.
  • erroneous comparison and determination can be reduced and AD conversion accuracy can be improved.
  • FIG. 1 is a circuit configuration diagram showing an embodiment of a successive approximation AD converter circuit according to the present invention. It is explanatory drawing which shows the sampling capacitor Cs and the low-pass filter which makes the load capacity of an amplification stage C, and its input-output characteristic. It is a graph which shows the relationship between the number of conversion bits in a successive approximation type AD converter circuit, and the static time (maximum value) per bit. It is a graph which shows the relationship between the load capacity ratio of the amplification stage which becomes the same as the settling time of the conversion bit and the most significant bit in a successive approximation type AD converter circuit. It is a circuit diagram which shows the specific example of a load capacity adjustment means.
  • FIG. 3 is a circuit configuration diagram showing a second embodiment of a successive approximation AD converter circuit according to the present invention.
  • FIG. 3 is a circuit configuration diagram showing a second embodiment of a successive approximation AD converter circuit according to the present invention.
  • the AD conversion circuit of 3rd Embodiment it is explanatory drawing which shows the method of the process of the code which shows the comparison result of each bit taking 4 bit AD conversion as an example.
  • FIG. 10 is an operation explanatory diagram showing a part of the comparison operation of the (n ⁇ 1) th bit and the comparison operation of the (n ⁇ 2) th bit in the AD conversion circuit of the third embodiment.
  • FIG. 1 shows an embodiment of a successive approximation AD converter circuit according to the present invention.
  • the AD conversion circuit shown in FIG. 1 is a sample-and-hold circuit 11 that alternately samples an analog input Vin input to an analog input terminal and a comparison voltage Vref applied to a reference voltage terminal to hold a difference voltage.
  • a chopper comparator 12 that amplifies the differential voltage sampled by the sample and hold circuit 11, a successive approximation register 13 that sequentially captures the output of the chopper comparator 12, and a signal output from the register 13
  • the local DA conversion circuit 14 that outputs the voltage obtained by DA-converting the output code of the register 13 as the comparison voltage Vref to the sample and hold circuit 11 when the switch is switched, and the control that outputs the predetermined signal using the output of the comparator 12 as an input
  • Each CMOS inverter of the circuit 15 and the comparator 12 Comprising INV1, INV2, connected to the output terminal of INV3 load capacitance adjusting means 16a, 16b, and 16c.
  • the sample and hold circuit 11 includes a pair of sampling switches SS1 and SS2 that are complementarily turned on and off by a sampling clock ⁇ s and a clock / ⁇ s having a phase opposite to the sampling clock ⁇ s, a connection node between the switches SS1 and SS2, and the chopper comparator
  • the sampling capacitor Cs is connected between 12 input terminals.
  • the chopper comparator 12 has three CMOS inverters INV1, INV2, and INV3 connected in cascade through capacitors C2 and C3, and switches S1, S2, and S3 that short-circuit the input / output terminals for each inverter. It is set as the provided structure.
  • the switches S1, S2, and S3 are turned on during the sampling period, and the input and output of the inverters INV1, INV2, and INV3 are short-circuited.
  • the potential is equal to the threshold value VLT. Therefore, in the sample and hold circuit 11, the switch SS1 on the input terminal side is turned on by the sampling clock ⁇ s.
  • the input analog voltage Vin is sampled in the sampling capacitor Cs with reference to VLT. That is, Cs is charged with a charge corresponding to the potential difference between VLT and Vin.
  • the capacitors C2 and C3 are charged with voltages (VLT2-VLT1) and (VLT3-VLT2) which are the differences between the logic threshold values of the inverters.
  • the reference side switch SS2 is turned on by the sampling clock / ⁇ s.
  • the switches S1, S2, and S3 are turned off by ⁇ s and the input and output of the inverters INV1, INV2, and INV3 are cut off, so that each inverter operates as an amplifier and outputs according to the input potential. Change.
  • the potential difference (Vref ⁇ Vin) is transmitted to the input terminal of the first-stage inverter INV1 through the sampling capacitor Cs, and the potential difference is gradually amplified by the inverters INV1, INV2, and INV3.
  • the result of comparing the input analog voltage Vin and the comparison voltage Vref appears at the output of the inverter INV3.
  • Vin is higher than Vref
  • the output of the inverter INV3 is at a low level (ground potential GND)
  • Vin is lower than Vref
  • the output of the inverter INV3 is at a high level (power supply voltage Vdd).
  • the control circuit 15 generates clocks ⁇ s and / ⁇ s for the sample and hold circuit 11 and the comparator 12, and generates and outputs control signals for the load capacity adjusting means 16a, 16b and 16c.
  • the control circuit 15 includes a counter inside, for example, and is configured to generate a control signal while grasping how many bits of the comparison operation are being performed.
  • the output voltage of the amplification stage is the time until the output reaches the target level even if the input voltage rises sharply by the integration operation of the low pass filter of R and C as shown in FIG. It takes time, and the change in the reference voltage is larger at the initial stage of conversion, that is, the comparison operation of the upper bits. Therefore, the settling time until the voltage reaches the target level is long, and the number of comparisons is repeated to shift to the lower bits. The shorter the settling time.
  • the load capacity of each amplification stage of the comparator 12 is reduced during high-order bit conversion to perform high-speed comparison operation, and the load capacity is increased during low-order bit conversion.
  • the load capacity adjusting means 16a to 16c are controlled so that the noise reduction effect is enhanced. By performing such control, the occurrence of errors can be suppressed without extending the AD conversion time as a whole.
  • the present inventor examined the relationship between the number of AD conversion bits and the settling time for the AD conversion circuit as shown in FIG. 14, and found that the maximum value, that is, the most significant bit settling time and the number of AD conversion bits. There was a proportional relationship as shown in FIG.
  • the capacity value at each conversion bit necessary for setting the same time as the settling time of the most significant bit is 14 bits, 13 bits.
  • 12-bit and 11-bit AD converter circuits were estimated. Then, when the capacity ratio between the capacity value and the minimum load capacity value of the amplification stage (inverter) was obtained, the result shown in FIG. 4 was obtained.
  • the load capacity adjusting means 16a to 16c are controlled so that the load capacity increases according to the characteristics of FIG. 4 as the number of comparisons, that is, the conversion bit progresses, the occurrence of errors can be suppressed without extending the AD conversion time as a whole. Can do.
  • the capacity ratio is about twice when the sixth bit is converted, about four times for the third bit, about seven times for the first bit, and about It can be seen that it is sufficient to increase the number of bits by about 14 with 0 bits.
  • a circuit that changes the load capacity every time has a complicated configuration and an increased occupation area.
  • the capacity ratio does not change so much when converting the first bit, that is, the upper bits, the capacity value may be switched in several steps in the range below the characteristic lines in FIG.
  • FIGS. 5A to 5F show circuit examples of the load capacity adjusting means, respectively.
  • INVi is composed of a P-channel MOSFET (insulated gate field effect transistor) Q1 and an N-channel MOS transistor Q2 constituting each amplification stage (inverter) of the comparator 12. It is a CMOS inverter.
  • the load capacity adjusting means of FIG. 5A is composed of one capacitive element Cl1 and one on / off switch connected in series between the output node of the inverter and the grounding point. The capacitance value is changed by being turned on or off by a signal from the control circuit 15.
  • the load capacity adjusting means shown in FIG. 5B is composed of two series-type capacitative elements Cl1, Cl2 and Cl2 and an on / off switch in parallel.
  • the load capacity adjusting means shown in FIG. 5C includes two series-type capacitive elements Cl1, Cl2, a series-type capacitive element Cl3 connected in parallel with the Cl2, and an on / off switch.
  • the load capacity adjusting means shown in FIG. 5D includes two parallel capacitive elements Cl1 and Cl2, and an on / off switch connected in series with the Cl2.
  • the load capacity adjusting means of FIG. 5E is provided with an on / off switch in series with the capacitive element Cl1 of FIG. 5D.
  • the load capacity adjusting means in FIG. 5F includes two capacitive elements Cl1, Cl2 in series and on / off switches, and two capacitive elements Cl3, Cl4 in series connected to the connection node of Cl1 and Cl2.
  • Two capacitive elements Cl5 and Cl6 in series connected to the connection node of Cl3 and Cl4 and the on / off switch and one of the series configuration connected to the connection node of Cl5 and Cl6
  • FIGS. 5A to 5D are capable of switching the capacitance value in two stages
  • FIG. 5E is capable of switching in three stages
  • FIG. 5F is capable of switching in 12 stages.
  • 5A to 5F show specific examples in which the capacitance value can be switched stepwise, but a variable capacitance element whose capacitance value changes according to the applied voltage, such as a MOSFET gate capacitance or a varicap diode, is used. Then, the capacitance value may be changed.
  • the load capacity adjusting means is provided for each of the three amplification stages.
  • the load capacity adjusting means may be provided for one amplification stage or two amplification stages.
  • the input conversion noise of the noise generated in the second and subsequent amplification stages is smaller than that in the first stage
  • the load capacitance adjusting means is provided in only one amplification stage, the first amplification stage. It is desirable to provide in.
  • the load capacity adjusting means may be provided only in the second amplification stage.
  • load capacity adjusting means 16i is provided at the output of the inverter. You may do it.
  • a comparator provided with a feedback capacitor can reduce noise as compared with a comparator that does not have a feedback capacitor by itself, but noise can be further reduced by providing a load capacitance adjusting means.
  • the above embodiment assuming an AD conversion circuit with a fixed number of bits, when converting the upper bits, the load capacity of the amplification stage is reduced to increase the speed, and when converting the lower bits, the amplification stage
  • the above embodiment is applied to an AD converter circuit having a variable number of bits that can be converted, and the load capacity is increased when the number of bits is large.
  • noise may be reduced, and when the number of bits is small, the load capacity may be reduced to increase the speed.
  • the AD conversion circuit When the AD conversion circuit is mounted on an LSI such as a microprocessor having a CPU (central processing unit), a register capable of setting the load capacity value by the CPU is provided. It is also possible to configure the load capacity adjusting means to be controlled according to the set value.
  • FIG. 7 shows an embodiment of another AD conversion circuit suitable using a chopper type comparator having a load capacity adjustment function of the present invention.
  • a sub DA conversion circuit (SubDAC) 17 connected to the input terminal of the first stage CMOS inverter INV1 of the comparator 12 is provided.
  • the load capacity adjusting means 16 is connected to the output terminal of the first-stage CMOS inverter INV1.
  • Other CMOS inverters may be provided with load capacity adjusting means. Since the specific example and function of the load capacity adjusting means 16 are the same as those in the above embodiment, the description thereof is omitted.
  • the sub DA conversion circuit 17 is connected to the capacitors CDA1... CDAk, one terminal of which is connected to the input terminal of the first-stage inverter INV1, and to the other terminal of each capacitor CDA1.
  • Vref_h and Vref_l are voltages corresponding to an upper limit value and a lower limit value of a voltage range FSR (Full Scale Range) in which AD conversion is possible.
  • Capacity CDA1 ?? CDAk are each 2 0, 2 1, the capacitance value such that the relationship with the weight of the « 2 k-1 is set.
  • the local DA converter circuit 14 is a charge distribution type circuit using a weight capacitor
  • the smallest capacitor CDak is the same as the smallest capacitor among the weight capacitors constituting the local DA converter circuit.
  • the capacitance value is smaller than that.
  • the switches SW11... SW1k perform a switching operation of the voltage to be applied according to a signal from the control circuit 15.
  • the two weighted weight capacity constituting the local DA conversion circuit 14 0, 2 1, when Hence 2 n, k is a positive integer smaller than n. It is also possible to set the capacitance value of the largest weighted capacitance in the sub DA conversion circuit 16 to the same capacitance value as the smallest one of the weighted capacitances in the local DA conversion circuit 14.
  • the control circuit 15 is configured to have a function of averaging a plurality of redundant comparison results output from the comparator 12 by a redundant comparison operation described later.
  • a function can be constituted by a register (accumulator) for holding the redundant comparison result of the comparator 12 and an arithmetic circuit (adder) for averaging the redundant comparison results of a plurality of times.
  • the output of the comparator 12 can be supplied / shut off to the successive approximation register 13 via a transmission gate G1 such as an AND gate.
  • the transmission gate G1 is controlled by the control circuit 15 by the local DA conversion circuit 14.
  • the output of the comparator 12 is transmitted to the successive approximation register 13, and when the normal DA conversion is completed, the transmission of the output of the comparator 12 to the successive approximation register 13 is controlled.
  • FIG. 8 shows the level of the output voltage (Vref) of the local DA converter circuit for each cycle, with the horizontal axis representing the time axis.
  • a period indicated by a symbol T1 is a period in which a normal AD conversion operation using the local DA converter circuit 14 is performed, and the same number of times (n times) as the number of weighting capacitors while switching the DAC output. ) Is only compared.
  • a period indicated by a symbol T2 is a period in which a redundant comparison operation using the sub DA conversion circuit is performed, and the same sequence is repeated a plurality of times (m times) in the redundant comparison. In each redundancy comparison, the comparison is performed k times by switching the switches SW11... SW1k in FIG.
  • the redundant comparison performed after the normal AD conversion is started by using the conversion result obtained by the normal AD conversion as a start value, that is, without newly sampling while holding the AD conversion value in the successive approximation register.
  • the low-order bits of the normal AD conversion result and the k redundant comparison results are averaged, and the average value is determined according to the average value. Then, addition or subtraction is performed on a value obtained by normal AD conversion and held in the successive approximation register.
  • the voltage Vref_h is applied to the terminal of the largest capacitor CDAk by the changeover switch SW1k in the sub DA converter circuit, and the terminals of the capacitors CDAk-1 to CDA1 smaller than that.
  • the voltage Vref_l is applied to the switch SW1k-1 to SW11.
  • the voltage applied to the terminal of the largest capacitor CDAk is switched from Vref_h to Vref_l by the switch SW1k.
  • the same state as when the reference voltage Vref output from the local DA conversion circuit 14 is lowered is set.
  • the comparator 12 operates and performs comparison, and then, according to the output of the comparator, the voltage applied to the terminals of the capacitors CDAk-1 to CDA1 is set to Vref_h or Vref_l, whereby redundant comparison is performed. .
  • an SN ratio of 3 dB is improved by executing one redundancy comparison sequence after a normal AD conversion, and an SN ratio of 6 dB is executed by executing the redundancy comparison sequence three times, and the redundancy comparison sequence is executed 15 times. It was found that the SN ratio could be improved by 12 dB. Therefore, if the allowable deviation of the AD conversion output is 2 codes, +3 redundant comparisons are performed, if the allowable deviation is 3 codes, +6 redundant comparisons are performed, and if the allowable deviation is 4 codes, +15 times are compared. It is desirable to perform a redundant comparison.
  • an error is caused in the AD conversion result by taking in thermal noise generated by elements such as resistors and transistors during sampling or noise (substrate noise) due to leakage current flowing in the substrate into the sampling capacitor.
  • an error occurs in the AD conversion result due to switching noise generated in the amplification stage at the time of comparison.
  • FIG. 13A and 13B the analog input voltage is taken on the horizontal axis, and the relationship between the switching frequency of the inverter and the code change of the AD conversion output is shown.
  • FIG. 13A shows a case where the variation in switching frequency is small
  • FIG. 13B shows a case where the variation in switching frequency is large.
  • an AD converter circuit including a chopper comparator often has characteristics as shown in FIG. 13B.
  • the conversion result is taken over and the lower bit redundancy comparison is performed a plurality of times and averaged to obtain an output code near the center of the distribution of FIG. 13B.
  • a value obtained by correcting an error due to switching noise of the inverter or the like can be obtained.
  • the AD conversion circuit When the AD conversion circuit is mounted on an LSI such as a microprocessor having a CPU (central processing unit), a register capable of setting the values of k and m by the CPU is provided, and the control circuit 15 However, it is also possible to configure the sub DA conversion circuit 17 to operate with the number of comparisons corresponding to the set value of this register.
  • LSI such as a microprocessor having a CPU (central processing unit)
  • a register capable of setting the values of k and m by the CPU is provided, and the control circuit 15
  • the sub DA conversion circuit 17 it is also possible to configure the sub DA conversion circuit 17 to operate with the number of comparisons corresponding to the set value of this register.
  • FIG. 9 shows still another embodiment of the AD conversion circuit suitable for use with the chopper type comparator having the load capacity adjustment function of the present invention.
  • the load capacity adjusting means 16 is connected to the output terminal of the first-stage CMOS inverter INV1.
  • Other CMOS inverters may be provided with load capacity adjusting means. Since the specific example and function of the load capacity adjusting means 16 are the same as those in the above embodiment, the description thereof is omitted.
  • the chopper type comparator 12 includes three CMOS inverters INV1, INV21, INV31 connected in cascade via coupling capacitors C21, C31, and switches S1, S1 that short-circuit the input / output terminals for each inverter. S21 and S31 are provided, and the first comparator section CMP1 in which the comparison point shift circuit CPS1 is connected to the input side of the second-stage inverter INV21 and the first-stage inverter INV1 are shared, and the subsequent stages are connected via coupling capacitors C22 and C32.
  • the second comparator section CMP2 in which two CMOS inverters INV22 and INV32 are connected in cascade and the comparison point shift circuit CPS2 is connected to the input side of the inverter INV22, and the logic circuit section LG.
  • the outputs of the first and second comparator units CMP1 and CMP2 are supplied to the logic circuit unit LG, and the logic circuit unit LG generates control signals for the comparison point shift circuits CPS1 and CPS2 based on the two outputs. It is configured.
  • the switches S1, S21, and S31 are turned on during the sampling period and the inputs and outputs of the inverters INV1, INV21, and INV31 are short-circuited. Is equal to the potential. Therefore, in the sample and hold circuit 11, when the switch SS1 on the input terminal side is turned on by the sampling clock ⁇ s, the input analog voltage Vin is sampled in the sampling capacitor Cs with reference to VLT. That is, Cs is charged with a charge corresponding to the potential difference between VLT and Vin.
  • the coupling capacitors C21 and C31 are charged with voltages (VLT21 ⁇ VLT1) and (VLT31 ⁇ VLT21) which are the differences between the logic threshold values of the inverters.
  • Inverters INV22 and INV32 of the comparator unit CMP2 are turned on by the switches S22 and S32 between the input and output terminals, and similarly, the coupling capacitors C22 and C32 are charged with the voltage difference between the logic threshold values of the inverters.
  • the reference side switch SS2 is turned on by the sampling clock / ⁇ s.
  • the switches S1, S21, and S31 are turned off by ⁇ s and the input / output of the inverters INV1, INV21, and INV31 is cut off, so that each inverter operates as an amplifier and outputs according to the input potential. Change.
  • the potential difference (Vref ⁇ Vin) is transmitted to the input terminal of the first-stage inverter INV1 via the sampling capacitor Cs, and the potential difference is gradually amplified by the inverters INV1, INV21, INV31 in the first comparator unit CMP1. Go. Similarly, in the second comparator unit CMP2, the potential difference is gradually amplified by the inverters INV1, INV22, INV32. As a result, a result of comparing the input analog voltage Vin and the comparison voltage Vref appears at the outputs of the inverters INV31 and INV32.
  • the comparison point shift circuit CPS1 can be switched between a capacitor CS1 having one terminal connected to the input terminal of the inverter INV21 and a predetermined reference voltage Vref0 and Vref1 connected to the other terminal of the capacitor.
  • Switch SW11 The comparison point shift circuit CPS2 includes a capacitor CS2 having one terminal connected to the input terminal of the inverter INV22, and a switch SW12 connected to the other terminal of the capacitor and capable of switching between predetermined reference voltages Vref0 and Vref2. It is comprised by.
  • the capacitors CS1 and CS2 are the same as each other, and can have the same capacitance value as the smallest one of the weighting capacitors constituting the local DA converter circuit 14, for example.
  • the switches SW11 and SW12 perform a voltage switching operation so that voltages changing in opposite directions are applied to CS1 and CS2. That is, first, the same voltage reference voltage Vref0 is applied, then the voltage Vref1 higher than Vref0 is applied to one side, and the voltage Vref2 lower than Vref0 is applied to the other side. Be controlled. In addition, switching of the switches SW11 and SW12, that is, switching of the reference voltage is performed in synchronization with the sampling clock ⁇ s. Instead of applying the same voltage reference voltage Vref0 first, different voltages Vref1 and Vref2 are applied, and then a voltage Vref1 ′ higher than the first applied voltage Vref1 is applied to one and the other is lower than Vref2. The voltage Vref2 ′ may be applied.
  • the comparison point shift circuit CPS1 switches the voltage applied to the terminal of the capacitor CS1 in the direction of increasing from Vref0 to Vref1 during sampling and comparison operation, while the comparison point shift circuit CPS2 changes the capacitance CS2 of the capacitor CS1.
  • the comparison point shift circuit CPS1 extracts the charge from the capacitor C21, and the comparison point shift circuit CPS2 injects the charge into the capacitor C22.
  • the comparison point shift circuit CPS1 changes the comparison voltage (comparison point) to Vref + ⁇ V1
  • the comparison point shift circuit CPS2 outputs a determination result equivalent to the comparison point changed to Vref ⁇ V2. Will come to be.
  • ⁇ Vref1 Vref1 ⁇ Vref0
  • ⁇ Vref2 Vref0 ⁇ Vref2
  • ⁇ Vref1, ⁇ Vref2, CS1, and CS2 are set so as to satisfy ⁇ V1, ⁇ V2 ⁇ FS / 2 n * 2 (k ⁇ 2) during the k-th bit comparison operation. By doing so, a conversion result with few misjudgments can be obtained.
  • FS is a potential difference between an upper limit and a lower limit of a voltage range FSR (Full Scale Range) in which AD conversion is possible.
  • FIG. 11 shows a part of the comparison operation of the (n-1) th bit and the comparison operation of the (n-2) th bit.
  • two comparison points are set by avoiding the original comparison point, that is, the comparison point set in the one having only one comparator unit, and shifting the comparison point up and down. Further, the shift amount of the comparison point is made smaller as the number of comparisons is followed.
  • the determination result is represented by, for example, three types of codes (1,0), (0, 1), and (0, 0) according to the input voltage range.
  • the logic circuit unit LG of FIG. 9 is provided with a conversion circuit including a logic gate that generates the above three types of codes based on the outputs of the comparator units CMP1 and CMP2.
  • the conversion circuit generates a code of (1, 0) when the outputs of the comparator units CMP1 and CMP2 are 1, 1, and generates a code of (0, 1) when the outputs of the CMP1 and CMP2 are 0, 1.
  • a code (0, 0) is generated.
  • Such a circuit can be realized by an AND gate and an exclusive OR gate.
  • the comparison point is always lower in the comparator unit CMP2, and the outputs of CMP1 and CMP2 do not become 1 and 0. Therefore, there is no need to consider a code corresponding to such a case.
  • the comparison points are both shifted higher.
  • the determination result of the (n-1) th bit is (0, 1)
  • the comparison is performed by shifting the comparison point closer as shown in (2), and the determination result is (0, 0). If it is, the comparison is performed by shifting the comparison points downward as shown in (3). That is, the next comparison operation is performed in any of the ranges (1), (2), and (3) according to the determination result (code) of the previous comparison operation.
  • FIG. 12A shows an example of a change in the output voltage of the local DAC during the conversion operation when AD conversion is performed according to the principle as described above.
  • FIG. 12B shows a change in the output voltage of the local DAC when AD conversion is performed at the original comparison point using a conventional chopper comparator.
  • a single determination mistake particularly at an early stage, an erroneous determination is repeated with an inappropriate comparison voltage thereafter, and an incorrect AD conversion result is output as shown in FIG. 12B. There is.
  • the logic circuit portion LG of FIG. 9 is provided with an arithmetic circuit including a bit shifter (shift register), an adder, and the like.
  • the processing of the least significant bit is not limited to rounding down and may be rounded up.
  • the conventional chopper type comparator (corresponding to the first comparator unit) of FIG. 9 includes two inverters and two capacitive elements for AC coupling.
  • the second comparator unit and the comparison point shift circuit provided for each comparator unit there is an effect that a highly accurate AD conversion result can be obtained without extending the conversion time. .
  • the first-stage inverter INV1 is shared by the two comparator units, the output of the two comparator units is less likely to cause an error, and the scale of the added circuit can be reduced, greatly increasing the cost. It can be avoided.
  • ⁇ Vk ⁇ Vk while satisfying the condition of ⁇ Vk ⁇ FS / 2 n * 2 (k ⁇ 2).
  • the number of elements constituting the point shift circuit can be reduced and the area can be reduced.
  • the present invention is not limited to the above embodiment.
  • a comparator in which three stages of CMOS inverters are cascade-connected is shown, but two inverters may be cascade-connected, or four inverters may be cascade-connected.
  • the CMOS inverter is used as the amplification stage constituting the chopper type comparator, but a single-ended differential amplifier circuit or a differential input-differential output amplifier circuit is used instead of the CMOS inverter. May be.

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  • Analogue/Digital Conversion (AREA)

Abstract

Dans un circuit convertisseur A/N de type à approximations successives, la précision de la conversion A/N est améliorée en réduisant le bruit dans un circuit de comparaison, sans réduction de la vitesse de conversion apparente. L'invention concerne un circuit convertisseur A/N de type à approximations successives comportant un circuit comparateur, un registre et un circuit convertisseur A/N local. Le circuit comparateur présente plusieurs étages d'amplification connectés en cascade à une capacitance de couplage entre chaque paire d'étages adjacents, et détermine si une tension analogique entrée est supérieure ou inférieure à une tension de comparaison. Le registre récupère séquentiellement les résultats de la détermination du circuit comparateur et les mémorise. Le circuit convertisseur A/N local convertit une valeur du registre en une tension pour générer la tension de comparaison. Ce circuit convertisseur A/N comprend des unités d'ajustement de la capacitance de charge (16) et un circuit de commande (15), les valeurs de capacitance des unités d'ajustement de la capacitance de charge étant ajustées pour être moins élevées pour la conversion de bits d'ordre supérieur et plus élevées pour la conversion de bits d'ordre inférieur. Les unités d'ajustement de la capacitance de charge (16) sont connectées aux bornes de sortie des étages d'amplification concernés du circuit comparateur (11). Le circuit de commande (15) génère un signal permettant de modifier les valeurs de capacitance des unités d'ajustement de la capacitance de charge.
PCT/JP2010/059175 2009-06-03 2010-05-31 Circuit convertisseur a/n de type à approximations successives WO2010140559A1 (fr)

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JP2009133679A JP2010283484A (ja) 2009-06-03 2009-06-03 逐次比較型ａｄ変換回路
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61242420A (ja) * 1985-04-19 1986-10-28 Toshiba Corp Ａ／ｄ変換回路
JPH02246621A (ja) * 1989-03-20 1990-10-02 Fujitsu Ltd Ａ／ｄ変換器
JPH11205145A (ja) * 1998-01-14 1999-07-30 Mitsubishi Electric Corp Ａｄ変換器

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61242420A (ja) * 1985-04-19 1986-10-28 Toshiba Corp Ａ／ｄ変換回路
JPH02246621A (ja) * 1989-03-20 1990-10-02 Fujitsu Ltd Ａ／ｄ変換器
JPH11205145A (ja) * 1998-01-14 1999-07-30 Mitsubishi Electric Corp Ａｄ変換器

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