+

WO2010011399A3 - Procédés et circuits pour déjouer des attaques de sécurité de circuit intégré semi-invasives et non invasives - Google Patents

Procédés et circuits pour déjouer des attaques de sécurité de circuit intégré semi-invasives et non invasives Download PDF

Info

Publication number
WO2010011399A3
WO2010011399A3 PCT/US2009/043994 US2009043994W WO2010011399A3 WO 2010011399 A3 WO2010011399 A3 WO 2010011399A3 US 2009043994 W US2009043994 W US 2009043994W WO 2010011399 A3 WO2010011399 A3 WO 2010011399A3
Authority
WO
WIPO (PCT)
Prior art keywords
invasive
integrated circuit
methods
thwarting
semi
Prior art date
Application number
PCT/US2009/043994
Other languages
English (en)
Other versions
WO2010011399A2 (fr
Inventor
Lawrence T. Clark
Fionn Sheerin
Thomas Mozdzen
Original Assignee
Arizona Board Of Regents For And On Behalf Of Arizona State University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Arizona Board Of Regents For And On Behalf Of Arizona State University filed Critical Arizona Board Of Regents For And On Behalf Of Arizona State University
Publication of WO2010011399A2 publication Critical patent/WO2010011399A2/fr
Publication of WO2010011399A3 publication Critical patent/WO2010011399A3/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/86—Secure or tamper-resistant housings
    • G06F21/87—Secure or tamper-resistant housings by means of encapsulation, e.g. for integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Security & Cryptography (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention porte sur des procédés et des systèmes pour déjouer des attaques de sécurité semi-invasives et non invasives sur un circuit intégré. Les procédés et les systèmes rendent, de façon générale, une ingénierie inverse, une reconfiguration, un décryptage, une observation, ou toute combinaison de ceux-ci, des opérations internes du circuit intégré sensiblement plus difficiles voire impossibles sans endommager le circuit intégré.
PCT/US2009/043994 2008-05-14 2009-05-14 Procédés et circuits pour déjouer des attaques de sécurité de circuit intégré semi-invasives et non invasives WO2010011399A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US5315008P 2008-05-14 2008-05-14
US61/053,150 2008-05-14

Publications (2)

Publication Number Publication Date
WO2010011399A2 WO2010011399A2 (fr) 2010-01-28
WO2010011399A3 true WO2010011399A3 (fr) 2010-05-27

Family

ID=41570797

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2009/043994 WO2010011399A2 (fr) 2008-05-14 2009-05-14 Procédés et circuits pour déjouer des attaques de sécurité de circuit intégré semi-invasives et non invasives

Country Status (1)

Country Link
WO (1) WO2010011399A2 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2488583A (en) * 2011-03-03 2012-09-05 Nds Ltd Preventing unauthorized access to data stored in non-volatile memories
US9405917B2 (en) 2014-05-30 2016-08-02 Apple Inc. Mechanism for protecting integrated circuits from security attacks
US10579536B2 (en) 2016-08-09 2020-03-03 Arizona Board Of Regents On Behalf Of Arizona State University Multi-mode radiation hardened multi-core microprocessors
US9946899B1 (en) 2016-10-14 2018-04-17 Google Llc Active ASIC intrusion shield
US10262956B2 (en) 2017-02-27 2019-04-16 Cisco Technology, Inc. Timing based camouflage circuit
CN110768779A (zh) * 2019-01-16 2020-02-07 哈尔滨安天科技集团股份有限公司 一种防止侧信道信息泄漏的芯片电源电路
DE102019213707A1 (de) * 2019-09-10 2021-03-11 Carl Zeiss Meditec Ag Computer-Hardware für ein computergesteuertes Medizingerät und Verfahren zur Steuerung eines computergesteuerten Medizingeräts
CN110659510B (zh) * 2019-09-12 2021-10-26 苏州浪潮智能科技有限公司 一种配置文件解密方法、装置、设备及可读存储介质

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030014643A1 (en) * 2001-07-12 2003-01-16 Fujitsu Limited Electronic apparatus and debug authorization method
US20030219126A1 (en) * 2000-09-14 2003-11-27 Stmicroelectronics Sa Method for scrambling the current consumption of an integrated circuit
US20050241005A1 (en) * 2004-04-27 2005-10-27 Infineon Technologies Ag Data processing apparatus and method for operating a dual rail circuit component
US6973570B1 (en) * 1999-12-31 2005-12-06 Western Digital Ventures, Inc. Integrated circuit comprising encryption circuitry selectively enabled by verifying a device
US20060087883A1 (en) * 2004-10-08 2006-04-27 Irvine Sensors Corporation Anti-tamper module
GB2423425A (en) * 2005-02-18 2006-08-23 Cirrus Logic Inc A low-noise digital audio driver with a PMOS pull-down transistor

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6973570B1 (en) * 1999-12-31 2005-12-06 Western Digital Ventures, Inc. Integrated circuit comprising encryption circuitry selectively enabled by verifying a device
US20030219126A1 (en) * 2000-09-14 2003-11-27 Stmicroelectronics Sa Method for scrambling the current consumption of an integrated circuit
US20030014643A1 (en) * 2001-07-12 2003-01-16 Fujitsu Limited Electronic apparatus and debug authorization method
US20050241005A1 (en) * 2004-04-27 2005-10-27 Infineon Technologies Ag Data processing apparatus and method for operating a dual rail circuit component
US20060087883A1 (en) * 2004-10-08 2006-04-27 Irvine Sensors Corporation Anti-tamper module
GB2423425A (en) * 2005-02-18 2006-08-23 Cirrus Logic Inc A low-noise digital audio driver with a PMOS pull-down transistor

Also Published As

Publication number Publication date
WO2010011399A2 (fr) 2010-01-28

Similar Documents

Publication Publication Date Title
WO2010011399A3 (fr) Procédés et circuits pour déjouer des attaques de sécurité de circuit intégré semi-invasives et non invasives
USD697905S1 (en) Case for electronic device
USD921548S1 (en) Portion of a vehicle component having an icon
WO2008008623A3 (fr) Systèmes et techniques assurant une sécurité de trajet de données dans un dispositif de système sur une puce (soc)
WO2007120804A3 (fr) Multiplexage d'une interface de bus parallèle et d'une interface de mémoire flash
WO2009097979A3 (fr) Élément de sécurité
WO2007149621A3 (fr) Procédés et systèmes pour l'identification et l'authentification d'objets
FR2914378B1 (fr) Dispositif et clavette de verrouillage.
WO2008077038A3 (fr) Ensemble refroidisseur thermoélectrique direct
WO2008070269A3 (fr) Procédés, logiciel et systèmes d'imagerie
IL195570A0 (en) Method for designing clothing and equipment for law enforcement, and the method for homologating such clothing and equipment
WO2010084107A9 (fr) Circuit de cryptographie, protégé notamment contre les attaques par observation de fuites d'information par leur chiffrement
DE602006017285D1 (de) Kryptographisches Kommunikationssystem und -methode
WO2007049863A3 (fr) Suppression de retards dans des chemins de signal
WO2009067140A3 (fr) Transistor à effet de champ à jonction à ailette
WO2009154952A3 (fr) Systèmes et procédés permettant de déterminer au moins deux caractéristiques d'une tranche
WO2010129506A3 (fr) Dispositifs de blocage de suture et systèmes de blocage de suture
ATE533947T1 (de) Einsetzausrüstung und installationsverfahren
WO2009085274A3 (fr) Traitement de cicatrices anormales ou excessives
WO2010066639A3 (fr) Compositions d'éclaircissement de la peau avec des inhibiteurs d'acétylcholinestérase
WO2008069831A3 (fr) Spectroscopie biométrique passive
BRPI0815087A2 (pt) Processo, e aparelho ou componente eletrônico.
WO2011163580A3 (fr) Dispositif de liaison pour retenir un objet, tel qu'une clef, une médaille d'identité et autres
ZA200810449B (en) Method for designing clothing and equipment for law enforcement, and the method for homologating such clothing and equipment
WO2011042743A3 (fr) Dispositif médical amélioré

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09800729

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 09800729

Country of ref document: EP

Kind code of ref document: A2

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载