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WO2010087009A1 - Electronic device, test equipment, and test method - Google Patents

Electronic device, test equipment, and test method Download PDF

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Publication number
WO2010087009A1
WO2010087009A1 PCT/JP2009/051649 JP2009051649W WO2010087009A1 WO 2010087009 A1 WO2010087009 A1 WO 2010087009A1 JP 2009051649 W JP2009051649 W JP 2009051649W WO 2010087009 A1 WO2010087009 A1 WO 2010087009A1
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WO
WIPO (PCT)
Prior art keywords
electronic device
signal
clock signal
data signal
test
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PCT/JP2009/051649
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French (fr)
Japanese (ja)
Inventor
健一 長谷
Original Assignee
株式会社アドバンテスト
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Publication date
Application filed by 株式会社アドバンテスト filed Critical 株式会社アドバンテスト
Priority to JP2010548337A priority Critical patent/JPWO2010087009A1/en
Priority to PCT/JP2009/051649 priority patent/WO2010087009A1/en
Publication of WO2010087009A1 publication Critical patent/WO2010087009A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31708—Analysis of signal quality
    • G01R31/31711—Evaluation methods, e.g. shmoo plots

Definitions

  • the present invention relates to an electronic device that inputs a data signal and a clock signal indicating a timing at which the data signal should be acquired, a test apparatus and a test method for testing such an electronic device.
  • An electronic device that uses a source-synchronous interface is known. This electronic device inputs and outputs a clock signal indicating the timing at which the data signal should be acquired in parallel with the data signal.
  • a test apparatus for testing an electronic device is also known. The test apparatus uses a strobe signal or timing signal with a fixed generation timing to acquire a signal output from the electronic device and generate a signal to be given to the electronic device.
  • an electronic device adopting a source synchronous interface includes phase jitter, phase drift, and skew in data signals and clock signals to be output and input.
  • phase jitter or the like does not affect normal communication between devices, but affects communication with a test apparatus using fixed strobe signals and timing signals. Therefore, when testing such an electronic device, the test apparatus increases the timing margin in signal generation and capture so that the phase jitter, phase drift and skew included in the data signal and clock signal do not affect the test results. It was provided.
  • an object of one aspect of the present invention is to provide an electronic device, a test apparatus, and a test method that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims.
  • the dependent claims define further advantageous specific examples of the present invention.
  • an electronic device for inputting a data signal and a clock signal indicating a timing at which the data signal is to be acquired, the data input for inputting the data signal
  • a clock input terminal for inputting the clock signal
  • an acquisition circuit for acquiring the data signal at a timing according to the clock signal
  • the clock signal instead of the data signal when testing the electronic device.
  • An electronic device comprising: a test circuit that switches whether or not the acquisition circuit acquires the signal.
  • a test apparatus for testing an electronic device that inputs a data signal and a clock signal indicating a timing at which the data signal is to be acquired, and the electronic device inputs the data signal.
  • a test circuit for switching whether or not the acquisition circuit acquires the clock signal and the test apparatus includes the test circuit so that the acquisition circuit acquires the clock signal instead of the data signal.
  • a control unit that performs control to supply the clock signal to the electronic device, and the data signal. Based on the result of the acquired said clock signal to said acquisition circuit in place, to provide a test apparatus including a quality determination unit for determining the electronic device.
  • a test method for testing an electronic device that inputs a data signal and a clock signal indicating a timing at which the data signal is to be acquired, wherein the electronic device inputs the data signal.
  • a data input terminal; a clock input terminal for inputting the clock signal; an acquisition circuit for acquiring the data signal at a timing according to the clock signal; and when testing the electronic device, the data signal instead of the data signal A test circuit that switches whether or not to cause the acquisition circuit to acquire a clock signal, and controls the test circuit to cause the acquisition circuit to acquire the clock signal instead of the data signal.
  • the clock signal is supplied to an electronic device, and the clock signal is replaced with the data signal instead of the data signal. Based on the result of the acquisition, it provides an acceptability determining test method the electronic device.
  • FIG. 1 shows an electronic device 10 and a test apparatus 20 according to this embodiment.
  • FIG. 2 shows the configuration of the electronic device 10 and the test apparatus 20 according to the present embodiment.
  • FIG. 3 shows an example of the timing of the data signal and the clock signal.
  • FIG. 4 shows the flow of data signals and clock signals when the electronic device 10 operates normally.
  • FIG. 5 shows an example of an operation flow of the test apparatus 20 when testing the electronic device 10.
  • FIG. 6 shows a signal flow when the delay amount set value in step S11 is detected.
  • FIG. 7 shows a signal flow when the electronic device 10 in step S12 and step S13 is tested.
  • FIG. 8 shows a configuration of the electronic device 10 and the test apparatus 20 according to a modification of the present embodiment.
  • FIG. 1 shows an electronic device 10 and a test apparatus 20 according to this embodiment.
  • the electronic device 10 employs a source synchronous interface, and inputs a data signal and a clock signal indicating timing to acquire the data signal.
  • the electronic device 10 inputs a data signal having a period of, for example, twice, four times,... With respect to the period of the clock signal.
  • the data signal input by the electronic device 10 has a transfer rate that is twice that of the clock signal, and the edge phase coincides with the timing of the rising edge and the falling edge of the clock signal.
  • the test apparatus 20 tests the electronic device 10. As an example, the test apparatus 20 provides a test signal to the electronic device 10 and receives a response signal output in response to the provision of the test signal. Then, the test apparatus 20 determines whether the electronic device 10 is acceptable by determining whether an expected response signal has been received.
  • FIG. 2 shows the configuration of the electronic device 10 and the test apparatus 20 according to the present embodiment.
  • the electronic device 10 according to the present embodiment includes a data input terminal 32, a clock input terminal 34, an acquisition circuit 36, an internal circuit 38, and a test circuit 40.
  • the data input terminal 32 inputs a data signal supplied from the outside.
  • the clock input terminal 34 inputs a clock signal supplied from the outside.
  • the acquisition circuit 36 acquires the data signal input from the data input terminal 32 at a timing corresponding to the clock signal input from the clock input terminal 34.
  • the acquisition circuit 36 includes a 90-degree phase delay device 42, a first latch 44, a second latch 46, and a transfer unit 48.
  • the 90-degree phase delay device 42 delays the clock signal input from the clock input terminal 34 by a phase of 90 degrees.
  • the first latch 44 acquires the value of the data signal input from the data input terminal 32 at the timing of the rising edge of the clock signal delayed by the 90-degree phase delay unit 42.
  • the second latch 46 acquires the value of the data signal input from the data input terminal 32 at the timing of the falling edge of the clock signal delayed by the 90-degree phase delay device 42.
  • the transfer unit 48 buffers the data string of the values acquired by the first latch 44 and the data string of the values acquired by the second latch 46 and transfers them to the internal circuit 38 at the subsequent stage.
  • Such an acquisition circuit 36 can acquire the value of the data signal at the phase timings of 90 degrees and 270 degrees of the clock signal. That is, such an acquisition circuit 36 can acquire the value of the data signal having a transfer rate twice that of the clock signal at the center phase timing of the data signal (timing of 180 degrees in phase).
  • the acquisition circuit 36 When the transfer rate of the data signal is higher than twice the transfer rate of the clock signal, the acquisition circuit 36 has a plurality of latches corresponding to the multiple of the rate. Then, the acquisition circuit 36 acquires the data signal at each of a plurality of types of timings according to the clock signal, using such a plurality of latches.
  • the internal circuit 38 operates in accordance with the data string acquired by the acquisition circuit 36.
  • the internal circuit 38 may be a circuit that processes a data string read from the memory.
  • the test circuit 40 switches whether the acquisition circuit 36 acquires the clock signal instead of the data signal when the test apparatus 20 tests the electronic device 10. In addition, when the test apparatus 20 tests the electronic device 10, the test circuit 40 determines whether the electronic device 10 is acceptable based on the result of comparing the value of the data signal acquired by the acquisition circuit 36 with an expected value. To do. Then, the test circuit 40 transmits the determination result to the test apparatus 20 as a response signal.
  • the test circuit 40 includes a selection unit 52, a variable delay unit 54, a fixed delay unit 56, and a loopback switching unit 58.
  • the selection unit 52 selects which of the data signal and the clock signal is supplied to the acquisition circuit 36 for acquisition in accordance with an instruction from the external test apparatus 20. Note that in a state where the electronic device 10 normally operates, the selection unit 52 causes the acquisition circuit 36 to acquire a data signal.
  • variable delay unit 54 the delay amount is varied in accordance with an instruction from the external test apparatus 20.
  • the variable delay unit 54 delays one of the data signal input from the data input terminal 32 and the clock signal input from the clock input terminal 34 with respect to the other, and supplies the delayed signal to the acquisition circuit 36.
  • variable delay unit 54 delays the clock signal input from the clock input terminal 34 and supplies it to the acquisition circuit 36.
  • the variable delay unit 54 may be configured to delay the data signal input from the data input terminal 32 and supply the delayed data signal to the acquisition circuit 36 via the selection unit 52. Note that in a state where the electronic device 10 normally operates, the variable delay unit 54 delays a given signal by a reference delay amount.
  • the variable delay unit 54 delays one of the data signal input from the data input terminal 32 or the clock signal input from the clock input terminal 34 that is delayed by the variable delay unit 54.
  • the other signal that has not been supplied is delayed and supplied to the acquisition circuit 36.
  • the fixed delay unit 56 delays the given signal by the delay amount (reference delay amount) of the variable delay unit 54 in a state where the electronic device 10 normally operates.
  • the fixed delay unit 56 delays the data signal input from the data input terminal 32 and supplies the delayed data signal to the acquisition circuit 36.
  • the variable delay unit 54 delays the data signal input from the data input terminal 32
  • the fixed delay unit 56 delays the clock signal input from the clock input terminal 34 and supplies it to the acquisition circuit 36.
  • the loopback switching unit 58 delays a signal input from the outside by one of the data input terminal 32 or the clock input terminal 34 by the variable delay unit 54 and outputs the signal from the other to the outside. Switch whether to output. In the present embodiment, the loopback switching unit 58 switches whether or not to connect between the terminal to which the clock input terminal 34 of the variable delay unit 54 is not connected and the data input terminal 32.
  • variable delay unit 54 delays the data signal input from the data input terminal 32, is the connection between the end of the variable delay unit 54 to which the data input terminal 32 is not connected and the clock input terminal 34 connected? Switch between no.
  • the loopback switching unit 58 opens the space between the data input terminal 32 and the clock input terminal 34.
  • the in-device determination unit 60 determines pass / fail based on the result of comparing the signal acquired by the acquisition circuit 36 with the expected value when the test apparatus 20 tests the electronic device 10. Then, the in-device determination unit 60 transmits the determination result to the test apparatus 20 as a response signal.
  • the test apparatus 20 includes a phase difference detection unit 101, a signal generation unit 102, a control unit 103, a storage unit 104, a test unit 105, and a calibration unit 106.
  • the phase difference detection unit 101 measures the phase or delay amount of the signal received from the electronic device 10.
  • the signal generator 102 supplies a signal to the electronic device 10.
  • the control unit 103 performs settings for the electronic device 10. More specifically, the control unit 103 gives a setting value to the variable delay unit 54 to change the delay amount.
  • the control unit 103 also controls switching of the selection unit 52 and the loopback switching unit 58 of the electronic device 10.
  • the storage unit 104 stores the delay amount setting value detected by the calibration unit 106.
  • the test unit 105 is realized, for example, by an arithmetic processing unit such as a CPU executing a test program.
  • the test unit 105 controls the selection unit 52 of the test circuit 40 so that the acquisition circuit 36 acquires the clock signal instead of the data signal, and sends the clock signal to the electronic device 10.
  • the supply control is executed.
  • test unit 105 executes control to set a setting value for shifting the data signal and the clock signal by the reference delay amount used in the normal operation of the electronic device in the variable delay unit 54.
  • test unit 105 variably sets a delay amount setting value for shifting the data signal and the clock signal by a predetermined offset delay amount with respect to a reference delay amount used in the normal operation of the electronic device 10. The control set in the delay unit 54 is executed.
  • the calibration unit 106 is realized by an arithmetic processing device such as a CPU executing a calibration program.
  • the calibration unit 106 gives a signal to one of the data input terminal 32 or the clock input terminal 34, and sets the delay amount of the variable delay unit 54 as a reference based on the signal output from the other through the variable delay unit 54.
  • a delay amount setting value that is shifted by an offset delay amount with respect to the delay amount is detected.
  • the calibration unit 106 sets a negative delay amount setting value that delays the phase of the data signal by the offset delay amount from the phase of the clock signal, and the phase of the data signal by the offset delay amount from the phase of the clock signal.
  • the positive delay amount set value to be advanced is detected.
  • FIG. 3 shows an example of the timing of the data signal and the clock signal.
  • the phase difference between a data signal and a clock signal applied to the device under test is tested as a standard state (state (A) in FIG. 3).
  • the test may be performed with the phase difference between the data signal applied to the device under test and the clock signal shifted from the standard state by a predetermined phase (states (B) and (C) in FIG. 3). According to the tests in the states of (B) and (C) of FIG. 3, even if the phase difference between the applied data signal and the clock signal is shifted to the upper limit or the lower limit determined by the specifications, the device under test It can be determined whether the device can acquire correct data.
  • the delay amount setting value is, for example, the setting value of the variable delay unit 54 that gives the upper or lower phase difference determined by the specification between the data signal acquired by the acquisition circuit 36 and the clock signal.
  • the calibration unit 106 detects a delay amount setting value that causes such a phase difference between the data signal and the clock signal prior to the test.
  • FIG. 4 shows the flow of data signals and clock signals when the electronic device 10 normally operates.
  • the selection unit 52 supplies the data signal input from the data input terminal 32 to the acquisition circuit 36.
  • the variable delay unit 54 delays the clock signal input from the clock input terminal 34 by a reference delay amount. Further, the loopback switching unit 58 opens between the data input terminal 32 and the clock input terminal 34.
  • the test circuit 40 supplies the data signal input from the data input terminal 32 to the acquisition circuit 36 after the fixed delay unit 56 delays the data signal by the reference delay amount.
  • the variable delay unit 54 delays the input clock signal by the reference delay amount and supplies it to the acquisition circuit 36.
  • the test circuit 40 can supply the data to the acquisition circuit 36 without shifting the phase relationship between the data signal input from the data input terminal 32 and the clock signal input from the clock input terminal 34.
  • FIG. 5 shows an example of the operation flow of the test apparatus 20 when testing the electronic device 10.
  • the test apparatus 20 performs the following steps S11 to S13 in a test before shipping the electronic device 10 or the like.
  • step S11 the test apparatus 20 sets a delay amount for setting the variable delay unit 54 to a delay amount shifted from a reference delay amount used during normal operation of the electronic device 10 by a predetermined offset delay amount. Detect value.
  • step S ⁇ b> 12 the test apparatus 20 tests the electronic device 10 using the variable delay unit 54 as a delay amount (reference delay amount) used during normal operation of the electronic device 10.
  • step S ⁇ b> 13 the test apparatus 20 tests the electronic device 10 with the delay amount setting value set in the variable delay unit 54.
  • the test apparatus 20 tests the electronic device 10 using the variable delay unit 54 as a delay amount that is shifted from the reference delay amount used during the normal operation of the electronic device 10 by a predetermined offset delay amount.
  • FIG. 6 shows a signal flow when the delay amount set value in step S11 is detected.
  • the calibration unit 106 receives a signal input from the outside from either the data input terminal 32 or the clock input terminal 34 to the control unit 103, as a variable delay unit. It is instructed to delay the output by 54 and output from the other side to the outside.
  • the control unit 103 loops back so that a signal input from the outside by either the data input terminal 32 or the clock input terminal 34 is delayed by the variable delay unit 54 and output from the other to the outside.
  • the switching unit 58 is switched.
  • the calibration unit 106 instructs the control unit 103 to connect the clock input terminal 34 and the data input terminal 32 via the variable delay unit 54.
  • the calibration unit 106 instructs the signal generation unit 102 to supply a signal to one of the data input terminal 32 and the clock input terminal 34. Further, the calibration unit 106 gives an instruction to the phase difference detection unit 101 to detect the phase difference between the signal output to one terminal and the signal output from the other terminal.
  • the signal generator 102 supplies a signal to one of the data input terminal 32 and the clock input terminal 34. Also, the phase difference detection unit 101 acquires a signal output from the other terminal via the variable delay unit 54 and the loopback switching unit 58, and a signal input to one terminal and a signal output from the other terminal The phase difference between and is detected.
  • the calibration unit 106 receives the phase difference detected by the phase difference detection unit 101. In this way, the calibration unit 106 gives a signal to one of the data input terminal 32 or the clock input terminal 34 and acquires a signal output from the other via the variable delay unit 54 and the loopback switching unit 58. Thus, the time difference from the timing when the signal is applied to one terminal to the timing when the signal is output from the other terminal is measured.
  • the calibration unit 106 performs such time difference measurement a plurality of times.
  • the calibration unit 106 gives an instruction to the control unit 103 to sequentially change the setting value to be given to the variable delay unit 54 in each execution.
  • the control unit 103 sequentially changes the set value to be given to the variable delay unit 54.
  • the calibration unit 106 detects a delay amount setting value that shifts the delay amount of the variable delay unit 54 from the reference delay amount by the offset delay amount from the measurement result of the time difference between the respective setting values.
  • the calibration unit 106 sets the negative delay amount setting value that shifts the delay amount of the variable delay unit 54 to the negative side by the offset delay amount with respect to the reference delay amount, and the reference delay amount.
  • the positive delay amount set value shifted by the offset delay amount to the positive side is detected. Then, the calibration unit 106 stores the delay amount setting value thus detected in the storage unit 104.
  • FIG. 7 shows a signal flow when the electronic device 10 in step S12 and step S13 is tested.
  • the test unit 105 acquires the clock signal input from the clock input terminal 34 instead of the data signal input from the data input terminal 32 to the control unit 103. Instruct the circuit 36 to acquire.
  • the control unit 103 switches the selection unit 52 so that the acquisition circuit 36 acquires the clock signal input from the clock input terminal 34.
  • the test unit 105 instructs the control unit 103 to set the delay amount of the variable delay unit 54 as the reference delay amount.
  • the control unit 103 gives a setting value to the variable delay unit 54 when the electronic device 10 normally operates.
  • the test unit 105 instructs the control unit 103 to set the delay amount of the variable delay unit 54 to a delay amount that is offset from the reference delay amount by the offset delay amount. To do.
  • the control unit 103 reads the delay amount setting value from the storage unit 104 and sets the read delay amount setting value in the variable delay unit 54.
  • step S13 each of the state in which the negative delay amount set value is set in the variable delay unit 54 and the state in which the positive delay amount set value is set in the variable delay unit 54 Device 10 is tested.
  • the test unit 105 determines whether the electronic device 10 is good or bad based on the result of causing the acquisition circuit 36 to acquire the clock signal instead of the data signal. In the present embodiment, the test unit 105 gives an instruction to generate a clock signal to the signal generation unit 102. Further, the test unit 105 gives an instruction to the electronic device 10 for obtaining and determining a given signal.
  • the signal generator 102 gives a clock signal to the clock input terminal 34.
  • the acquisition circuit 36 acquires the value of the clock signal supplied instead of the data signal based on the timing of the clock signal delayed by the variable delay unit 54.
  • the in-device determination unit 60 compares the value acquired by the acquisition circuit 36 with the expected value, and transmits the comparison result to the test unit 105. Then, the test unit 105 determines that the electronic device 10 is a non-defective product when the acquired value matches the expected value, and the electronic device 10 is a defective product when the acquired value does not match the expected value. Judge.
  • the internal test circuit 40 causes the acquisition circuit 36 to acquire the clock signal instead of the data signal. Therefore, the test apparatus 20 need only supply a clock signal to the electronic device 10 during the test. Thereby, according to the electronic device 10 and the test apparatus 20, the phase jitter, the phase drift, and the skew included between the data signal and the clock signal can be extremely reduced, and the electronic device 10 can be accurately tested. it can.
  • the electronic device 10 includes a loopback switching unit 58 that connects the data input terminal 32 and the clock input terminal 34 via the variable delay unit 54 during the test. Therefore, according to the electronic device 10 and the test apparatus 20, when testing in a state in which the phase of the data signal and the clock signal is shifted by a predetermined offset delay amount, the delay amount can be accurately calibrated at a low cost. Can do.
  • FIG. 8 shows the configuration of the electronic device 10 and the test apparatus 20 according to a modification of the present embodiment. Since the electronic device 10 and the test apparatus 20 according to the present modification have substantially the same configuration and function as the members having the same reference numerals shown in FIG. 2, the description thereof will be omitted except for the following differences.
  • the test circuit 40 according to the present modification does not have the in-device determination unit 60 and transfers the signal acquired by the acquisition circuit 36 to the test apparatus 20 as a response signal.
  • the test apparatus 20 according to this modification further includes a determination unit 107.
  • the determination unit 107 receives the response signal from the test circuit 40 and determines whether the electronic device 10 is good or bad based on the result obtained by causing the acquisition circuit 36 to acquire the clock signal instead of the data signal.
  • the electronic device 10 and the test apparatus 20 according to such a modification can reduce the configuration of the test circuit 40 of the electronic device 10.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

Test equipment is used for testing an electronic device receiving a data signal and a clock signal indicating a timing at which the data signal should be acquired. The electronic device comprises a data input terminal for receiving the data signal, a clock input terminal for receiving the clock signal, an acquisition circuit for acquiring the data signal at a timing corresponding to the clock signal, and a test circuit for, when the electronic device is tested, switching whether to allow the acquisition circuit to acquire the clock signal in place of the data signal or not. The test equipment comprises a test unit for controlling the test circuit so as to allow the acquisition circuit to acquire the clock signal in place of the data signal and executing control for supplying the clock signal to the electronic device and a determination unit for determining, based on the result of allowing the acquisition circuit to acquire the clock signal in place of the data signal, whether the electronic device is good or not.

Description

電子デバイス、試験装置および試験方法Electronic device, test apparatus and test method
　本発明は、データ信号およびこのデータ信号を取得すべきタイミングを示すクロック信号を入力する電子デバイス、このような電子デバイスを試験する試験装置および試験方法に関する。 The present invention relates to an electronic device that inputs a data signal and a clock signal indicating a timing at which the data signal should be acquired, a test apparatus and a test method for testing such an electronic device.
　ソースシンクロナスインターフェースを採用した電子デバイスが知られている。この電子デバイスは、データ信号と並行して、データ信号を取得すべきタイミングを示すクロック信号を入出力する。また、電子デバイスを試験する試験装置が知られている。試験装置は、発生タイミングが固定されたストローブ信号またはタイミング信号を用いて、電子デバイスから出力される信号の取得および電子デバイスに対して与える信号を発生する。 An electronic device that uses a source-synchronous interface is known. This electronic device inputs and outputs a clock signal indicating the timing at which the data signal should be acquired in parallel with the data signal. A test apparatus for testing an electronic device is also known. The test apparatus uses a strobe signal or timing signal with a fixed generation timing to acquire a signal output from the electronic device and generate a signal to be given to the electronic device.
　ところで、ソースシンクロナスインターフェースを採用した電子デバイスは、出力および入力するデータ信号およびクロック信号に、位相ジッタ、位相ドリフトおよびスキューを含む。このような位相ジッタ等は、デバイス間での通常の通信には影響を与えないが、固定のストローブ信号およびタイミング信号を用いる試験装置との通信には影響を与える。従って、試験装置は、このような電子デバイスを試験する場合、データ信号およびクロック信号に含まれる位相ジッタ、位相ドリフトおよびスキューが試験結果に影響しないように、信号の発生および取込においてタイミングマージンを設けていた。 By the way, an electronic device adopting a source synchronous interface includes phase jitter, phase drift, and skew in data signals and clock signals to be output and input. Such phase jitter or the like does not affect normal communication between devices, but affects communication with a test apparatus using fixed strobe signals and timing signals. Therefore, when testing such an electronic device, the test apparatus increases the timing margin in signal generation and capture so that the phase jitter, phase drift and skew included in the data signal and clock signal do not affect the test results. It was provided.
　しかし、近年、ソースシンクロナスインターフェースを採用した電子デバイスのデータ転送速度は、より高速となっている。従って、試験装置は、位相ジッタ、位相ドリフトおよびスキューの影響を考慮したタイミングマージンが減少して、このような電子デバイスを精度良く試験することができなくなってきた。さらに、試験装置は、このような電子デバイスを試験する前に精度の良いキャリブレーションをしなければならなく、試験コストが高くなっていた。 However, in recent years, the data transfer speed of electronic devices adopting a source synchronous interface has become higher. Therefore, the timing margin considering the influence of phase jitter, phase drift, and skew is reduced, and the test apparatus cannot test such an electronic device with high accuracy. Further, the test apparatus has to perform calibration with high accuracy before testing such an electronic device, and the test cost is high.
　そこで本発明の１つの側面においては、上記の課題を解決することのできる電子デバイス、試験装置および試験方法を提供することを目的とする。この目的は請求の範囲における独立項に記載の特徴の組み合わせにより達成される。また従属項は本発明の更なる有利な具体例を規定する。 Therefore, an object of one aspect of the present invention is to provide an electronic device, a test apparatus, and a test method that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.
　上記課題を解決するために、本発明の第１の態様においては、データ信号および前記データ信号を取得すべきタイミングを示すクロック信号を入力する電子デバイスであって、前記データ信号を入力するデータ入力端子と、前記クロック信号を入力するクロック入力端子と、前記クロック信号に応じたタイミングで前記データ信号を取得する取得回路と、当該電子デバイスを試験する場合に、前記データ信号に代えて前記クロック信号を前記取得回路に取得させるか否かを切り替えるテスト用回路と、を備える電子デバイスを提供する。 In order to solve the above problems, in a first aspect of the present invention, an electronic device for inputting a data signal and a clock signal indicating a timing at which the data signal is to be acquired, the data input for inputting the data signal A clock input terminal for inputting the clock signal, an acquisition circuit for acquiring the data signal at a timing according to the clock signal, and the clock signal instead of the data signal when testing the electronic device. An electronic device comprising: a test circuit that switches whether or not the acquisition circuit acquires the signal.
　本発明の第２の態様においては、データ信号および前記データ信号を取得すべきタイミングを示すクロック信号を入力する電子デバイスを試験する試験装置であって、前記電子デバイスは、前記データ信号を入力するデータ入力端子と、前記クロック信号を入力するクロック入力端子と、前記クロック信号に応じたタイミングで前記データ信号を取得する取得回路と、前記電子デバイスを試験する場合に、前記データ信号に代えて前記クロック信号を前記取得回路に取得させるか否かを切り替えるテスト用回路と、を備え、当該試験装置は、前記データ信号に代えて前記クロック信号を前記取得回路に取得させるように前記テスト用回路を制御して、前記電子デバイスに前記クロック信号を供給する制御を実行する試験部と、前記データ信号に代えて前記クロック信号を前記取得回路に取得させた結果に基づいて、当該電子デバイスを良否判定する判定部を備える試験装置を提供する。 According to a second aspect of the present invention, there is provided a test apparatus for testing an electronic device that inputs a data signal and a clock signal indicating a timing at which the data signal is to be acquired, and the electronic device inputs the data signal. A data input terminal; a clock input terminal for inputting the clock signal; an acquisition circuit for acquiring the data signal at a timing according to the clock signal; and when testing the electronic device, the data signal instead of the data signal And a test circuit for switching whether or not the acquisition circuit acquires the clock signal, and the test apparatus includes the test circuit so that the acquisition circuit acquires the clock signal instead of the data signal. A control unit that performs control to supply the clock signal to the electronic device, and the data signal. Based on the result of the acquired said clock signal to said acquisition circuit in place, to provide a test apparatus including a quality determination unit for determining the electronic device.
　本発明の第３の態様においては、データ信号および前記データ信号を取得すべきタイミングを示すクロック信号を入力する電子デバイスを試験する試験方法であって、前記電子デバイスは、前記データ信号を入力するデータ入力端子と、前記クロック信号を入力するクロック入力端子と、前記クロック信号に応じたタイミングで前記データ信号を取得する取得回路と、前記電子デバイスを試験する場合に、前記データ信号に代えて前記クロック信号を前記取得回路に取得させるか否かを切り替えるテスト用回路と、を備え、前記データ信号に代えて前記クロック信号を前記取得回路に取得させるように前記テスト用回路を制御して、前記電子デバイスに前記クロック信号を供給し、前記データ信号に代えて前記クロック信号を前記取得回路に取得させた結果に基づいて、当該電子デバイスを良否判定する試験方法を提供する。 According to a third aspect of the present invention, there is provided a test method for testing an electronic device that inputs a data signal and a clock signal indicating a timing at which the data signal is to be acquired, wherein the electronic device inputs the data signal. A data input terminal; a clock input terminal for inputting the clock signal; an acquisition circuit for acquiring the data signal at a timing according to the clock signal; and when testing the electronic device, the data signal instead of the data signal A test circuit that switches whether or not to cause the acquisition circuit to acquire a clock signal, and controls the test circuit to cause the acquisition circuit to acquire the clock signal instead of the data signal. The clock signal is supplied to an electronic device, and the clock signal is replaced with the data signal instead of the data signal. Based on the result of the acquisition, it provides an acceptability determining test method the electronic device.
　なお、上記の発明の概要は、本発明の必要な特徴の全てを列挙したものではない。また、これらの特徴群のサブコンビネーションもまた、発明となりうる。 Note that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.
図１は、本実施形態に係る電子デバイス１０および試験装置２０を示す。FIG. 1 shows an electronic device 10 and a test apparatus 20 according to this embodiment. 図２は、本実施形態に係る電子デバイス１０および試験装置２０の構成を示す。FIG. 2 shows the configuration of the electronic device 10 and the test apparatus 20 according to the present embodiment. 図３は、データ信号およびクロック信号のタイミングの一例を示す。FIG. 3 shows an example of the timing of the data signal and the clock signal. 図４は、電子デバイス１０が通常動作する場合の、データ信号およびクロック信号の流れを示す。FIG. 4 shows the flow of data signals and clock signals when the electronic device 10 operates normally. 図５は、電子デバイス１０を試験する場合の、試験装置２０の動作フローの一例を示す。FIG. 5 shows an example of an operation flow of the test apparatus 20 when testing the electronic device 10. 図６は、ステップＳ１１の遅延量設定値を検出する場合における信号の流れを示す。FIG. 6 shows a signal flow when the delay amount set value in step S11 is detected. 図７は、ステップＳ１２およびステップＳ１３の電子デバイス１０を試験する場合における信号の流れを示す。FIG. 7 shows a signal flow when the electronic device 10 in step S12 and step S13 is tested. 図８は、本実施形態の変形例に係る電子デバイス１０および試験装置２０の構成を示す。FIG. 8 shows a configuration of the electronic device 10 and the test apparatus 20 according to a modification of the present embodiment.
　以下、発明の実施の形態を通じて本発明を説明するが、以下の実施形態は請求の範囲にかかる発明を限定するものではない。また、実施形態の中で説明されている特徴の組み合わせの全てが発明の解決手段に必須であるとは限らない。 Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.
　図１は、本実施形態に係る電子デバイス１０および試験装置２０を示す。電子デバイス１０は、ソースシンクロナスインターフェースを採用し、データ信号およびデータ信号を取得すべきタイミングを示すクロック信号を入力する。電子デバイス１０は、クロック信号の周期に対して、例えば、２倍、４倍、…の周期のデータ信号を入力する。本実施形態において、電子デバイス１０が入力するデータ信号は、転送レートがクロック信号の２倍であり、エッジ位相がクロック信号の立上エッジおよび立下りエッジのタイミングと一致する。 FIG. 1 shows an electronic device 10 and a test apparatus 20 according to this embodiment. The electronic device 10 employs a source synchronous interface, and inputs a data signal and a clock signal indicating timing to acquire the data signal. The electronic device 10 inputs a data signal having a period of, for example, twice, four times,... With respect to the period of the clock signal. In the present embodiment, the data signal input by the electronic device 10 has a transfer rate that is twice that of the clock signal, and the edge phase coincides with the timing of the rising edge and the falling edge of the clock signal.
 　試験装置２０は、電子デバイス１０を試験する。試験装置２０は、一例として、電子デバイス１０に対して試験信号を与え、試験信号を与えたことに応じて出力される応答信号を受け取る。そして、試験装置２０は、期待された応答信号を受け取れたか否かを判断して電子デバイス１０の良否を判定する。 試 験 The test apparatus 20 tests the electronic device 10. As an example, the test apparatus 20 provides a test signal to the electronic device 10 and receives a response signal output in response to the provision of the test signal. Then, the test apparatus 20 determines whether the electronic device 10 is acceptable by determining whether an expected response signal has been received.
　図２は、本実施形態に係る電子デバイス１０および試験装置２０の構成を示す。本実施形態に係る電子デバイス１０は、データ入力端子３２と、クロック入力端子３４と、取得回路３６と、内部回路３８と、テスト用回路４０とを備える。 FIG. 2 shows the configuration of the electronic device 10 and the test apparatus 20 according to the present embodiment. The electronic device 10 according to the present embodiment includes a data input terminal 32, a clock input terminal 34, an acquisition circuit 36, an internal circuit 38, and a test circuit 40.
　データ入力端子３２は、外部から供給されたデータ信号を入力する。クロック入力端子３４は、外部から供給されたクロック信号を入力する。 The data input terminal 32 inputs a data signal supplied from the outside. The clock input terminal 34 inputs a clock signal supplied from the outside.
　取得回路３６は、クロック入力端子３４が入力したクロック信号に応じたタイミングで、データ入力端子３２が入力したデータ信号を取得する。本実施形態においては、取得回路３６は、９０度位相遅延器４２と、第１ラッチ４４と、第２ラッチ４６と、転送部４８とを有する。９０度位相遅延器４２は、クロック入力端子３４が入力したクロック信号を、９０度の位相分遅延する。 The acquisition circuit 36 acquires the data signal input from the data input terminal 32 at a timing corresponding to the clock signal input from the clock input terminal 34. In the present embodiment, the acquisition circuit 36 includes a 90-degree phase delay device 42, a first latch 44, a second latch 46, and a transfer unit 48. The 90-degree phase delay device 42 delays the clock signal input from the clock input terminal 34 by a phase of 90 degrees.
　第１ラッチ４４は、９０度位相遅延器４２により遅延されたクロック信号の立上りエッジのタイミングにおいて、データ入力端子３２が入力したデータ信号の値を取得する。第２ラッチ４６は、９０度位相遅延器４２により遅延されたクロック信号の立下りエッジのタイミングにおいて、データ入力端子３２が入力したデータ信号の値を取得する。転送部４８は、第１ラッチ４４が取得した値のデータ列および第２ラッチ４６が取得した値のデータ列をバッファリングして、後段の内部回路３８に転送する。 The first latch 44 acquires the value of the data signal input from the data input terminal 32 at the timing of the rising edge of the clock signal delayed by the 90-degree phase delay unit 42. The second latch 46 acquires the value of the data signal input from the data input terminal 32 at the timing of the falling edge of the clock signal delayed by the 90-degree phase delay device 42. The transfer unit 48 buffers the data string of the values acquired by the first latch 44 and the data string of the values acquired by the second latch 46 and transfers them to the internal circuit 38 at the subsequent stage.
　このような取得回路３６は、クロック信号の９０度および２７０度の位相タイミングで、データ信号の値を取得することができる。すなわち、このような取得回路３６は、クロック信号の２倍の転送レートのデータ信号の値を、当該データ信号の中心位相タイミング（位相が１８０度のタイミング）において取得することができる。 Such an acquisition circuit 36 can acquire the value of the data signal at the phase timings of 90 degrees and 270 degrees of the clock signal. That is, such an acquisition circuit 36 can acquire the value of the data signal having a transfer rate twice that of the clock signal at the center phase timing of the data signal (timing of 180 degrees in phase).
　なお、データ信号の転送レートがクロック信号の転送レートの２倍より高い場合には、取得回路３６は、レートの倍数に対応する個数の複数のラッチを有する。そして、取得回路３６は、このような複数のラッチを用いて、クロック信号に応じた複数種類のタイミングのそれぞれでデータ信号をそれぞれ取得する。 When the transfer rate of the data signal is higher than twice the transfer rate of the clock signal, the acquisition circuit 36 has a plurality of latches corresponding to the multiple of the rate. Then, the acquisition circuit 36 acquires the data signal at each of a plurality of types of timings according to the clock signal, using such a plurality of latches.
　内部回路３８は、取得回路３６により取得されたデータ列に応じて動作する。内部回路３８は、一例として、メモリから読み出したデータ列を処理する回路であってよい。 The internal circuit 38 operates in accordance with the data string acquired by the acquisition circuit 36. For example, the internal circuit 38 may be a circuit that processes a data string read from the memory.
　テスト用回路４０は、試験装置２０が当該電子デバイス１０を試験する場合に、データ信号に代えてクロック信号を取得回路３６に取得させるか否かを切り替える。また、テスト用回路４０は、試験装置２０が当該電子デバイス１０を試験する場合に、取得回路３６が取得したデータ信号の値を期待値と比較した結果に基づき、当該電子デバイス１０の良否を判定する。そして、テスト用回路４０は、判定結果を応答信号として試験装置２０に送信する。 The test circuit 40 switches whether the acquisition circuit 36 acquires the clock signal instead of the data signal when the test apparatus 20 tests the electronic device 10. In addition, when the test apparatus 20 tests the electronic device 10, the test circuit 40 determines whether the electronic device 10 is acceptable based on the result of comparing the value of the data signal acquired by the acquisition circuit 36 with an expected value. To do. Then, the test circuit 40 transmits the determination result to the test apparatus 20 as a response signal.
　本実施形態においては、テスト用回路４０は、選択部５２と、可変遅延部５４と、固定遅延部５６と、ループバック切替部５８とを有する。選択部５２は、外部の試験装置２０からの指示に応じて、データ信号およびクロック信号のいずれを取得回路３６に供給して取得させるかを選択する。なお、当該電子デバイス１０が通常動作する状態においては、選択部５２は、データ信号を取得回路３６に取得させる。 In the present embodiment, the test circuit 40 includes a selection unit 52, a variable delay unit 54, a fixed delay unit 56, and a loopback switching unit 58. The selection unit 52 selects which of the data signal and the clock signal is supplied to the acquisition circuit 36 for acquisition in accordance with an instruction from the external test apparatus 20. Note that in a state where the electronic device 10 normally operates, the selection unit 52 causes the acquisition circuit 36 to acquire a data signal.
　可変遅延部５４は、外部の試験装置２０からの指示に応じて、遅延量が可変される。可変遅延部５４は、データ入力端子３２から入力したデータ信号およびクロック入力端子３４から入力したクロック信号の一方を他方に対して遅延させて取得回路３６に供給する。 In the variable delay unit 54, the delay amount is varied in accordance with an instruction from the external test apparatus 20. The variable delay unit 54 delays one of the data signal input from the data input terminal 32 and the clock signal input from the clock input terminal 34 with respect to the other, and supplies the delayed signal to the acquisition circuit 36.
　本実施形態においては、可変遅延部５４は、クロック入力端子３４から入力したクロック信号を遅延して取得回路３６に供給する。これに代えて、可変遅延部５４は、データ入力端子３２から入力したデータ信号を遅延して、選択部５２を介して取得回路３６に供給する構成であってもよい。なお、当該電子デバイス１０が通常動作する状態においては、可変遅延部５４は、与えられた信号を基準遅延量分、遅延する。 In the present embodiment, the variable delay unit 54 delays the clock signal input from the clock input terminal 34 and supplies it to the acquisition circuit 36. Alternatively, the variable delay unit 54 may be configured to delay the data signal input from the data input terminal 32 and supply the delayed data signal to the acquisition circuit 36 via the selection unit 52. Note that in a state where the electronic device 10 normally operates, the variable delay unit 54 delays a given signal by a reference delay amount.
　固定遅延部５６は、データ入力端子３２から入力したデータ信号またはクロック入力端子３４から入力したクロック信号のうちの、可変遅延部５４が遅延する一方の信号に対して、可変遅延部５４が遅延していない他方の信号を遅延させて取得回路３６に供給する。固定遅延部５６は、当該電子デバイス１０が通常動作する状態における可変遅延部５４の遅延量（基準遅延量）分、与えられた信号を遅延する。 In the fixed delay unit 56, the variable delay unit 54 delays one of the data signal input from the data input terminal 32 or the clock signal input from the clock input terminal 34 that is delayed by the variable delay unit 54. The other signal that has not been supplied is delayed and supplied to the acquisition circuit 36. The fixed delay unit 56 delays the given signal by the delay amount (reference delay amount) of the variable delay unit 54 in a state where the electronic device 10 normally operates.
　本実施形態においては、固定遅延部５６は、データ入力端子３２から入力したデータ信号を遅延して取得回路３６に供給する。なお、可変遅延部５４がデータ入力端子３２から入力したデータ信号を遅延する場合には、固定遅延部５６は、クロック入力端子３４から入力したクロック信号を遅延して取得回路３６に供給する。 In the present embodiment, the fixed delay unit 56 delays the data signal input from the data input terminal 32 and supplies the delayed data signal to the acquisition circuit 36. When the variable delay unit 54 delays the data signal input from the data input terminal 32, the fixed delay unit 56 delays the clock signal input from the clock input terminal 34 and supplies it to the acquisition circuit 36.
　ループバック切替部５８は、外部の試験装置２０からの指示に応じて、データ入力端子３２またはクロック入力端子３４の一方が外部から入力した信号を、可変遅延部５４により遅延して他方から外部へと出力させるか否かを切り替える。本実施形態においては、ループバック切替部５８は、可変遅延部５４におけるクロック入力端子３４が接続されていない端子と、データ入力端子３２との間を、接続するか否かを切り替える。 In response to an instruction from the external test apparatus 20, the loopback switching unit 58 delays a signal input from the outside by one of the data input terminal 32 or the clock input terminal 34 by the variable delay unit 54 and outputs the signal from the other to the outside. Switch whether to output. In the present embodiment, the loopback switching unit 58 switches whether or not to connect between the terminal to which the clock input terminal 34 of the variable delay unit 54 is not connected and the data input terminal 32.
　可変遅延部５４がデータ入力端子３２から入力したデータ信号を遅延する場合には、可変遅延部５４におけるデータ入力端子３２が接続されていない端と、クロック入力端子３４との間を、接続するか否かを切り替える。なお、当該電子デバイス１０が通常動作する状態においては、ループバック切替部５８は、データ入力端子３２とクロック入力端子３４との間を開放する。 When the variable delay unit 54 delays the data signal input from the data input terminal 32, is the connection between the end of the variable delay unit 54 to which the data input terminal 32 is not connected and the clock input terminal 34 connected? Switch between no. In the state where the electronic device 10 normally operates, the loopback switching unit 58 opens the space between the data input terminal 32 and the clock input terminal 34.
　デバイス内判定部６０は、試験装置２０が当該電子デバイス１０を試験する場合に、取得回路３６により取得された信号を期待値と比較した結果に基づき良否判定する。そして、デバイス内判定部６０は、判定結果を応答信号として試験装置２０に送信する。 The in-device determination unit 60 determines pass / fail based on the result of comparing the signal acquired by the acquisition circuit 36 with the expected value when the test apparatus 20 tests the electronic device 10. Then, the in-device determination unit 60 transmits the determination result to the test apparatus 20 as a response signal.
　本実施形態に係る試験装置２０は、位相差検出部１０１と、信号発生部１０２と、制御部１０３と、記憶部１０４と、試験部１０５と、キャリブレーション部１０６とを備える。位相差検出部１０１は、電子デバイス１０から受け取った信号の位相または遅延量を測定する。 The test apparatus 20 according to the present embodiment includes a phase difference detection unit 101, a signal generation unit 102, a control unit 103, a storage unit 104, a test unit 105, and a calibration unit 106. The phase difference detection unit 101 measures the phase or delay amount of the signal received from the electronic device 10.
　信号発生部１０２は、電子デバイス１０に対して信号を供給する。制御部１０３は、電子デバイス１０に対する設定等を行う。より具体的には、制御部１０３は、可変遅延部５４に対して設定値を与えて遅延量を変更する。また、制御部１０３は、電子デバイス１０の選択部５２およびループバック切替部５８の切り替えを制御する。記憶部１０４は、キャリブレーション部１０６により検出された遅延量設定値を記憶する。 The signal generator 102 supplies a signal to the electronic device 10. The control unit 103 performs settings for the electronic device 10. More specifically, the control unit 103 gives a setting value to the variable delay unit 54 to change the delay amount. The control unit 103 also controls switching of the selection unit 52 and the loopback switching unit 58 of the electronic device 10. The storage unit 104 stores the delay amount setting value detected by the calibration unit 106.
　試験部１０５は、一例として、ＣＰＵ等の演算処理装置が試験プログラムを実行することにより実現される。試験部１０５は、電子デバイス１０を試験する場合に、データ信号に代えてクロック信号を取得回路３６に取得させるようにテスト用回路４０の選択部５２を制御して、電子デバイス１０にクロック信号を供給する制御を実行する。 The test unit 105 is realized, for example, by an arithmetic processing unit such as a CPU executing a test program. When testing the electronic device 10, the test unit 105 controls the selection unit 52 of the test circuit 40 so that the acquisition circuit 36 acquires the clock signal instead of the data signal, and sends the clock signal to the electronic device 10. The supply control is executed.
　さらに、試験部１０５は、データ信号およびクロック信号を、電子デバイスの通常動作において用いる基準遅延量分ずらす設定値を、可変遅延部５４に設定する制御を実行する。また、他の試験においては、試験部１０５は、データ信号およびクロック信号を、電子デバイス１０の通常動作において用いる基準遅延量に対して予め指定されたオフセット遅延量分ずらす遅延量設定値を、可変遅延部５４に設定する制御を実行する。 Further, the test unit 105 executes control to set a setting value for shifting the data signal and the clock signal by the reference delay amount used in the normal operation of the electronic device in the variable delay unit 54. In other tests, the test unit 105 variably sets a delay amount setting value for shifting the data signal and the clock signal by a predetermined offset delay amount with respect to a reference delay amount used in the normal operation of the electronic device 10. The control set in the delay unit 54 is executed.
　キャリブレーション部１０６は、一例として、ＣＰＵ等の演算処理装置がキャリブレーションプログラムを実行することにより実現される。キャリブレーション部１０６は、データ入力端子３２またはクロック入力端子３４の一方に信号を与えて、可変遅延部５４を介して他方から出力された信号に基づいて、可変遅延部５４の遅延量を、基準遅延量に対してオフセット遅延量分ずらす遅延量設定値を検出する。本実施形態においては、キャリブレーション部１０６は、データ信号の位相をクロック信号の位相よりオフセット遅延量分遅らせる負側の遅延量設定値と、データ信号の位相をクロック信号の位相よりオフセット遅延量分進ませる正側の遅延量設定値とを検出する。 As an example, the calibration unit 106 is realized by an arithmetic processing device such as a CPU executing a calibration program. The calibration unit 106 gives a signal to one of the data input terminal 32 or the clock input terminal 34, and sets the delay amount of the variable delay unit 54 as a reference based on the signal output from the other through the variable delay unit 54. A delay amount setting value that is shifted by an offset delay amount with respect to the delay amount is detected. In the present embodiment, the calibration unit 106 sets a negative delay amount setting value that delays the phase of the data signal by the offset delay amount from the phase of the clock signal, and the phase of the data signal by the offset delay amount from the phase of the clock signal. The positive delay amount set value to be advanced is detected.
　図３は、データ信号およびクロック信号のタイミングの一例を示す。ソースシンクロナスインターフェースを採用したデバイスの試験では、被試験デバイスに与えるデータ信号とクロック信号との位相差を、標準の状態（図３の（Ａ）の状態）として試験をする。 FIG. 3 shows an example of the timing of the data signal and the clock signal. In testing a device employing a source synchronous interface, the phase difference between a data signal and a clock signal applied to the device under test is tested as a standard state (state (A) in FIG. 3).
　さらに、被試験デバイスに与えるデータ信号とクロック信号との位相差を、標準状態から所定位相ずらした状態（図３の（Ｂ），（Ｃ）の状態）として試験をする場合もある。図３の（Ｂ）および（Ｃ）の状態とした試験によれば、与えられるデータ信号とクロック信号との位相差を仕様により定められた上限または下限までずらした条件であっても、被試験デバイスが正しいデータを取得できるか否かを判定することができる。 Further, the test may be performed with the phase difference between the data signal applied to the device under test and the clock signal shifted from the standard state by a predetermined phase (states (B) and (C) in FIG. 3). According to the tests in the states of (B) and (C) of FIG. 3, even if the phase difference between the applied data signal and the clock signal is shifted to the upper limit or the lower limit determined by the specifications, the device under test It can be determined whether the device can acquire correct data.
　ここで、遅延量設定値は、一例として、取得回路３６に取得されるデータ信号とクロック信号との間に、仕様により定められた上限または下限の位相差を与える可変遅延部５４の設定値を表す。従って、本実施形態において、キャリブレーション部１０６は、試験に先立って、このような位相差をデータ信号およびクロック信号の間に生じさせる遅延量設定値を検出する。 Here, the delay amount setting value is, for example, the setting value of the variable delay unit 54 that gives the upper or lower phase difference determined by the specification between the data signal acquired by the acquisition circuit 36 and the clock signal. To express. Therefore, in the present embodiment, the calibration unit 106 detects a delay amount setting value that causes such a phase difference between the data signal and the clock signal prior to the test.
　図４は、電子デバイス１０が通常動作する場合の、データ信号およびクロック信号の流れを示す。当該電子デバイス１０が通常動作する場合、選択部５２は、データ入力端子３２が入力したデータ信号を取得回路３６に供給する。また、可変遅延部５４は、クロック入力端子３４から入力したクロック信号を、基準遅延量分遅延する。また、ループバック切替部５８は、データ入力端子３２とクロック入力端子３４との間を開放する。 FIG. 4 shows the flow of data signals and clock signals when the electronic device 10 normally operates. When the electronic device 10 normally operates, the selection unit 52 supplies the data signal input from the data input terminal 32 to the acquisition circuit 36. The variable delay unit 54 delays the clock signal input from the clock input terminal 34 by a reference delay amount. Further, the loopback switching unit 58 opens between the data input terminal 32 and the clock input terminal 34.
　当該電子デバイス１０が通常動作する場合、テスト用回路４０は、データ入力端子３２から入力したデータ信号を固定遅延部５６が基準遅延量分遅延して取得回路３６に供給し、クロック入力端子３４から入力したクロック信号を可変遅延部５４が基準遅延量分遅延して取得回路３６に供給する。これにより、テスト用回路４０は、データ入力端子３２から入力したデータ信号およびクロック入力端子３４から入力したクロック信号の位相関係をずらすことなく、取得回路３６へ供給することができる。 When the electronic device 10 operates normally, the test circuit 40 supplies the data signal input from the data input terminal 32 to the acquisition circuit 36 after the fixed delay unit 56 delays the data signal by the reference delay amount. The variable delay unit 54 delays the input clock signal by the reference delay amount and supplies it to the acquisition circuit 36. Thus, the test circuit 40 can supply the data to the acquisition circuit 36 without shifting the phase relationship between the data signal input from the data input terminal 32 and the clock signal input from the clock input terminal 34.
　図５は、電子デバイス１０を試験する場合の、試験装置２０の動作フローの一例を示す。試験装置２０は、電子デバイス１０の出荷前等の試験において、以下のステップＳ１１からＳ１３の処理を実行する。 FIG. 5 shows an example of the operation flow of the test apparatus 20 when testing the electronic device 10. The test apparatus 20 performs the following steps S11 to S13 in a test before shipping the electronic device 10 or the like.
　まず、ステップＳ１１において、試験装置２０は、電子デバイス１０の通常動作時において用いる基準遅延量から予め指定されたオフセット遅延量分ずらした遅延量に、可変遅延部５４を設定するための遅延量設定値を検出する。続いて、ステップＳ１２において、試験装置２０は、可変遅延部５４を、電子デバイス１０の通常動作時において用いる遅延量（基準遅延量）として、電子デバイス１０を試験する。 First, in step S11, the test apparatus 20 sets a delay amount for setting the variable delay unit 54 to a delay amount shifted from a reference delay amount used during normal operation of the electronic device 10 by a predetermined offset delay amount. Detect value. Subsequently, in step S <b> 12, the test apparatus 20 tests the electronic device 10 using the variable delay unit 54 as a delay amount (reference delay amount) used during normal operation of the electronic device 10.
　続いて、ステップＳ１３において、試験装置２０は、可変遅延部５４に遅延量設定値を設定した状態で、電子デバイス１０を試験する。即ち、試験装置２０は、可変遅延部５４を、電子デバイス１０の通常動作時において用いる基準遅延量から予め指定されたオフセット遅延量分ずらした遅延量として、電子デバイス１０を試験する。 Subsequently, in step S <b> 13, the test apparatus 20 tests the electronic device 10 with the delay amount setting value set in the variable delay unit 54. In other words, the test apparatus 20 tests the electronic device 10 using the variable delay unit 54 as a delay amount that is shifted from the reference delay amount used during the normal operation of the electronic device 10 by a predetermined offset delay amount.
　図６は、ステップＳ１１の遅延量設定値を検出する場合における信号の流れを示す。ステップＳ１１の遅延量設定値を検出する場合において、まず、キャリブレーション部１０６は、制御部１０３に対して、データ入力端子３２またはクロック入力端子３４の一方が外部から入力した信号を、可変遅延部５４により遅延して他方から外部へと出力させるように指示する。この指示に応じて、制御部１０３は、データ入力端子３２またはクロック入力端子３４の一方が外部から入力した信号を、可変遅延部５４により遅延して他方から外部へと出力させるように、ループバック切替部５８を切り替える。本実施形態においては、キャリブレーション部１０６は、クロック入力端子３４とデータ入力端子３２との間を可変遅延部５４を介して接続させるように、制御部１０３に指示を与える。 FIG. 6 shows a signal flow when the delay amount set value in step S11 is detected. In the case of detecting the delay amount set value in step S11, first, the calibration unit 106 receives a signal input from the outside from either the data input terminal 32 or the clock input terminal 34 to the control unit 103, as a variable delay unit. It is instructed to delay the output by 54 and output from the other side to the outside. In response to this instruction, the control unit 103 loops back so that a signal input from the outside by either the data input terminal 32 or the clock input terminal 34 is delayed by the variable delay unit 54 and output from the other to the outside. The switching unit 58 is switched. In the present embodiment, the calibration unit 106 instructs the control unit 103 to connect the clock input terminal 34 and the data input terminal 32 via the variable delay unit 54.
　このように設定した状態において、キャリブレーション部１０６は、信号発生部１０２に対して、データ入力端子３２またはクロック入力端子３４の一方へ信号を供給する指示を与える。さらに、キャリブレーション部１０６は、位相差検出部１０１に対して、一方の端子へ出力された信号と、他方の端子から出力された信号との位相差を検出する指示を与える。 In the state set in this way, the calibration unit 106 instructs the signal generation unit 102 to supply a signal to one of the data input terminal 32 and the clock input terminal 34. Further, the calibration unit 106 gives an instruction to the phase difference detection unit 101 to detect the phase difference between the signal output to one terminal and the signal output from the other terminal.
　この指示に応じて、信号発生部１０２は、データ入力端子３２またはクロック入力端子３４の一方へ信号を供給する。また、位相差検出部１０１は、可変遅延部５４およびループバック切替部５８を介して他方の端子から出力された信号を取得して、一方の端子へ入力した信号と他方の端子から出力した信号との位相差を検出する。 In response to this instruction, the signal generator 102 supplies a signal to one of the data input terminal 32 and the clock input terminal 34. Also, the phase difference detection unit 101 acquires a signal output from the other terminal via the variable delay unit 54 and the loopback switching unit 58, and a signal input to one terminal and a signal output from the other terminal The phase difference between and is detected.
　そして、キャリブレーション部１０６は、位相差検出部１０１により検出された位相差を受け取る。このようにして、キャリブレーション部１０６は、データ入力端子３２またはクロック入力端子３４の一方へ信号を与えて、可変遅延部５４およびループバック切替部５８を介して他方から出力された信号を取得することにより、一方の端子へ信号を与えたタイミングから他方の端子から信号が出力されたタイミングまでの時間差を測定する。 The calibration unit 106 receives the phase difference detected by the phase difference detection unit 101. In this way, the calibration unit 106 gives a signal to one of the data input terminal 32 or the clock input terminal 34 and acquires a signal output from the other via the variable delay unit 54 and the loopback switching unit 58. Thus, the time difference from the timing when the signal is applied to one terminal to the timing when the signal is output from the other terminal is measured.
　さらに、キャリブレーション部１０６は、このような時間差の測定を複数回実行する。キャリブレーション部１０６は、制御部１０３に対して、それぞれの実行において、可変遅延部５４に与える設定値を順次に変化させる指示を与える。この指示に応じて、制御部１０３は、可変遅延部５４に与える設定値を順次に変化させる。 Further, the calibration unit 106 performs such time difference measurement a plurality of times. The calibration unit 106 gives an instruction to the control unit 103 to sequentially change the setting value to be given to the variable delay unit 54 in each execution. In response to this instruction, the control unit 103 sequentially changes the set value to be given to the variable delay unit 54.
　キャリブレーション部１０６は、それぞれの設定値における時間差の測定結果から、可変遅延部５４の遅延量を、基準遅延量に対してオフセット遅延量分ずらす遅延量設定値を検出する。なお、本実施形態においては、キャリブレーション部１０６は、可変遅延部５４の遅延量を、基準遅延量に対して負側にオフセット遅延量分ずらす負側の遅延量設定値、および、基準遅延量に対して正側にオフセット遅延量分ずらす正側の遅延量設定値を検出する。そして、キャリブレーション部１０６は、このように検出した遅延量設定値を記憶部１０４に記憶させる。 The calibration unit 106 detects a delay amount setting value that shifts the delay amount of the variable delay unit 54 from the reference delay amount by the offset delay amount from the measurement result of the time difference between the respective setting values. In the present embodiment, the calibration unit 106 sets the negative delay amount setting value that shifts the delay amount of the variable delay unit 54 to the negative side by the offset delay amount with respect to the reference delay amount, and the reference delay amount. The positive delay amount set value shifted by the offset delay amount to the positive side is detected. Then, the calibration unit 106 stores the delay amount setting value thus detected in the storage unit 104.
　図７は、ステップＳ１２およびステップＳ１３の電子デバイス１０を試験する場合における信号の流れを示す。ステップＳ１２およびステップＳ１３の試験をする場合において、まず、試験部１０５は、制御部１０３に対して、データ入力端子３２が入力したデータ信号に代えて、クロック入力端子３４が入力したクロック信号を取得回路３６に取得させるように指示する。この指示に応じて、制御部１０３は、クロック入力端子３４が入力したクロック信号を取得回路３６に取得させるように、選択部５２を切り替える。 FIG. 7 shows a signal flow when the electronic device 10 in step S12 and step S13 is tested. When performing the tests in step S12 and step S13, first, the test unit 105 acquires the clock signal input from the clock input terminal 34 instead of the data signal input from the data input terminal 32 to the control unit 103. Instruct the circuit 36 to acquire. In response to this instruction, the control unit 103 switches the selection unit 52 so that the acquisition circuit 36 acquires the clock signal input from the clock input terminal 34.
　さらに、試験部１０５は、ステップＳ１２の試験をする場合には、制御部１０３に対して、可変遅延部５４の遅延量を、基準遅延量とするように指示する。この指示に応じて、制御部１０３は、可変遅延部５４に対して、電子デバイス１０が通常動作する場合における設定値を与える。 Furthermore, when performing the test in step S12, the test unit 105 instructs the control unit 103 to set the delay amount of the variable delay unit 54 as the reference delay amount. In response to this instruction, the control unit 103 gives a setting value to the variable delay unit 54 when the electronic device 10 normally operates.
　また、試験部１０５は、ステップＳ１３の試験をする場合には、制御部１０３に対して、可変遅延部５４の遅延量を、基準遅延量からオフセット遅延量分ずれた遅延量とするように指示する。この指示に応じて、制御部１０３は、記憶部１０４から遅延量設定値を読み出し、可変遅延部５４に対して、読み出した遅延量設定値を設定する。なお、本実施形態においては、ステップＳ１３において、可変遅延部５４に負側の遅延量設定値を設定した状態および可変遅延部５４に正側の遅延量設定値を設定した状態のそれぞれで、電子デバイス１０を試験する。 Further, when performing the test of step S13, the test unit 105 instructs the control unit 103 to set the delay amount of the variable delay unit 54 to a delay amount that is offset from the reference delay amount by the offset delay amount. To do. In response to this instruction, the control unit 103 reads the delay amount setting value from the storage unit 104 and sets the read delay amount setting value in the variable delay unit 54. In the present embodiment, in step S13, each of the state in which the negative delay amount set value is set in the variable delay unit 54 and the state in which the positive delay amount set value is set in the variable delay unit 54 Device 10 is tested.
　このように設定した状態において、試験部１０５は、データ信号に代えてクロック信号を取得回路３６に取得させた結果に基づいて、当該電子デバイス１０を良否判定する。本実施形態においては、試験部１０５は、信号発生部１０２に対して、クロック信号を発生させる指示を与える。さらに、試験部１０５は、電子デバイス１０に対して、与えられた信号を取得して判定する指示を与える。 In the state set in this way, the test unit 105 determines whether the electronic device 10 is good or bad based on the result of causing the acquisition circuit 36 to acquire the clock signal instead of the data signal. In the present embodiment, the test unit 105 gives an instruction to generate a clock signal to the signal generation unit 102. Further, the test unit 105 gives an instruction to the electronic device 10 for obtaining and determining a given signal.
　この指示に応じて、信号発生部１０２は、クロック信号をクロック入力端子３４に与える。クロック入力端子３４にクロック信号が与えられると、取得回路３６は、可変遅延部５４により遅延されたクロック信号のタイミングに基づいて、データ信号に代えて与えられたクロック信号の値を取得する。 In response to this instruction, the signal generator 102 gives a clock signal to the clock input terminal 34. When the clock signal is supplied to the clock input terminal 34, the acquisition circuit 36 acquires the value of the clock signal supplied instead of the data signal based on the timing of the clock signal delayed by the variable delay unit 54.
　さらに、デバイス内判定部６０は、取得回路３６により取得された値を期待値と比較し、比較結果を試験部１０５に送信する。そして、試験部１０５は、取得された値が期待値と一致する場合には当該電子デバイス１０が良品と判断し、取得された値が期待値と一致しない場合には当該電子デバイス１０が不良品と判断する。 Furthermore, the in-device determination unit 60 compares the value acquired by the acquisition circuit 36 with the expected value, and transmits the comparison result to the test unit 105. Then, the test unit 105 determines that the electronic device 10 is a non-defective product when the acquired value matches the expected value, and the electronic device 10 is a defective product when the acquired value does not match the expected value. Judge.
　以上のように本実施形態に係る電子デバイス１０は、試験時において、内部のテスト用回路４０がデータ信号に代えてクロック信号を取得回路３６に取得させる。従って、試験装置２０は、試験時において、電子デバイス１０へクロック信号のみを供給すればよい。これにより、電子デバイス１０および試験装置２０によれば、データ信号とクロック信号との間に含まれる位相ジッタ、位相ドリフトおよびスキューを非常に小さくして、精度良く当該電子デバイス１０を試験することができる。 As described above, in the electronic device 10 according to the present embodiment, during the test, the internal test circuit 40 causes the acquisition circuit 36 to acquire the clock signal instead of the data signal. Therefore, the test apparatus 20 need only supply a clock signal to the electronic device 10 during the test. Thereby, according to the electronic device 10 and the test apparatus 20, the phase jitter, the phase drift, and the skew included between the data signal and the clock signal can be extremely reduced, and the electronic device 10 can be accurately tested. it can.
　また、電子デバイス１０は、試験時において、可変遅延部５４を介してデータ入力端子３２とクロック入力端子３４との間を接続するループバック切替部５８を備える。従って、電子デバイス１０および試験装置２０によれば、データ信号とクロック信号との位相を所定のオフセット遅延量ずらした状態において試験する場合において、遅延量を、精度良く、低いコストでキャリブレーションすることができる。 In addition, the electronic device 10 includes a loopback switching unit 58 that connects the data input terminal 32 and the clock input terminal 34 via the variable delay unit 54 during the test. Therefore, according to the electronic device 10 and the test apparatus 20, when testing in a state in which the phase of the data signal and the clock signal is shifted by a predetermined offset delay amount, the delay amount can be accurately calibrated at a low cost. Can do.
　図８は、本実施形態の変形例に係る電子デバイス１０および試験装置２０の構成を示す。本変形例に係る電子デバイス１０および試験装置２０は、図２に示した同一符号の部材と略同一の構成および機能を採るので、以下相違点を除き説明を省略する。 FIG. 8 shows the configuration of the electronic device 10 and the test apparatus 20 according to a modification of the present embodiment. Since the electronic device 10 and the test apparatus 20 according to the present modification have substantially the same configuration and function as the members having the same reference numerals shown in FIG. 2, the description thereof will be omitted except for the following differences.
　本変形例に係るテスト用回路４０は、デバイス内判定部６０を有さずに、取得回路３６により取得された信号を、応答信号として試験装置２０へ転送する。本変形例に係る試験装置２０は、判定部１０７を更に備える。判定部１０７は、テスト用回路４０から応答信号を受け取り、データ信号に代えてクロック信号を取得回路３６に取得させた結果に基づいて、電子デバイス１０を良否判定する。このような変形例に係る電子デバイス１０および試験装置２０は、電子デバイス１０のテスト用回路４０の構成を小さくすることができる。 The test circuit 40 according to the present modification does not have the in-device determination unit 60 and transfers the signal acquired by the acquisition circuit 36 to the test apparatus 20 as a response signal. The test apparatus 20 according to this modification further includes a determination unit 107. The determination unit 107 receives the response signal from the test circuit 40 and determines whether the electronic device 10 is good or bad based on the result obtained by causing the acquisition circuit 36 to acquire the clock signal instead of the data signal. The electronic device 10 and the test apparatus 20 according to such a modification can reduce the configuration of the test circuit 40 of the electronic device 10.
　以上、本発明を実施の形態を用いて説明したが、本発明の技術的範囲は上記実施の形態に記載の範囲には限定されない。上記実施の形態に、多様な変更または改良を加えることが可能であることが当業者に明らかである。その様な変更または改良を加えた形態も本発明の技術的範囲に含まれ得ることが、請求の範囲の記載から明らかである。 As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.
　請求の範囲、明細書、および図面中において示した装置、システム、プログラム、および方法における動作、手順、ステップ、および段階等の各処理の実行順序は、特段「より前に」、「先立って」等と明示しておらず、また、前の処理の出力を後の処理で用いるのでない限り、任意の順序で実現しうることに留意すべきである。請求の範囲、明細書、および図面中の動作フローに関して、便宜上「まず、」、「次に、」等を用いて説明したとしても、この順で実施することが必須であることを意味するものではない。 The execution order of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior”. It should be noted that they can be implemented in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for the sake of convenience, it means that it is essential to carry out in this order. is not.

Claims (10)

  1. 　データ信号および前記データ信号を取得すべきタイミングを示すクロック信号を入力する電子デバイスであって、
    　前記データ信号を入力するデータ入力端子と、
    　前記クロック信号を入力するクロック入力端子と、
    　前記クロック信号に応じたタイミングで前記データ信号を取得する取得回路と、
    　当該電子デバイスを試験する場合に、前記データ信号に代えて前記クロック信号を前記取得回路に取得させるか否かを切り替えるテスト用回路と、
    　を備える電子デバイス。     An electronic device for inputting a data signal and a clock signal indicating a timing to acquire the data signal,
    A data input terminal for inputting the data signal;
    A clock input terminal for inputting the clock signal;
    An acquisition circuit for acquiring the data signal at a timing according to the clock signal;
    When testing the electronic device, a test circuit that switches whether the acquisition circuit acquires the clock signal instead of the data signal;
    An electronic device comprising:
  2. 　前記テスト用回路は、外部の装置からの指示に応じて、前記データ信号および前記クロック信号のいずれを前記取得回路に供給して取得させるかを選択する選択部を有する請求項１に記載の電子デバイス。 The electronic circuit according to claim 1, wherein the test circuit includes a selection unit that selects which of the data signal and the clock signal is supplied to the acquisition circuit to be acquired in accordance with an instruction from an external device. device.
  3. 　前記テスト用回路は、前記データ入力端子から入力した前記データ信号および前記クロック入力端子から入力したクロック信号の一方を他方に対して遅延させて前記取得回路に供給する、遅延量が可変の可変遅延部を更に有する請求項２に記載の電子デバイス。 The test circuit delays one of the data signal input from the data input terminal and the clock signal input from the clock input terminal with respect to the other and supplies it to the acquisition circuit. The electronic device according to claim 2, further comprising a portion.
  4. 　前記テスト用回路は、前記データ入力端子または前記クロック入力端子の一方が外部から入力した信号を、前記可変遅延部により遅延して他方から外部へと出力させるか否かを切り替えるループバック切替部を更に有する請求項３に記載の電子デバイス。 The test circuit includes a loopback switching unit that switches whether a signal input from the outside of the data input terminal or the clock input terminal is delayed by the variable delay unit and output from the other to the outside. The electronic device according to claim 3, further comprising:
  5. 　前記テスト用回路は、前記取得回路により取得された信号を期待値と比較した結果に基づき良否判定するデバイス内判定部を更に有する請求項１から４のいずれかに記載の電子デバイス。 The electronic device according to any one of claims 1 to 4, wherein the test circuit further includes an in-device determination unit that determines pass / fail based on a result obtained by comparing the signal acquired by the acquisition circuit with an expected value.
  6. 　データ信号および前記データ信号を取得すべきタイミングを示すクロック信号を入力する電子デバイスを試験する試験装置であって、
    　前記電子デバイスは、
    　前記データ信号を入力するデータ入力端子と、
    　前記クロック信号を入力するクロック入力端子と、
    　前記クロック信号に応じたタイミングで前記データ信号を取得する取得回路と、
    　前記電子デバイスを試験する場合に、前記データ信号に代えて前記クロック信号を前記取得回路に取得させるか否かを切り替えるテスト用回路と、
    　を備え、
    　当該試験装置は、
    　前記データ信号に代えて前記クロック信号を前記取得回路に取得させるように前記テスト用回路を制御して、前記電子デバイスに前記クロック信号を供給する制御を実行する試験部と、
    　前記データ信号に代えて前記クロック信号を前記取得回路に取得させた結果に基づいて、当該電子デバイスを良否判定する判定部を備える
    　試験装置。     A test apparatus for testing an electronic device that inputs a data signal and a clock signal indicating a timing at which the data signal should be acquired,
    The electronic device is
    A data input terminal for inputting the data signal;
    A clock input terminal for inputting the clock signal;
    An acquisition circuit for acquiring the data signal at a timing according to the clock signal;
    When testing the electronic device, a test circuit that switches whether the acquisition circuit acquires the clock signal instead of the data signal;
    With
    The test equipment
    A test unit that controls the test circuit to cause the acquisition circuit to acquire the clock signal instead of the data signal, and executes control to supply the clock signal to the electronic device;
    A test apparatus comprising: a determination unit that determines whether the electronic device is good or bad based on a result obtained by causing the acquisition circuit to acquire the clock signal instead of the data signal.
  7. 　前記テスト用回路は、
    　当該試験装置からの指示に応じて、前記データ信号および前記クロック信号のいずれを前記取得回路に供給して取得させるかを選択する選択部と、
    　前記データ入力端子から入力した前記データ信号および前記クロック入力端子から入力したクロック信号の一方を他方に対して遅延させて前記取得回路に供給する、遅延量が可変の可変遅延部と、
    　を有し、
    　前記試験部は、前記データ信号および前記クロック信号を、前記電子デバイスの通常動作において用いる基準遅延量に対して予め指定されたオフセット遅延量分ずらす遅延量設定値を、前記可変遅延部に設定し、
    　前記判定部は、前記可変遅延部に前記遅延量設定値を設定した状態において、前記取得回路が前記クロック信号を取得した結果に基づいて、前記電子デバイスを良否判定する
    　請求項６に記載の試験装置。     The test circuit includes:
    In accordance with an instruction from the test apparatus, a selection unit that selects which of the data signal and the clock signal is supplied to the acquisition circuit for acquisition,
    A variable delay unit having a variable delay amount, delaying one of the data signal input from the data input terminal and the clock signal input from the clock input terminal and supplying the delayed signal to the acquisition circuit;
    Have
    The test unit sets, in the variable delay unit, a delay amount setting value for shifting the data signal and the clock signal by a predetermined offset delay amount with respect to a reference delay amount used in a normal operation of the electronic device. ,
    The test according to claim 6, wherein the determination unit determines whether the electronic device is acceptable based on a result of the acquisition circuit acquiring the clock signal in a state where the delay amount setting value is set in the variable delay unit. apparatus.
  8. 　前記テスト用回路は、前記データ入力端子または前記クロック入力端子の一方が外部から入力した信号を、前記可変遅延部により遅延して他方から外部へと出力させるか否かを切り替えるループバック切替部を更に有し、
    　当該試験装置は、前記データ入力端子または前記クロック入力端子の一方に信号を与えて、前記可変遅延部を介して他方から出力された信号に基づいて、前記可変遅延部の遅延量を、前記基準遅延量に対して前記オフセット遅延量分ずらす前記遅延量設定値を検出するキャリブレーション部を更に備える
    　請求項７に記載の試験装置。     The test circuit includes a loopback switching unit that switches whether a signal input from the outside of the data input terminal or the clock input terminal is delayed by the variable delay unit and output from the other to the outside. In addition,
    The test apparatus provides a signal to one of the data input terminal or the clock input terminal, and determines the delay amount of the variable delay unit based on a signal output from the other via the variable delay unit, as the reference The test apparatus according to claim 7, further comprising a calibration unit configured to detect the delay amount setting value that is shifted by the offset delay amount with respect to the delay amount.
  9. 　前記テスト用回路は、前記取得回路により取得された信号を期待値と比較した結果に基づき良否判定するデバイス内判定部を更に有し、
    　前記判定部は、前記デバイス内判定部から判定結果を取得して、当該判定結果に基づいて前記電子デバイスを良否判定する
    　請求項６から８のいずれかに記載の試験装置。     The test circuit further includes an in-device determination unit that determines pass / fail based on a result of comparing the signal acquired by the acquisition circuit with an expected value,
    The test apparatus according to claim 6, wherein the determination unit acquires a determination result from the in-device determination unit, and determines whether the electronic device is good based on the determination result.
  10. 　データ信号および前記データ信号を取得すべきタイミングを示すクロック信号を入力する電子デバイスを試験する試験方法であって、
    　前記電子デバイスは、
    　前記データ信号を入力するデータ入力端子と、
    　前記クロック信号を入力するクロック入力端子と、
    　前記クロック信号に応じたタイミングで前記データ信号を取得する取得回路と、
    　前記電子デバイスを試験する場合に、前記データ信号に代えて前記クロック信号を前記取得回路に取得させるか否かを切り替えるテスト用回路と、
    　を備え、
    　前記データ信号に代えて前記クロック信号を前記取得回路に取得させるように前記テスト用回路を制御して、前記電子デバイスに前記クロック信号を供給し、
    　前記データ信号に代えて前記クロック信号を前記取得回路に取得させた結果に基づいて、当該電子デバイスを良否判定する
    　試験方法。     A test method for testing an electronic device that inputs a data signal and a clock signal indicating a timing at which the data signal is to be obtained,
    The electronic device is
    A data input terminal for inputting the data signal;
    A clock input terminal for inputting the clock signal;
    An acquisition circuit for acquiring the data signal at a timing according to the clock signal;
    When testing the electronic device, a test circuit that switches whether the acquisition circuit acquires the clock signal instead of the data signal;
    With
    Controlling the test circuit to cause the acquisition circuit to acquire the clock signal instead of the data signal, and supplying the clock signal to the electronic device;
    A test method for determining whether or not the electronic device is acceptable based on a result obtained by causing the acquisition circuit to acquire the clock signal instead of the data signal.
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