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WO2009127848A3 - Clock distribution buffer - Google Patents

Clock distribution buffer Download PDF

Info

Publication number
WO2009127848A3
WO2009127848A3 PCT/GB2009/050279 GB2009050279W WO2009127848A3 WO 2009127848 A3 WO2009127848 A3 WO 2009127848A3 GB 2009050279 W GB2009050279 W GB 2009050279W WO 2009127848 A3 WO2009127848 A3 WO 2009127848A3
Authority
WO
WIPO (PCT)
Prior art keywords
buffer
clock distribution
power consumption
current source
local oscillator
Prior art date
Application number
PCT/GB2009/050279
Other languages
French (fr)
Other versions
WO2009127848A2 (en
Inventor
David Wilson
Original Assignee
Elonics Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elonics Limited filed Critical Elonics Limited
Priority to EP09732693A priority Critical patent/EP2277267A2/en
Publication of WO2009127848A2 publication Critical patent/WO2009127848A2/en
Publication of WO2009127848A3 publication Critical patent/WO2009127848A3/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/35613—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration
    • H03K3/356139—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration with synchronous operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0005—Modifications of input or output impedance
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018557—Coupling arrangements; Impedance matching circuits
    • H03K19/018564—Coupling arrangements; Impedance matching circuits with at least one differential stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
  • Superheterodyne Receivers (AREA)
  • Amplifiers (AREA)

Abstract

A clock distribution buffer, and a local oscillator circuit comprising a clock pulse generator and one or more such buffers, that provides efficient power consumption across a wide range of operational frequencies of a local oscillator. The buffer comprises a resistive load and a bias current source, one or both being controllable to vary the slew rate of the buffer. The controllable nature of the resistive load and bias current source enables the slew rate of the buffer to be tailored to the operational frequency desired so as to reduce unnecessary power consumption.
PCT/GB2009/050279 2008-04-18 2009-03-25 Clock distribution buffer WO2009127848A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP09732693A EP2277267A2 (en) 2008-04-18 2009-03-25 Clock distribution buffer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0807148.2 2008-04-18
GB0807148A GB0807148D0 (en) 2008-04-18 2008-04-18 Clock distribution buffer

Publications (2)

Publication Number Publication Date
WO2009127848A2 WO2009127848A2 (en) 2009-10-22
WO2009127848A3 true WO2009127848A3 (en) 2009-12-23

Family

ID=39472384

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2009/050279 WO2009127848A2 (en) 2008-04-18 2009-03-25 Clock distribution buffer

Country Status (3)

Country Link
EP (1) EP2277267A2 (en)
GB (1) GB0807148D0 (en)
WO (1) WO2009127848A2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110292855A1 (en) * 2010-05-28 2011-12-01 Qualcomm Incorporated Dynamic clock buffer power optimization based on modes of operation
US9058130B2 (en) 2013-02-05 2015-06-16 International Business Machines Corporation Tunable sector buffer for wide bandwidth resonant global clock distribution
US9054682B2 (en) 2013-02-05 2015-06-09 International Business Machines Corporation Wide bandwidth resonant global clock distribution
US8704576B1 (en) 2013-02-05 2014-04-22 International Business Machines Corporation Variable resistance switch for wide bandwidth resonant global clock distribution
CN103399808B (en) * 2013-06-06 2016-05-04 北京航天自动控制研究所 A kind of method that realizes the two redundancies of crystal oscillator in flight control computer
US9847776B2 (en) 2014-07-14 2017-12-19 Finisar Corporation Multi-rate clock buffer
KR102641515B1 (en) * 2016-09-19 2024-02-28 삼성전자주식회사 Memory device and clock distribution method thereof
CN108089487B (en) * 2017-11-03 2020-07-24 成都赛英科技有限公司 Adjustable video pulse signal source

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997026710A1 (en) * 1996-01-19 1997-07-24 Motorola Inc. Method and apparatus for selecting from multiple mixers
US6218858B1 (en) * 1999-01-27 2001-04-17 Xilinx, Inc. Programmable input/output circuit for FPGA for use in TTL, GTL, GTLP, LVPECL and LVDS circuits
US20040041605A1 (en) * 2002-09-03 2004-03-04 Kizer Jade M. Locked loop circuit with clock hold function
US20040246026A1 (en) * 2003-06-06 2004-12-09 Microsoft Corporation Method and apparatus for multi-mode driver
US20050212553A1 (en) * 2002-02-19 2005-09-29 Rambus Inc. Method and apparatus for selectably providing single-ended and differential signaling with controllable impedence and transition time
US20070188207A1 (en) * 2005-09-30 2007-08-16 Alan Fiedler Output driver with slew rate control
US20070279083A1 (en) * 2006-04-13 2007-12-06 Stmicroelectronics S.A. Buffer circuit with output signal slope control means

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997026710A1 (en) * 1996-01-19 1997-07-24 Motorola Inc. Method and apparatus for selecting from multiple mixers
US6218858B1 (en) * 1999-01-27 2001-04-17 Xilinx, Inc. Programmable input/output circuit for FPGA for use in TTL, GTL, GTLP, LVPECL and LVDS circuits
US20050212553A1 (en) * 2002-02-19 2005-09-29 Rambus Inc. Method and apparatus for selectably providing single-ended and differential signaling with controllable impedence and transition time
US20040041605A1 (en) * 2002-09-03 2004-03-04 Kizer Jade M. Locked loop circuit with clock hold function
US20040246026A1 (en) * 2003-06-06 2004-12-09 Microsoft Corporation Method and apparatus for multi-mode driver
US20070188207A1 (en) * 2005-09-30 2007-08-16 Alan Fiedler Output driver with slew rate control
US20070279083A1 (en) * 2006-04-13 2007-12-06 Stmicroelectronics S.A. Buffer circuit with output signal slope control means

Also Published As

Publication number Publication date
EP2277267A2 (en) 2011-01-26
GB0807148D0 (en) 2008-05-21
WO2009127848A2 (en) 2009-10-22

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