+

WO2009101565A1 - Topologie optimisée pour bobine d'inductance à faible champ magnétique parasite - Google Patents

Topologie optimisée pour bobine d'inductance à faible champ magnétique parasite Download PDF

Info

Publication number
WO2009101565A1
WO2009101565A1 PCT/IB2009/050508 IB2009050508W WO2009101565A1 WO 2009101565 A1 WO2009101565 A1 WO 2009101565A1 IB 2009050508 W IB2009050508 W IB 2009050508W WO 2009101565 A1 WO2009101565 A1 WO 2009101565A1
Authority
WO
WIPO (PCT)
Prior art keywords
inductor
shaped
crossing
clover
turns
Prior art date
Application number
PCT/IB2009/050508
Other languages
English (en)
Inventor
Alexé Levan NAZARIAN
Lukas Frederik Tiemeijer
Original Assignee
Nxp B.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp B.V. filed Critical Nxp B.V.
Publication of WO2009101565A1 publication Critical patent/WO2009101565A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F5/00—Coils
    • H01F5/003—Printed circuit coils
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type
    • H01F17/0006—Printed inductances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/34—Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
    • H01F27/346—Preventing or reducing leakage fields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type
    • H01F17/0006—Printed inductances
    • H01F2017/0073—Printed inductances with a special conductive pattern, e.g. flat spiral
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Each crossing point increases resistance of inductor and capacitance between windings. Therefore, by keeping the number of crossings points at a minimum, the quality factor of an inductor increases as a consequence thereof.
  • the present inventions relates to 8-shaped and clover-shaped inductors layouts, wherein the amount of crossing points is minimized.
  • Many 8-shaped and clover-shaped have been described in the prior art. These have, however, typically been directed to reducing magnetic field effects thereof. Therein, symmetry is of relevance.
  • WO2006/105184 Al describes a method and apparatus for use in an integrated circuit or printed circuit board for reducing or minimizing interference.
  • An inductance is formed using two or more inductors coupled together and configured such that current flows through the inductors in different directions, thus at least partially canceling magnetic fields.
  • the configuration of the inductors, as well as the relative positions of portions of the circuit can be tweaked to provide optimal interference or noise control.
  • WO0057437 Al describes a balanced inductor formed on lossy substrate material having adjacent strips leading current in opposite directions and being arranged in such a way that substrate currents relating to individual strips induced in the lossy substrate are balancing out one another leading to high Q-values.
  • the inductor structure according to the invention can be implemented in MMIC devices using standard semiconductor substrates and do not require any special treatment of the substrate being needed.
  • Lossy substrate means that it is made from neither dielectric material nor ideal conductor. In other words, it conducts current but has not negligible resistance.
  • WO2005/096328 Al describes a method and system for reducing mutual EM coupling between VCO resonators and for implementing the same on a single semiconductor chip.
  • the method and system involve using inductors that are substantially symmetrical about their horizontal and/or their vertical axes and providing current to the inductors in a way so that the resulting magnetic field components tend to cancel each other by virtue of the symmetry.
  • two such inductors may be placed near each other and oriented in a way so that the induced current in the second inductor due to the magnetic field originating from first inductor is significantly reduced.
  • the inductors may be of various forms.
  • WO2007/006867 Al describes the inductance of a monolithic planar inductor, which is distributed into smaller inductor portions.
  • the smaller inductor portions are provided in a cascade configuration in a manner that causes the inductor to function as a differential inductor device.
  • the node (CM) between the immediate inductor portions (L21, L22 is a common-mode point of the inductor device, which is typically connected to the signal ground.
  • Some of the inductor portions are arranged to be symmetrically by-passed or shortcut in relation to the common point in one or more steps for operation in one or more higher radio frequency band.
  • US2005/017836 Al describes an on-chip inductor including a main inductor portion configured to provide a main magnetic field of an on-chip inductor.
  • An interconnect inductor portion is electrically coupled to the main inductor portion and is configured to provide an interconnect magnetic field that constructively combines with the main magnetic field.
  • US2004/018823 Al describes an on-chip differential inductor includes a first interwound winding having a substantially octagonal shape, or rectangular octagonal shape, and a second interwound winding having a substantially octagonal shape, or rectangular octagonal shape, that is interwound with the first interwound winding. Both the first and second interwound windings are on the same layer of the integrated circuit.
  • Each interwound winding includes two nodes; one of node of each winding is commonly coupled to a reference potential. The other node of each winding is operably coupled to receive a respective leg of a differential signal.
  • US2005/077992 Al describes a substantially symmetric inductor comprising a plurality of windings, at least one conductor crossover, and a peripheral conductor disposed at the periphery of the plurality of windings, the plurality of windings having a generally symmetric shape, each of the plurality of windings having a center and being of a different size from other ones of the plurality of windings, the peripheral conductor being generally symmetric and having a center, the plurality of windings and the peripheral conductor being substantially concentric, the conductor crossovers being disposed such that the symmetry of the inductor in substantially preserved.
  • a method of winding an inductor such that the inductor is substantially symmetric about a center of the inductor, whereby signal degradation due to asymmetry of the inductor is substantially minimized.
  • US2005/024178 Al describes a switchable inductance that can be formed in an integrated circuit, including a spiral interrupted between two first points connected to two terminals via two metallizations running one above the other, one of the two metallizations being deformable; a hollowing between the two metallizations; and a switching device capable of deforming the deformable metallization to separate or to put in contact said two metallizations.
  • substantially symmetrical inductors with eight or clover shaped structures, are known in the art, as can be seen in WO 2006/105184 Al, WO 00/57437 Al, WO 2005/096328 Al and possibly the Minerva document.
  • influence of the crossing points is also known to be an area of interest in obtaining desired performance in such inductor arrangements (see disclosures in US 2005/0017836 Al, for example).
  • the number of crossing points may be proportional to the number of turns.
  • US 2005/0017836 Al scribes a possible design of a crossing of two turns of an inductor. These types of crossings make it possible for turns to have positive mutual inductance at the cost of increased resistance.
  • race track or 8-shaped symmetrical inductors with multiple turns to have crossing points which are proportional to the number of turns, however, typically quadratic proportional.
  • crossing points which are proportional to the number of turns, however, typically quadratic proportional.
  • IC inductors are essential to realize the voltage-controlled oscillators needed in many fully integrated transceiver chips serving a multitude of wireless communication protocols. These are being provided to the market today.
  • WO1998005048(Al), WO2004012213(Al), WO2005096328(Al) and WO2006105184(Al) conductors are described that indeed have a lower magnetic coupling.
  • the price that must be paid is a smaller quality factor of such an inductor.
  • Such a crossing point can be identified as a geometrical point, situated in a 2- D plane parallel to the main plane of an inductor, where one conducting track of an inductor crosses another line of the inductor, wherein at the crossing point the two conducting tracks are not in the same plane.
  • conducting tracks are running in 2 parallel planes, whereas at the crossing point each track is using only one plane, so no shortcut is created (see e.g. figures 2-4).
  • each conducting track is terminated on one plane and an electrical current flows using the other plane.
  • An inductor at low frequency could be represented by equivalent network
  • each crossing point gives an additional contribution to the resistance of an inductor.
  • each turn should preferably use only one layer. This leads to a dramatic increase of sheet resistance for the parts of an inductor where such crossing is implemented. As a result total resistance of inductor increases.
  • Each crossing point contributes also to the capacitance between windings or coils due to potential difference between different layers of the crossing point.
  • 8-shaped and clover-shaped prior art inductors suffer from one or more of the above mentioned drawbacks.
  • symmetric inductors in case of prior art 8-shaped and clover- shaped layout are given in figure 2.
  • the number of crossing points for 8-shaped and clover- shaped inductors are n 2 + n — ⁇ and 2n 2 + n — ⁇ , respectively.
  • n is the number of turns of a coil, e.g. for an 8-shaped inductor, per definition having two coils per 8, and having n coils per layer.
  • the number of crossing points increases quadratic with the number of turns per coil.
  • the present invention relates to a symmetrical inductor, preferably an 8- shaped or clover-shaped inductor, comprising two or four inductor eyes, respectively, each eye comprising 2 or more turns per coil, comprising a geometrical crossing line situated in a 2-D plane parallel to the main plane of the inductor, at which line a conducting track of the inductor crosses maximal one another conducting track of the inductor, wherein at the crossing point the two conducting tracks are not in the same plane, and devices comprising said inductor.
  • a symmetrical inductor preferably an 8- shaped or clover-shaped inductor, comprising two or four inductor eyes, respectively, each eye comprising 2 or more turns per coil, comprising a geometrical crossing line situated in a 2-D plane parallel to the main plane of the inductor, at which line a conducting track of the inductor crosses maximal one another conducting track of the inductor, wherein at the crossing point the two conducting tracks are not in the same plane, and devices comprising said inductor
  • the invention in a first embodiment relates to a symmetrical inductor, preferably an 8-shaped or clover-shaped inductor, comprising two or four inductor eyes, respectively, each eye comprising 2 or more turns per coil, comprising a geometrical crossing line situated in a 2-D plane parallel to the main plane of the inductor, at which line a conducting track of the inductor crosses maximal one another conducting track of the inductor, wherein at the crossing point the two conducting tracks are not in the same plane.
  • a symmetrical inductor preferably an 8-shaped or clover-shaped inductor, comprising two or four inductor eyes, respectively, each eye comprising 2 or more turns per coil, comprising a geometrical crossing line situated in a 2-D plane parallel to the main plane of the inductor, at which line a conducting track of the inductor crosses maximal one another conducting track of the inductor, wherein at the crossing point the two conducting tracks are not in the same plane.
  • an inductor may comprise two or four inductor eyes, for 8-shaped or clover-shaped inductors, respectively.
  • Each eye forms a coil, typically comprising 2 or more turns per coil, preferably 3 or more, more preferably 4 or more, such as 5 or more turns per coil.
  • the aim of the invention is to reduce the number of crossing points, as described above.
  • crossing point As two conducting tracks cross each other, the crossing point comprises more than one layer, in order to prevent the two tracks to be in electrical contact.
  • Typical configurations of crossing points are indicated in figures 2-4, respectively.
  • a geometrical crossing line is indicated, which is running vertically. It is situated in a 2-D plane parallel to the main plane of the inductor. Typically this geometrical crossing line lies in a mirror plane of the inductor.
  • the line itself is virtual, and merely serves the purpose of identifying various components of the present inductor, specifically crossing points.
  • the blue line in figures 2-4 and the geometrical crossing line are situated above one and another. However, the blue line is not a "virtual" line at all.
  • It is a center tap - metal strip that lies a number of metal layers under the metal layers where inductor itself is implemented. One end of the strip is connected (using vias) to the center of the inductor. In the figures 2-4 it is the upper end of the center tap that is connected to the inductor. In common mode potential difference on one side is applied to the signal pads of the inductor and on the other side second end of the center tap.
  • the width of the tracks forming the coils is from 0.5-50 ⁇ m, preferably from 5-30 ⁇ m, even more preferably from 7-15 ⁇ m, such as 11 ⁇ m.
  • the form of the coils is substantially square, hexagonal, octagonal, multigonal, oval, or substantially circular, such as horizontal and vertical sections forming a substantially circular loop or a circle, or combinations thereof, preferably substantially circular. Such a form provides the best quality factor.
  • the required inductance value is typically in the order of nH, such as from InH to 6OnH, and is adjustable to the application, e.g. an integrated circuit in question, whereas the quality factor is as high as possible, e.g. preferably more than 20. Depending on a process being used to fabricate a chip and on operating frequency, the quality factor may vary from 10 to 25. An additional benefit is a low net magnetic field, resulting in a lower magnetic coupling to other inductors.
  • the present inventor comprises further a first contact, and a second contact, and the above tracks form coils which coils are electrically connected to one another, arranged such that an electrical current can run from the first contact to the second contact, wherein the electrical current in a first eye runs in one direction, and wherein the electrical current in an adjacent eye section runs in another direction.
  • a material is chosen with a low electrical resistivity, such as a metal or metal-like material, such as copper, aluminum, tungsten, or combinations thereof.
  • the invention relates to a clover shaped symmetrical inductor, comprising a second geometrical crossing line situated in a 2-D plane parallel to the main plane of the inductor and being perpendicular to the first geometrical crossing line, at which second line a conducting track of the inductor crosses maximal one another conducting track of the inductor, wherein at the crossing point the two conducting tracks are not in the same plane.
  • a clover-shaped inductor benefits from minimizing the number of crossing points, as indicated above, also in a second dimension, in the present case a horizontal dimension.
  • the invention relates to an inductor, wherein the number of crossing points is equal to the product of the number of inductor eyes (E) and number of turns (n) per coil minus 1 (E*n-i).
  • the invention relates to an inductor, wherein the inductor is formed in two or more parallel layers.
  • Fig. 3 one can see an example of implementations of 8-shaped and clover- shaped inductors, which have a number of crossings points being proportional to the number of turns. In both cases the number of crossing points is proportional to the number of turns. Dashed regions show parts of the crossing points that use under layer(s) of the crossing.
  • the number of crossing points for the new layouts (for example those of figure 4) of 8-shaped and clover-shaped inductors are 2n-l and 4n-l, respectively, wherein n is the number of turns.
  • n is the number of turns.
  • the present invention is only advantageous for n>l .
  • the following tables demonstrate the improvement.
  • d is an inner diameter of an "eye”
  • w is a width of the track of the inductor
  • N is number of crossings points.
  • Numbers C 1 , C 2 and C3 do not depend on d, w and N. These numbers depend on the sheet resistance of the inductor, distance between turns and other parameters of the layout. From the formula it follows that as smaller inner diameter d gets as more significant reduction of number of turns N is for the total resistance. The opposite is also true: the larger d becomes, the less significant JV becomes. This is why results in figures 5-8 are indicative. As such they were obtained for some specific dimensions of coils.
  • This invention allows building inductors of low magnetic coupling without too big compromise in the quality factor. Invention is especially relevant for the multiple turn inductors. Proposed layouts have at least one axis of symmetry and therefore can be used not only in differential but also in the common mode.
  • the invention relates the use of an inductor, for reducing resistance of the inductor and/or for reducing parasitic capacitance, such as capacitance between turns of a coil.
  • the invention in a third aspect relates to a semiconductor device comprising an inductor according to the invention.
  • the invention in a fourth aspect relates to an integrated transceiver chip comprising an inductor according to the invention and/or a semiconductor device according to the invention.
  • the invention relates to an device, such as mobile phone, Bluetooth transceiver, ww Ian, ww pan, ultra-wideband radio, TV tuner, and combinations thereof, comprising an inductor according to the invention and/or a semiconductor device according to the invention.
  • Fig. la-c. a) An inductor at low frequency represented by an equivalent network, b) Difference of potential applied to signal pads of an inductor, used in differential mode, roughly corresponding to an equivalent network, c) A point dividing an inductor in two parts with the same resistance and self inductance.
  • FIG. 2 Example of symmetrical prior art 8-shaped and clover-shaped layouts.
  • Fig. 3 Example of symmetrical 8-shaped and clover-shaped layout.
  • Inner radius of a coil is in fact inner radius of an "eye”.
  • Fig. la-c. a) An inductor at low frequency represented by an equivalent network, b) Difference of potential applied to signal pads of an inductor, used in differential mode, roughly corresponding to an equivalent network, c) A point dividing an inductor in two parts with the same resistance and self inductance. A difference of potential is applied to this point and signal taps in such a way giving an equivalent network.
  • Fig. 2 Example of symmetrical 8-shaped and clover-shaped layouts. In both cases the number of crossing points is proportional to the square of number of turns. Red regions show parts of the crossing points that use under layer(s) of the crossing.
  • Fig. 3 Example of symmetrical 8-shaped and clover-shaped layout. In both cases the number of crossing points is proportional to the number of turns. Red regions show parts of the crossing points that use under layer(s) of the crossing.
  • Inner radius of a coil is in fact inner radius of an "eye”.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Coils Or Transformers For Communication (AREA)

Abstract

L'invention porte sur des topologies de bobine d'inductance en forme de 8 et en forme de trèfle qui minimisent le nombre de points de croisement. Chaque point de croisement augmente la résistance de la bobine d'inductance et la capacité entre enroulements. En conséquence, en maintenant le nombre de points de croisement à un minimum, le facteur de qualité d'une bobine d'inductance augmente. La présente invention porte sur des topologies de bobine d'inductance en forme de 8 et en forme de trèfle dans lesquelles le nombre de points de croisement est minimisé. De nombreuses topologies en forme de 8 et en forme de trèfle ont été décrites dans l'état antérieur de la technique. Celles-ci étaient toutefois typiquement orientées vers une réduction des effets de champ magnétique. Dans la présente invention, la symétrie est pertinente.
PCT/IB2009/050508 2008-02-14 2009-02-09 Topologie optimisée pour bobine d'inductance à faible champ magnétique parasite WO2009101565A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP08101632 2008-02-14
EP08101632.1 2008-02-14

Publications (1)

Publication Number Publication Date
WO2009101565A1 true WO2009101565A1 (fr) 2009-08-20

Family

ID=40585588

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2009/050508 WO2009101565A1 (fr) 2008-02-14 2009-02-09 Topologie optimisée pour bobine d'inductance à faible champ magnétique parasite

Country Status (1)

Country Link
WO (1) WO2009101565A1 (fr)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2421011A1 (fr) * 2010-08-19 2012-02-22 Nxp B.V. Inducteur symétrique
WO2012076998A1 (fr) 2010-12-06 2012-06-14 Nxp B.V. Bobines d'induction de circuit intégré
WO2012128832A1 (fr) * 2011-03-21 2012-09-27 Xilinx, Inc. Structure d'inducteur à prise médiane symétrique
US8427266B2 (en) 2011-03-21 2013-04-23 Xilinx, Inc. Integrated circuit inductor having a patterned ground shield
GB2497310A (en) * 2011-12-06 2013-06-12 Cambridge Silicon Radio Ltd Inductor structure
US8592943B2 (en) 2011-03-21 2013-11-26 Xilinx, Inc. Symmetrical center tap inductor structure
EP2669906A1 (fr) * 2012-06-01 2013-12-04 Nxp B.V. Transformateur à base de circuit intégré
WO2015109183A1 (fr) * 2014-01-17 2015-07-23 Marvell World Trade Ltd Inducteur en forme de pseudo-8
WO2016069195A1 (fr) * 2014-10-31 2016-05-06 Qualcomm Incorporated Réseau de transformateurs en forme de 8 entrelacés présentant une isolation élevée entre des éléments adjacents
CN107240489A (zh) * 2016-03-28 2017-10-10 瑞昱半导体股份有限公司 单端电感器
CN114724799A (zh) * 2021-01-06 2022-07-08 瑞昱半导体股份有限公司 电感装置
US11915848B2 (en) 2020-08-25 2024-02-27 Realtek Semiconductor Corporation Inductor device
US12205755B2 (en) 2020-08-25 2025-01-21 Realtek Semiconductor Corporation Inductor structure

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050195063A1 (en) * 2004-03-03 2005-09-08 Thomas Mattsson Method of and inductor layout for reduced VCO coupling

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050195063A1 (en) * 2004-03-03 2005-09-08 Thomas Mattsson Method of and inductor layout for reduced VCO coupling

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102376415A (zh) * 2010-08-19 2012-03-14 Nxp股份有限公司 对称电感器
EP2421011A1 (fr) * 2010-08-19 2012-02-22 Nxp B.V. Inducteur symétrique
US9196409B2 (en) 2010-12-06 2015-11-24 Nxp, B. V. Integrated circuit inductors
WO2012076998A1 (fr) 2010-12-06 2012-06-14 Nxp B.V. Bobines d'induction de circuit intégré
WO2012128832A1 (fr) * 2011-03-21 2012-09-27 Xilinx, Inc. Structure d'inducteur à prise médiane symétrique
US8427266B2 (en) 2011-03-21 2013-04-23 Xilinx, Inc. Integrated circuit inductor having a patterned ground shield
US8592943B2 (en) 2011-03-21 2013-11-26 Xilinx, Inc. Symmetrical center tap inductor structure
CN103518260A (zh) * 2011-03-21 2014-01-15 吉林克斯公司 对称中央分接头的电感器结构
GB2497310A (en) * 2011-12-06 2013-06-12 Cambridge Silicon Radio Ltd Inductor structure
US8576039B2 (en) 2011-12-06 2013-11-05 Cambridge Silicon Radio Limited Inductor structure
EP2669906A1 (fr) * 2012-06-01 2013-12-04 Nxp B.V. Transformateur à base de circuit intégré
US9159484B2 (en) 2012-06-01 2015-10-13 Nxp, B.V. Integrated circuit based transformer
WO2015109183A1 (fr) * 2014-01-17 2015-07-23 Marvell World Trade Ltd Inducteur en forme de pseudo-8
CN106030730A (zh) * 2014-01-17 2016-10-12 马维尔国际贸易有限公司 似8形状的电感器
US9697938B2 (en) 2014-01-17 2017-07-04 Marvell World Trade Ltd. Pseudo-8-shaped inductor
WO2016069195A1 (fr) * 2014-10-31 2016-05-06 Qualcomm Incorporated Réseau de transformateurs en forme de 8 entrelacés présentant une isolation élevée entre des éléments adjacents
CN107240489A (zh) * 2016-03-28 2017-10-10 瑞昱半导体股份有限公司 单端电感器
US11915848B2 (en) 2020-08-25 2024-02-27 Realtek Semiconductor Corporation Inductor device
US12205755B2 (en) 2020-08-25 2025-01-21 Realtek Semiconductor Corporation Inductor structure
CN114724799A (zh) * 2021-01-06 2022-07-08 瑞昱半导体股份有限公司 电感装置
CN114724799B (zh) * 2021-01-06 2024-06-04 瑞昱半导体股份有限公司 电感装置

Similar Documents

Publication Publication Date Title
WO2009101565A1 (fr) Topologie optimisée pour bobine d'inductance à faible champ magnétique parasite
US7489220B2 (en) Integrated circuits with inductors in multiple conductive layers
US8143987B2 (en) Stacked dual inductor structure
US7808356B2 (en) Integrated high frequency BALUN and inductors
US6759937B2 (en) On-chip differential multi-layer inductor
US10643790B2 (en) Manufacturing method for 3D multipath inductor
JP4505201B2 (ja) ３−ｄスパイラル積層インダクタおよび３−ｄスパイラル積層インダクタを形成する方法
EP2281292B1 (fr) Symetriseur radiofrequence en forme de huit
TWI408796B (zh) 交插式三維晶片上差動電感器及變壓器
US9196409B2 (en) Integrated circuit inductors
US9865392B2 (en) Solenoidal series stacked multipath inductor
US9570233B2 (en) High-Q multipath parallel stacked inductor
US7253712B1 (en) Integrated high frequency balanced-to-unbalanced transformers
US6940386B2 (en) Multi-layer symmetric inductor
EP1357599B1 (fr) Inducteur en spirale empilé sur un substrat semiconducteur
CN1973342B (zh) 平面电感器
JP2006066769A (ja) インダクタ及びその製造方法
WO2012144360A1 (fr) Transformateur haute fréquence, composants haute fréquence et appareil de terminal de communication
US20130020676A1 (en) Solenoid inductor for frequency synthesizer in digital cmos process
US20230230764A1 (en) Offset transformer structure
KR20070032341A (ko) 평면형 인덕터

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09710967

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 09710967

Country of ref document: EP

Kind code of ref document: A1

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载