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WO2009034687A1 - 不揮発性記憶装置および不揮発性記憶装置へのデータ書込方法 - Google Patents

不揮発性記憶装置および不揮発性記憶装置へのデータ書込方法 Download PDF

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Publication number
WO2009034687A1
WO2009034687A1 PCT/JP2008/002291 JP2008002291W WO2009034687A1 WO 2009034687 A1 WO2009034687 A1 WO 2009034687A1 JP 2008002291 W JP2008002291 W JP 2008002291W WO 2009034687 A1 WO2009034687 A1 WO 2009034687A1
Authority
WO
WIPO (PCT)
Prior art keywords
storage apparatus
nonvolatile storage
resistance
resistance state
series
Prior art date
Application number
PCT/JP2008/002291
Other languages
English (en)
French (fr)
Inventor
Yoshikazu Katoh
Kazuhiko Shimakawa
Original Assignee
Panasonic Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corporation filed Critical Panasonic Corporation
Priority to US12/677,421 priority Critical patent/US8102696B2/en
Priority to JP2009532050A priority patent/JP5065401B2/ja
Priority to CN2008801063829A priority patent/CN101802921B/zh
Publication of WO2009034687A1 publication Critical patent/WO2009034687A1/ja

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0038—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0078—Write using current through the cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/10—Resistive cells; Technology aspects
    • G11C2213/15—Current-voltage curve
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor

Landscapes

  • Semiconductor Memories (AREA)

Abstract

　同一極性の電気パルスで複数の抵抗状態の間を遷移する抵抗変化型素子を複数備えたメモリセルアレイを有する不揮発性記憶装置（３００）。メモリセルアレイ（７０）と電気パルス印加装置（５０）との間に直列抵抗設定器（３１０）を設け、直列抵抗設定器を制御することにより、選択された抵抗変化型素子を低抵抗状態から高抵抗状態へと変化させる時および高抵抗状態から低抵抗状態へと変化させる時の少なくとも一方において、直列電流経路の抵抗値を所定の範囲で時間と共に変化させる。
PCT/JP2008/002291 2007-09-10 2008-08-25 不揮発性記憶装置および不揮発性記憶装置へのデータ書込方法 WO2009034687A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US12/677,421 US8102696B2 (en) 2007-09-10 2008-08-25 Nonvolatile memory device and method of writing data to nonvolatile memory device
JP2009532050A JP5065401B2 (ja) 2007-09-10 2008-08-25 不揮発性記憶装置および不揮発性記憶装置へのデータ書込方法
CN2008801063829A CN101802921B (zh) 2007-09-10 2008-08-25 非易失性存储装置和向非易失性存储装置的数据写入方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007233804 2007-09-10
JP2007-233804 2007-09-10

Publications (1)

Publication Number Publication Date
WO2009034687A1 true WO2009034687A1 (ja) 2009-03-19

Family

ID=40451708

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/002291 WO2009034687A1 (ja) 2007-09-10 2008-08-25 不揮発性記憶装置および不揮発性記憶装置へのデータ書込方法

Country Status (4)

Country Link
US (1) US8102696B2 (ja)
JP (1) JP5065401B2 (ja)
CN (1) CN101802921B (ja)
WO (1) WO2009034687A1 (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012026506A1 (ja) * 2010-08-26 2012-03-01 独立行政法人産業技術総合研究所 メモリ素子の駆動方法及びメモリ素子を用いた記憶装置
WO2012056689A1 (ja) * 2010-10-29 2012-05-03 パナソニック株式会社 不揮発性記憶装置
US8421051B2 (en) 2009-08-07 2013-04-16 Kabushiki Kaisha Toshiba Resistance-change memory
US9093143B2 (en) 2013-03-22 2015-07-28 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and method of controlling the same
JPWO2017126451A1 (ja) * 2016-01-18 2018-11-22 日本電気株式会社 論理集積回路および半導体装置

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5095728B2 (ja) * 2007-03-13 2012-12-12 パナソニック株式会社 抵抗変化型記憶装置
CN102422361B (zh) * 2010-03-30 2014-03-19 松下电器产业株式会社 非易失性存储装置和对非易失性存储装置的写入方法
DE102010062238A1 (de) * 2010-03-30 2011-10-06 Robert Bosch Gmbh Startvorrichtung, Schnittstelleneinrichtung und Verfahren zum Betreiben eines Systems einer Startvorrichtung
JP5499364B2 (ja) 2010-08-26 2014-05-21 独立行政法人産業技術総合研究所 メモリ素子の駆動方法及びメモリ素子を備える記憶装置
US8331129B2 (en) * 2010-09-03 2012-12-11 Hewlett-Packard Development Company, L. P. Memory array with write feedback
JP5271460B1 (ja) * 2011-11-29 2013-08-21 パナソニック株式会社 抵抗変化型不揮発性記憶装置及びその書き込み方法
US9087573B2 (en) 2012-03-13 2015-07-21 Semiconductor Energy Laboratory Co., Ltd. Memory device and driving method thereof
US8804434B2 (en) * 2012-05-10 2014-08-12 Nxp, B.V. Pulse-based memory read-out
US9659648B2 (en) * 2012-08-29 2017-05-23 SK Hynix Inc. Semiconductor memory device including switches for selectively turning on bit lines
TW201417102A (zh) * 2012-10-23 2014-05-01 Ind Tech Res Inst 電阻式記憶體裝置
WO2014100024A1 (en) * 2012-12-18 2014-06-26 The Regents Of The University Of Michigan Resistive memory structure for single or multi-bit data storage
US9299409B2 (en) * 2013-09-11 2016-03-29 Tadashi Miyakawa Semiconductor storage device
KR20150058927A (ko) * 2013-11-21 2015-05-29 삼성전자주식회사 불 휘발성 메모리의 쓰기 속도를 제어하는 기술
US9776400B2 (en) 2014-07-26 2017-10-03 Hewlett-Packard Development Company, L.P. Printhead with a number of memristor cells and a parallel current distributor
US9805794B1 (en) * 2015-05-19 2017-10-31 Crossbar, Inc. Enhanced erasing of two-terminal memory
CN108431895B (zh) * 2016-01-27 2023-06-23 慧与发展有限责任合伙企业 忆阻阵列及用于对忆阻阵列编程的方法
US9722822B1 (en) * 2016-03-04 2017-08-01 Inphi Corporation Method and system using driver equalization in transmission line channels with power or ground terminations
US9544864B1 (en) * 2016-03-07 2017-01-10 Panasonic Liquid Crystal Display Co., Ltd. Data transmission system and receiving device
US9819523B2 (en) * 2016-03-09 2017-11-14 Qualcomm Incorporated Intelligent equalization for a three-transmitter multi-phase system
JP2017199443A (ja) * 2016-04-27 2017-11-02 ソニー株式会社 半導体記憶装置、駆動方法、および電子機器
WO2021120136A1 (zh) * 2019-12-19 2021-06-24 浙江大学 存储计算阵列及模组、数据计算方法
US11164628B2 (en) 2020-02-21 2021-11-02 International Business Machines Corporation Compensating PCM drift for neuromorphic applications
US11437092B2 (en) 2020-05-27 2022-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Systems and methods to store multi-level data
TWI784515B (zh) 2020-05-27 2022-11-21 台灣積體電路製造股份有限公司 記憶體系統以及操作記憶體系統的方法
KR20240149637A (ko) * 2023-04-06 2024-10-15 에스케이하이닉스 주식회사 반도체 장치

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006073010A (ja) * 2004-09-02 2006-03-16 Hewlett-Packard Development Co Lp プログラム可能な抵抗メモリ素子のプログラミング
WO2006137111A1 (ja) * 2005-06-20 2006-12-28 Fujitsu Limited 不揮発性半導体記憶装置及びその書き込み方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6597598B1 (en) * 2002-04-30 2003-07-22 Hewlett-Packard Development Company, L.P. Resistive cross point memory arrays having a charge injection differential sense amplifier
JP4205938B2 (ja) 2002-12-05 2009-01-07 シャープ株式会社 不揮発性メモリ装置
US6847544B1 (en) * 2003-10-20 2005-01-25 Hewlett-Packard Development Company, L.P. Magnetic memory which detects changes between first and second resistive states of memory cell
JP4385778B2 (ja) 2004-01-29 2009-12-16 ソニー株式会社 記憶装置
JP2006294182A (ja) 2005-04-14 2006-10-26 Renesas Technology Corp 不揮発性半導体記憶装置
JP2007018615A (ja) * 2005-07-08 2007-01-25 Sony Corp 記憶装置及び半導体装置
JP4203506B2 (ja) 2006-01-13 2009-01-07 シャープ株式会社 不揮発性半導体記憶装置及びその書き換え方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006073010A (ja) * 2004-09-02 2006-03-16 Hewlett-Packard Development Co Lp プログラム可能な抵抗メモリ素子のプログラミング
WO2006137111A1 (ja) * 2005-06-20 2006-12-28 Fujitsu Limited 不揮発性半導体記憶装置及びその書き込み方法

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8421051B2 (en) 2009-08-07 2013-04-16 Kabushiki Kaisha Toshiba Resistance-change memory
WO2012026506A1 (ja) * 2010-08-26 2012-03-01 独立行政法人産業技術総合研究所 メモリ素子の駆動方法及びメモリ素子を用いた記憶装置
US9135990B2 (en) 2010-08-26 2015-09-15 National Institute Of Advanced Industrial Science And Technology Drive method for memory element, and storage device using memory element
WO2012056689A1 (ja) * 2010-10-29 2012-05-03 パナソニック株式会社 不揮発性記憶装置
JP5000026B2 (ja) * 2010-10-29 2012-08-15 パナソニック株式会社 不揮発性記憶装置
US8619460B2 (en) 2010-10-29 2013-12-31 Panasonic Corporation Nonvolatile memory device and method for programming nonvolatile memory element
US9093143B2 (en) 2013-03-22 2015-07-28 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and method of controlling the same
JPWO2017126451A1 (ja) * 2016-01-18 2018-11-22 日本電気株式会社 論理集積回路および半導体装置

Also Published As

Publication number Publication date
CN101802921A (zh) 2010-08-11
US20100202185A1 (en) 2010-08-12
US8102696B2 (en) 2012-01-24
JP5065401B2 (ja) 2012-10-31
JPWO2009034687A1 (ja) 2010-12-24
CN101802921B (zh) 2013-08-28

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