+

WO2009030165A1 - Ldmos et dispositif à semi-conducteur intégré à ldmos et cmos - Google Patents

Ldmos et dispositif à semi-conducteur intégré à ldmos et cmos Download PDF

Info

Publication number
WO2009030165A1
WO2009030165A1 PCT/CN2008/072196 CN2008072196W WO2009030165A1 WO 2009030165 A1 WO2009030165 A1 WO 2009030165A1 CN 2008072196 W CN2008072196 W CN 2008072196W WO 2009030165 A1 WO2009030165 A1 WO 2009030165A1
Authority
WO
WIPO (PCT)
Prior art keywords
type
doped region
drain
source
channel
Prior art date
Application number
PCT/CN2008/072196
Other languages
English (en)
Chinese (zh)
Inventor
Jian Tan
Original Assignee
Jian Tan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jian Tan filed Critical Jian Tan
Publication of WO2009030165A1 publication Critical patent/WO2009030165A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/856—Complementary IGFETs, e.g. CMOS the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0191—Manufacturing their doped wells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates

Definitions

  • the present invention relates to LDM0S and semiconductor devices integrating LDM0S and CMOS. Specifically, it is a laterally diffused metal oxide semiconductor transistor (LDM0S) and its integration with a CMOS process.
  • LDM0S laterally diffused metal oxide semiconductor transistor
  • CMOS Complementary Metal Oxide Semiconductor
  • LDM0S Low Density Device
  • Power management refers to the combination of circuits used to control the conversion and delivery of electrical energy to the appropriate load.
  • This load can be any chip, system or subsystem such as a microprocessor chip, a floating point processor, an optics, a micro motor system, and the like.
  • the CMOS process is driven by digital technology, the minimum gate line width becomes smaller and smaller, and the oxide layer thickness is correspondingly thinner and thinner. This makes the CMOS integration per unit area higher and higher, and at the same time makes the corresponding CMOS speed is getting faster and faster.
  • LDM0S is usually much higher than CMOS due to breakdown voltage, and is usually a process that is several generations behind CMOS. Moreover, the thickness of the oxide layer is also different from the standard CMOS process. In recent years there has been a trend to integrate CMOS and LDM0S on the same semiconductor substrate. Since CMOS and LDM0S have different processes, it is not easy to integrate them together. CMOS and LDM0S, which are usually integrated together, have different oxide thicknesses and different minimum line widths. And often the minimum gate line width of LDM0S is several times larger than that of CMOS.
  • LDM0S and CMOS processes have the same oxide thickness, but they are usually integrated with some older CMOS processes, such as 0.5 micron or even older. And despite this, the LDM0S's minimum gate linewidth is still several times larger than CMOS.
  • the minimum gate line width of LDM0S is larger than CMOS, it indicates that the LDM0S does not fully utilize advanced CMOS process technology to optimize the LDM0S index. It just completed a simple merger of two sets of processes.
  • Such LDM0S requires a lot of energy to drive, and the turn-off speed is very slow, so the switching frequency is very low, such as 300 kHz.
  • the present invention provides an LDMMOS comprising a semiconductor substrate, a channel on a surface of the substrate, and a gate on the channel, further comprising: a source/drain, the source/drain a lightly doped region adjacent to the channel and next to the channel and a heavily doped region next to the lightly doped region; a reverse opposite to the source/drain doping type a doped well, the reverse doped well being under the channel and completely containing the channel; a reverse doped region opposite to the source/drain doping type, the reverse doped region being located Between the heavily doped region of the source/drain and the counter doped well.
  • the present invention also provides another LDMMOS comprising a semiconductor substrate, a channel on the surface of the substrate, and a gate on the channel, further characterized by: a source/drain, the source/ The drain includes a lightly doped region next to the channel next to the channel and a heavily doped region next to the lightly doped region; one opposite the source/drain doping type a reverse doped well, the reverse doped well being under the channel and completely containing the channel; another doping region of the same type as the source/drain doping, the another doping region A heavily doped region and a lightly doped region surrounding the source/drain and the counter doped well.
  • a source/drain the source/ The drain includes a lightly doped region next to the channel next to the channel and a heavily doped region next to the lightly doped region; one opposite the source/drain doping type a reverse doped well, the reverse doped well being under the channel and completely containing the channel; another doping region of the same type as the source/drain doping
  • the present invention also provides a semiconductor device integrated with LDMOS and CMOS, comprising a CMOS and an LDMOS disposed on a semiconductor substrate, the CMOS comprising an NM0S and a PIOS, the LDMOS comprising an N-LDMOS and a P- LDM0S, wherein the N-LDMOS and the P-LDMOS each comprise: a channel on a surface of the substrate, a gate on the channel,
  • the source/drain comprising a lightly doped region next to the channel next to the channel and a heavily doped region next to the lightly doped region;
  • a counter doped region opposite to the source/drain doping type the counter doped region being between the heavily doped region of the source/drain and the counter doped well.
  • the present invention also provides a semiconductor device integrated with LDMOS and CMOS, comprising a CMOS and an LDMOS disposed on a semiconductor substrate, the CMOS comprising an NM0S and a PIOS, the LDMOS comprising an N-LDMOS and a P- LDM0S, wherein the N-LDMOS and the P-LDMOS each comprise: a channel on a surface of the substrate, a gate on the channel,
  • the source/drain comprising a lightly doped region next to the channel next to the channel and a heavily doped region next to the lightly doped region;
  • a reverse doped well opposite to the source/drain doping type the reverse doped well being located below the channel and completely containing the channel;
  • Another doping region of the same source/drain doping type the other doping region surrounding the source/drain heavily doped region and the lightly doped region and the reverse doping Miscellaneous trap.
  • the present invention also describes how to integrate the LDM0S with a CMOS process. As can be seen from the process flow, this LDM0S makes full use of the existing CMOS (BiCMOS) process, greatly reducing the number of mask layers.
  • BiCMOS CMOS
  • the LDM0S provided by the invention has the advantages of fast switching speed, small on-resistance, low parasitic capacitance and low cost.
  • FIG. 13 are cross-sectional views showing main processes of a semiconductor device in which the semiconductor LDM0S of the present invention and an integrated LDM0S and CMOS are fabricated;
  • Figure 14 to Figure 17 show the P-LDM0S and N-LDM0S with high voltage on one side;
  • Fig. 18 is a schematic view showing the structure of the device shown in Fig. 14 in which the source and the drain can withstand high voltage. detailed description
  • An LDMOS as shown in FIG. 14 and FIG. 15, includes a P-LDOS0 and an N-LDOS, which are co-located on a semiconductor substrate 211, and each of the P-LDMOS and the N-LDMOS includes a substrate 211.
  • a channel of the surface and a gate 270, a source/drain, on the channel, the source/drain comprising a lightly doped region 256, 257 located next to the channel and next to the channel And a heavily doped region 266, 267 next to the lightly doped regions 256, 257; a reverse doped well 241, 242 opposite the source/drain doping type, the reverse doped well 241, 242 is located under the channel and completely includes the channel; a reverse doped region 235, 236 opposite to the source/drain doping type, the reverse doped region 235, 236 is located at the source / between the heavily doped regions 266, 267 of the drain and the counter doped wells 241, 242.
  • Figure 14 shows that the LDMOS is implemented on a P-type epitaxial layer.
  • a P-type epitaxial layer 222 is further disposed on the substrate 211.
  • the channels of the P-LDMOS and the N-LDOS are located on the surface of the epitaxial layer 222, and the source/drain of the N-LDOS is an N-type lightly doped region. 257 and an N-type heavily doped region 267, the reverse doped well 242 of the N-LDOS0 is a P-type well, and the reverse doped region 236 of the N-LDOS0 is a P-type doped region or a P-type
  • the epitaxial layer 222 is formed to have a lower doping concentration than the counter doped well 242.
  • the source/drain of the P-LDOS0 is a P-type lightly doped region 256 and a P-type heavily doped region 266, and the inverted doped well 241 of the P-LDOSOS is an N-type well, and the P-LDM0S
  • the counter doped region 235 is an N-type doped region having a lower doping concentration than the counter doped well 241.
  • the P-LDMOS has been isolated from other components on the epitaxial layer 222 through the N-type reverse doping region 235, and the N-LDMOS can be non-isolated, Can be isolated.
  • the isolated structure is shown in Figure 14.
  • the method further includes a deep N-type doped well 231 surrounding the source/drain, the reverse doped well 242, and the reverse doped region 236, which form an integral part, and an underlying N-type buried The layer 221 or the N-type substrate 211 is incorporated. If the N-LDM0S is not surrounded by the deep N-type doped well 231 and the underlying N-type buried layer 221 or the N-type substrate 211, it is non-isolated N_LDM0S.
  • N - LDM0S and P - LDM0S may be asymmetric or symmetric.
  • Figure 14 shows the asymmetric N-LDM0S and the asymmetric P-LDM0S.
  • the asymmetric P-LDOSOS also includes another source/drain that includes another P-type heavily doped region 266 next to the channel and next to the channel.
  • the asymmetric N-LDOSOS also includes another source/drain that includes another N-type heavily doped region 267 located next to the channel and next to the channel.
  • the symmetrical structure is shown in Figure 18.
  • the symmetrical P-LDOSOS also includes another source/drain that includes another P-type next to the channel and next to the channel.
  • the symmetric N-LDOSOS further includes another source/drain, the other source/drain comprising a further N-type lightly doped region 257 located next to the channel next to the channel and a compact Another N-type heavily doped region 267 of the other N-type lightly doped region 257 is present.
  • the symmetric P-LDMOS has been isolated from other components on the epitaxial layer 222 by the N-type reverse doped well 241, and the symmetric N-LDOS0 can be either non-isolated or isolated.
  • the isolated structure is as shown in FIG. 18, further comprising surrounding the source/drain, the reverse doped well 242 and the reverse doped region 236, and the other source/drain four parts constitute a whole.
  • the symmetric N-LDM0S is not surrounded by the deep N-type doped well 231 and the underlying N-type buried layer 221 or the N-type substrate 211, it is a symmetric non-isolated N-LDM0S.
  • the LDMOS can also be implemented on the N-type epitaxial layer. As shown in FIG. 15, an N-type epitaxial layer 223 is further disposed on the substrate 211. The channels of the P-LDM0S and the N-LDOS are located on the surface of the epitaxial layer 223.
  • the source/drain of the N-LDOS0 is an N-type lightly doped region 257 and an N-type heavily doped region 267, and the reverse doped well 242 of the N-LDOS0 is a P-type well, the N-LDM0S
  • the counter doped region 236 is a P-type doped region having a lower doping concentration than the counter doped well 242.
  • the source/drain of the P-LDOS0 is a P-type lightly doped region 256 and a P-type heavily doped region 266, and the inverted doped well 241 of the P-LDOSOS is an N-type well, and the P-LDM0S
  • the counter doped region 235 is formed of an N-type doped region or an N-type epitaxial layer 223 having a lower doping concentration than the reverse doped well 241.
  • the N-LDMOS has been isolated from other components on the epitaxial layer 223 by the P-type reverse doped well 242, and the P-LDMOS can be non-isolated as well. Can be isolated.
  • the isolated structure is as shown in FIG. 15 , and further includes a deep P-type doped well surrounding the three sides of the source/drain, the counter doped well 241 and the counter doped region 235 to form a whole. 232 and the underlying P-type buried layer 224 or P-type substrate 211.
  • N-LDM0S and P-LDM0S which are also on the N-type epitaxial layer, can be either asymmetric or symmetrical.
  • Figure 15 shows an asymmetric N-LDM0S and an asymmetric P-LDM0S.
  • the asymmetric P-LDOSOS also includes another source/drain that contains a tightly located side of the channel. Another P-type light and heavy region 266 is next to the channel.
  • the asymmetric N-LDMOS further includes another source/drain that includes another N-type heavily doped region 267 next to the channel and next to the channel.
  • the symmetric P-LDOSOS further includes another source/drain, the other source/drain comprising a further P-type lightly doped region 256 next to the channel next to the channel and a compact Another P-type heavily doped region 266 of the other P-type lightly doped region 256 is present.
  • the symmetric N-LDOSOS further includes another source/drain, the other source/drain comprising a further N-type lightly doped region 257 located next to the channel next to the channel and a compact Another N-type heavily doped region 267 of the other N-type lightly doped region 257 is present.
  • the symmetric N-LDM0S has been isolated from the other components on the epitaxial layer 223 by the P-type reverse doped well 242, and the symmetric P-LDM0S can be either non-isolated or isolated.
  • the isolated structure further includes a depth P-type surrounding the source/drain, the counter doped well 241 and the counter doped region 235, and the other source/drain portions constitute an integral side
  • the well 232 is doped and the underlying P-type buried layer 224 or P-type substrate 211.
  • the symmetric P-LDM0S is not surrounded by the deep P-type doped well 232 and the underlying P-type buried layer 224 or the P-type substrate 211, it is a symmetric non-isolated P_LDM0S.
  • an LDMOS includes a P-LDOS0 and an N-LDOS, which are co-located on a semiconductor substrate 211, and each of the P-LDMOS and the N-LDMOS includes a surface on the substrate 211.
  • Figure 16 shows that the LDMOS is implemented on a P-type epitaxial layer.
  • a P-type epitaxial layer 222 is further disposed on the substrate 211.
  • the channels of the P-LDM0S and the N-LDOS are located on the surface of the epitaxial layer 222, and the source/drain of the N-LDOS0 is an N-type lightly doped region.
  • 257 and N-type heavily doped region 267, the reverse doped well 242 of the N-LDOS0 is a P-type well, and the other doped region 238 of the N-LDOS0 is an N-type doped region, and its doping concentration Lower than the counter doped well 242.
  • the source/drain of the P-LDOS0 is a P-type lightly doped region 256 and a P-type heavily doped region 266, and the inverted doped well 241 of the P-LDOSOS is an N-type well, and the P-LDM0S
  • the other doped region 237 is a P-type doped region or is formed of a P-type epitaxial layer 222 having a lower doping concentration than the counter doped well 241.
  • the N-LDMOS has passed through the N-type doping region 238 and the same on the epitaxial layer 222. Its components are isolated, while P-LDMOS can be either non-isolated or isolated.
  • the isolated structure is as shown in FIG. 16, and further includes a deep N-type doped well surrounding the three sides of the source/drain, the counter doped well 241 and the other doped region 237 to form a whole. 231 and the underlying N-type buried layer 221 or the N-type substrate 211. If the P-LDM0S is not surrounded by the deep N-type doped well 231 and the underlying N-type buried layer 221 or the N-type substrate 211, it is non-isolated P_LDM0S.
  • N - LDM0S and P - LDM0S may be asymmetric or symmetric.
  • Figure 16 shows the asymmetric N-LDM0S and the asymmetric P-LDM0S.
  • the asymmetric P-LDOSOS also includes another source/drain that includes another P-type heavily doped region 266 next to the channel and next to the channel.
  • the asymmetric N-LDOSOS also includes another source/drain that includes another N-type heavily doped region 267 located next to the channel and next to the channel.
  • the symmetric P-LDOSOS further includes another source/drain, the other source/drain comprising a further P-type lightly doped region 256 next to the channel next to the channel and a compact Another P-type heavily doped region 266 of the other P-type lightly doped region 256 is present.
  • the symmetric N-LDOSOS further includes another source/drain, the other source/drain comprising a further N-type lightly doped region 257 located next to the channel next to the channel and a compact Another N-type heavily doped region 267 of the other N-type lightly doped region 257 is present.
  • the symmetric N-LDM0S has been isolated from other components on the epitaxial layer 222 by another N-type doped region 238, and the symmetric P-LDM0S can be either non-isolated or isolated.
  • the isolated structure further includes a depth N-type surrounding the source/drain, the reverse doped well 241 and the other doped region 237, and the other source/drain portions constitute an integral two sides
  • the well 231 and the underlying N-type buried layer 221 or the N-type substrate 211 are doped.
  • the symmetric P-LDM0S is not surrounded by the deep N-type doped well 231 and the underlying N-type buried layer 221 or the N-type substrate 211, it is a symmetric non-isolated P_LDM0S.
  • the LDMOS may also be implemented on the N-type epitaxial layer. As shown in FIG. 17, an N-type epitaxial layer 223 is further disposed on the substrate 211. The channels of the P-LDM0S and the N-LDOS are located on the surface of the epitaxial layer 223.
  • the source/drain of the N-LDOS0 is an N-type lightly doped region 257 and an N-type heavily doped region 267, and the reverse doped well 242 of the N-LDOS0 is a P-type well, the N-LDM0S
  • the other doped region 238 is an N-type doped region or is formed of an N-type epitaxial layer 223 having a lower doping concentration than the reverse doped well 242.
  • the source/drain of the P-LDOS0 is a P-type lightly doped region 256 and a P-type heavily doped region 266, and the inverted doped well 241 of the P-LDOSOS is an N-type well, and the P-LDM0S
  • the other doped region 237 is a P-type doped region having a lower doping concentration than the counter doped well 241.
  • the P-LDMOS has been isolated from other components on the epitaxial layer 223 by another P-type doping region 237, and the N-LDMOS can be non-isolated, Can be isolated.
  • the isolated structure is as shown in FIG. 17, and further includes a deep P-type doped well surrounding the two sides of the source/drain, the counter doped well 242 and the other doped region 238. 232 and the underlying P-type buried layer 224 or P-type substrate 211. If the N-LDM0S is not surrounded by the deep P-type doped well 232 and the underlying P-type buried layer 224 or the P-type substrate 211, it is non-isolated N_LDM0S.
  • the N-LDMOS and P-LDMOS on the N-type epitaxial layer can be either asymmetric or symmetrical.
  • Figure 17 shows an asymmetric N-LDM0S and an asymmetric P-LDM0S.
  • the asymmetric P-LDOSOS also includes another source/drain, the other source/drain containing a tightly located side of the channel.
  • Another P-type light and heavy region 266 is next to the channel.
  • the asymmetric N-LDMOS further includes another source/drain that includes another N-type heavily doped region 267 next to the channel and next to the channel.
  • the symmetric P-LDOSOS further includes another source/drain, the other source/drain comprising a further P-type lightly doped region 256 next to the channel next to the channel and a compact Another P-type heavily doped region 266 of the other P-type lightly doped region 256 is present.
  • the symmetric N-LDOSOS further includes another source/drain, the other source/drain comprising a further N-type lightly doped region 257 located next to the channel next to the channel and a compact Another N-type heavily doped region 267 of the other N-type lightly doped region 257 is present.
  • the symmetric P-LDM0S has been isolated from other components on the epitaxial layer 223 by another P-type doped region 237, and the symmetric N-LDM0S can be either non-isolated or isolated.
  • the isolated structure further includes a depth P-type surrounding the source/drain, the reverse doped well 242 and the other doped region 238, and the other source/drain portions constitute an integral side
  • the well 232 is doped and the underlying P-type buried layer 224 or P-type substrate 211. If the symmetric N-LDM0S is not surrounded by the deep P-type doped well 232 and the underlying P-type buried layer 224 or the P-type substrate 211, it is a symmetric non-isolated N_LDM0S.
  • a semiconductor device integrated with LDMOS and CMOS includes a CMOS and an LDMOS disposed on a semiconductor substrate 211.
  • the CMOS includes an NMOS and a PMOS
  • the LDMOS includes an N- LDM0S and a P-LDM0S, wherein the PMOS and the MN include:
  • a source/drain comprising a lightly doped region 251, 252 and heavily doped regions 261, 262 next to the lightly doped regions 251, 252,
  • a counter doped well 241, 242 of opposite type to the source/drain doping is provided.
  • a source/drain comprising a lightly doped region 256, 257 next to the channel next to the channel and a heavily doped layer adjacent to the lightly doped regions 256, 257 Miscellaneous area 266, 267;
  • the counter doped regions 235, 236 being located in the source/drain heavily doped regions 266, 267 and the inverse Between the doped wells 241, 242. As shown in FIGS. 14 and 15, the doping concentration of the heavily doped region 267 of the source/drain of the N-LDOS0 is lower than the doping concentration of the heavily doped region 262 of the NMOS source/drain.
  • the doping concentration of the heavily doped region 266 of the source/drain of the P-LDOS0 is lower than the doping concentration of the heavily doped region 261 of the PM0S source/drain.
  • the N-LDOS and the MN have opposite doped wells 242 of the same doping profile.
  • the P-LDOS and the PMOS have opposite doped wells 241 of the same doping profile.
  • a semiconductor device integrated with LDMOS and CMOS includes a CMOS and an LDMOS disposed on a semiconductor substrate 211.
  • the CMOS includes an NMOS and a PMOS
  • the LDMOS includes an N- LDM0S and a P-LDM0S, wherein the PMOS and the MN include:
  • a source/drain comprising a lightly doped region 251, 252 and heavily doped regions 261, 262 next to the lightly doped regions 251, 252,
  • a counter doped well 241, 242 of opposite type to the source/drain doping is provided.
  • the P-LDMOS and the N-LDMOS each comprise: a channel on the surface of the substrate 211, and a gate 270 on the channel,
  • a source/drain comprising a lightly doped region 256, 257 next to the channel next to the channel and a heavily doped layer adjacent to the lightly doped regions 256, 257 Miscellaneous area 266, 267;
  • Another doped region 237, 238 of the same source/drain doping type the other doped regions 237, 238 surrounding the source/drain heavily doped regions 266, 267 and lightly doped Regions 256, 257 and the counter doped wells 241, 242.
  • the doping concentration of the source/drain heavily doped region 267 of the N-LDOS0 is lower than the doping concentration of the heavily doped region 262 of the source/drain.
  • the doping concentration of the heavily doped region 266 of the source/drain of the P-LDOS0 is lower than the doping concentration of the heavily doped region 261 of the PM0S source/drain.
  • the N-LDOSS and the NMOS have reverse doping wells 242 having the same doping profile.
  • the P-LDOSOS and the PMOS have opposite doped wells 241 having the same doping profile.
  • the description of the present invention is in the context of applications in power management, but any other application that combines high voltage devices and low voltage devices will be within the scope of the present invention.
  • the low voltage device referred to in the present invention refers to a standard operating voltage device used in the selected CMOS process; and the high voltage device refers to a device in which the drain/source can withstand higher than the standard voltage.
  • the gate voltage is not limited and can be the same voltage as a standard CMOS process or a higher or lower voltage than a standard CMOS process. As long as the drain/source voltage is higher than the standard voltage, it is the high voltage device referred to in this embodiment.
  • the drain/source operating voltage of a standard device is 2.5 volts, which is a low voltage device referred to in the present invention.
  • a high voltage device is one in which the drain/source is subjected to a voltage higher than 2.5 volts, regardless of whether the highest voltage that the gate can withstand is higher than, lower than or equal to 2.5 volts.
  • FIG. 1 to 13 are cross-sectional views showing the main process flow of the LDM0S device of the present invention. All cross-sectional views of the present invention are not drawn to scale, in accordance with the practice of the semiconductor industry. The following description of the process is only the main process steps to achieve the structure of the device. Those skilled in the art will be aware of the secondary steps not mentioned therein, and the description of these main process steps does not constitute a limitation of the invention.
  • FIG. 1 is a cross-sectional view showing a semiconductor device of the present invention after a buried layer and an epitaxial layer are completed.
  • the semiconductor device begins with a semiconductor substrate 211, and then an epitaxial layer 212 is grown on the substrate 211.
  • Epitaxial layer 212 may or may not be required at times.
  • both 211 and 212 are P-type, but they may all be N-type, or one of them is a P-type and the other is an N-type.
  • the P-type and the N-type referred to in the present invention mean that the semiconductors ultimately exhibit different electrode properties due to different types of doping.
  • the P-type doping is usually an implanted boron element, but may be any other element that causes the semiconductor to exhibit a P-type.
  • the N-type doping is usually implanted with a nitrogen (N) element or an arsenic (As) element, but may be any other impurity that causes the semiconductor to exhibit an N-type.
  • the description in this embodiment is exemplified by a P-type substrate.
  • the epitaxial layer 212 is first oxidized and then photolithographically patterned through a mask to locate the layer 221 where it needs to be buried. Lithographic positioning as referred to herein is a commonly used process in semiconductor fabrication. It is to first uniformly apply the photoresist material to the surface of the semiconductor, and then expose the photoresist material in the place where the mask is not needed through the mask, and then remove the exposed photoresist material.
  • the remaining photoresist material is used for the mask of the next process. Since the lithographic positioning is a process commonly used in semiconductor fabrication processes, the process will not be described in detail in the following processes.
  • the oxide layer is etched away, and the N-type impurity is implanted by using the photoresist material and the oxide layer as a mask, and then the temperature is raised to diffuse the implanted impurities and activate to form the buried layer 221 .
  • the surface photoresist material and oxide layer are then removed and an epitaxial layer 222 is formed over the surface.
  • This epitaxial layer 222 may be either N-type or P-type. In this embodiment, the P type is taken as an example.
  • the epitaxial layer has a relatively low impurity concentration, such as 1 X 10 13 to 1 X 10 15 per cubic centimeter.
  • Another method of forming the buried layer 222 is to first form the epitaxial layer 222 on the substrate 211 and the epitaxial layer 212, and then position the buried layer 221 by mask lithography where the layer 221 needs to be buried. Impurity implantation and high temperature diffusion to activate the implanted impurities form the buried layer 221.
  • any other formation well known in the art The method of embedding the layers is within the scope of the present invention.
  • Figure 2 shows a cross-sectional view of the semiconductor process after completion of the deep N-well.
  • a region where deep N-type wells 231, 235 are required is photolithographically patterned on the basis of Fig. 1, N-type impurity implantation is performed, and then thermally diffused to form deep N-type wells 231, 235.
  • the locations where the four devices are formed are shown in Figure 2 below: PM0S, NM0S, P-LDM0S, N_LDM0S.
  • the N-wells 231 and 235 may be the same impurity distribution. This makes it only necessary to mask once when forming the N-wells 231, 235.
  • the P-well 236 in the figure can be either an epitaxial layer 222 or a deep P-well 236 that is positioned through a mask.
  • Figure 3 shows a cross-sectional view of the semiconductor process after the isolation trench is completed.
  • STI shallow trench isolation
  • LOCOS basic regional oxidation isolation technology
  • First through a mask lithography The position of the isolation trench is located, and then oxidized, and then the photoresist material and the surface oxide layer are removed.
  • Figure 3 shows that after the isolation trench is formed, the substrate 211 is divided into four regions separated by isolation trenches. The regions will form different devices: PM0S, NM0S, P-LDM0S, and N-LDM0S.
  • NM0S and PMOS are standard devices provided in the CMOS process, which are the low-voltage devices defined in this embodiment. These devices are mainly used for A variety of circuit design, such as controllers, signal processors, etc. And P-LDM0S and N-LDM0S are high-voltage devices as defined in this embodiment. Usually used for power conversion output stage, power device drive circuit , sometimes used in control circuits.
  • Figure 4 shows a cross-sectional view of the semiconductor process after completion of the N-well 241 step.
  • the position where the N-type well 241 is required is first positioned by mask lithography, and then the N-type well 241 is formed by N-type impurity implantation and thermal diffusion.
  • the N-well 241 is an important step in the formation of PM0S and P-LDM0S.
  • the figure shows that for the P-LDM0S, this N-well 241 is implanted into the aforementioned deep well 235.
  • the impurity concentration of the N-type well is higher than the impurity concentration of the deep N-type well 235 and the epitaxial layer 222.
  • impurity implantation of the domain voltage adjustment is performed immediately after the N-type well impurity implantation is performed using the same N-type well mask.
  • PM0S and P-LDM0S can have different N-type well impurity distributions, but in order to simplify the process, the same impurity distribution can be used to share the same mask.
  • Figure 5 shows a cross-sectional view of the semiconductor process after completion of the P-well 242 step.
  • the place where the P-type well 242 is required is first positioned by mask lithography, and then the P-type well 242 is formed by P-type impurity implantation and thermal diffusion.
  • the P-well is an important step in the formation of the Li OS and N-LDM0S.
  • the figure shows that for the Li OS, this P-type well is implanted into the aforementioned epitaxial layer 222.
  • the N-LDM0S this P-type well is implanted into the aforementioned deep well 236.
  • the impurity concentration of the P-type well is higher than the impurity concentration of the deep P-type well 236 and the epitaxial layer 222.
  • the impurity injection of the domain voltage adjustment is performed immediately by the same P-type well mask.
  • the OS and N-LDM0S can have different P-type well impurity distributions, but also to simplify the process, the same impurity distribution can be used to share the same mask.
  • the process sequence of Figures 5 and 4 above may be interchanged.
  • Figure 6 shows a cross-sectional view of the semiconductor process after completion of the gate.
  • the gate dielectric layers 275, 276 are first oxidized to a specified thickness.
  • the dielectric layer is typically made of silicon dioxide. Other commonly used dielectric materials are also within the scope of the present invention.
  • the gate dielectric 276 of the high voltage devices P-LDM0S and N-LDM0S preferably has the same thickness as the gate dielectric 275 of the low voltage devices PM0S and NMOS. This can be done only after one oxidation process.
  • the gate dielectric 276 of the high voltage device P-LDM0S or N-LDM0S is sometimes required to be thicker than the gate dielectric 275 of the low voltage devices PM0S and NMOS. This requires two oxidations. In this case, a thick gate dielectric 276 can be oxidized first, and then a region of the thin gate dielectric 275 is required to be photolithographically patterned through a mask. The dielectric in the region is etched away, the photoresist material is removed, and the gate dielectric 275 of the low voltage devices PM0S and NMOS is formed.
  • the gate dielectric of the high-voltage device P-LDM0S or N-LDM0S is subjected to a threshold voltage adjustment impurity injection in this step due to the excessive thickness.
  • polysilicon is deposited onto the gate dielectrics 275, 276, and then the polysilicon is doped to an N-type or a P-type with an appropriate impurity species. The doping is then activated by high temperature annealing. Finally, a mask is used to position the gate 270.
  • Figure ⁇ shows a cross-sectional view of the semiconductor process after completion of the N-type low-voltage lightly doped region 252 and the P-type low-voltage lightly doped region 251. Their positions are determined by their respective mask lithographic positioning. It is then formed by impurity implantation. The N-type low-voltage light-doped region 252 is implanted into the N-type impurity, and the P-type impurity is implanted to form the P-type low-voltage light-doped region 251.
  • Figure 8 shows a cross-sectional view of the semiconductor process after forming an N-type high voltage lightly doped region 257 and a P-type high voltage lightly doped region 256.
  • the position and width of the N-type high-voltage lightly doped region 257 and the P-type high-voltage lightly doped region 256 are respectively determined by photolithographic positioning of respective masks, and then formed by impurity implantation.
  • the N-type high-voltage light-doped region 257 is implanted with N-type impurities
  • the P-type high-voltage light-doped region 256 is implanted with P-type impurities.
  • the high voltage lightly doped regions 257, 256 have a lower doping concentration than the low voltage lightly doped regions 252, 251.
  • This N-type high-voltage lightly doped region 257 is a necessary step in forming the N-LDM0S, which allows the N-LDM0S to withstand voltages that are higher than the source/drain of the OS source.
  • This pole is usually the drain of the N-LDM0S, but it can also be the source.
  • P-type high voltage lightly doped region 256 is a necessary step in forming P-LDMOS. It allows the P-LDM0S to withstand voltages that are higher than the PM0S drain/source. This pole is usually the drain of P-LDM0S, but it can also be the source.
  • Figure 9 shows a cross-sectional view of the semiconductor process after forming the gate spacer structure 271.
  • the gate spacer structure 271 is typically formed by oxidizing the gate polysilicon followed by etching a portion of the silicon oxide that etches away the surface layer of the gate polysilicon. Other ways of forming 271 in the art are also within the scope of the invention.
  • Figure 10 shows a cross-sectional view of the semiconductor process forming the heavily doped regions 262, 267 of the MN and N-LDMOS. They are each lithographically positioned by a mask and then formed by N-type impurity implantation. For NM0S, this heavily doped region 262 forms the source/drain of the MN. For the N-LDMOS, the heavily doped region 267 forms a low voltage source/drain and the other must withstand The high voltage source/drain is formed by a heavily doped region 267 and a lightly doped region 257 next to it.
  • the heavily doped region 262 of the low voltage device LM source/drain has the same doping concentration profile as the heavily doped region 267 of the high voltage device N-LDM0S source/drain. This allows a mask to be shared for lithographic positioning. In certain cases, the heavily doped region 267 of the high voltage device N-LDM0S source/drain may have a different doping profile than the heavily doped region 262 of the low voltage device NMOS source/drain to increase the source of the high voltage device/ The breakdown voltage of the drain. In this case, each requires a different mask for lithographic positioning. In addition, the heavily doped region 267 of the source/drain of the high voltage device N-LDM0S is next to the lightly doped region 257 of the source/drain of the high voltage device N-LDM0S.
  • Figure 11 shows a cross-sectional view of the semiconductor process forming PM0S and P-LDM0S source/drain heavily doped regions 261, 266. They are each photolithographically positioned and then formed by P-type impurity implantation. For PM0S, this heavily doped region 261 forms the source/drain of the PMOS. For the P-LDM0S, the heavily doped region 266 forms a low voltage source/drain and the other has to withstand the high voltage source/drain. The heavily doped region 266 and the lightly doped region 256 next to each other are formed together.
  • the heavily doped region 261 of the low voltage device PM0S source/drain has the same doping concentration profile as the heavily doped region 266 of the source/drain of the high voltage device P-LDM0S. This allows a mask to be shared for lithographic positioning.
  • the heavily doped region 266 of the high voltage device P-LDM0S source/drain may have a different doping profile than the heavily doped region 261 of the low voltage device NMOS source/drain to increase the source of the high voltage device/ The breakdown voltage of the drain.
  • the heavily doped region 266 of the high-voltage device P-LDM0S source/drain is next to the lightly doped region 256 of the source/drain of the high voltage device P-LDM0S.
  • Figure 12 shows a cross-sectional view of the semiconductor process after forming the metal silicide layer 268.
  • a mask lithography is used to locate the source/drain of the source/drain in the NM0S, PM0S, N-LDM0S, and P-LDM0S, and then the surface of the dielectric is etched away to precipitate the metal material (usually aluminum).
  • the surface of the silicon substrate is finally annealed at a high temperature.
  • the metal in contact with the silicon surface chemically reacts with silicon at a high temperature to form a metal silicide layer 268.
  • the remaining metal that did not react was then etched away.
  • Figure 13 shows a cross-sectional view of the semiconductor process after forming a first metal connection.
  • a substrate is deposited on the substrate after the above steps are completed, and then a mask lithography is used to locate the place where the first metal connection port needs to be opened.
  • the medium at this location is etched away to form the medium 280 of FIG.
  • Figure 14 shows a cross-sectional view of the above device after forming a first layer of metal connections 285.
  • a layer of metal material usually aluminum
  • the metal forms a first metal connection layer 285.
  • the process of Figures 13 and 14 can be repeated many times to form a multilayer metal bond.
  • semiconductor processes have 1 to 7 metal connections.
  • the deep N-well 235 and the N-well 241 of the P-LDMOS in FIG. 14 use different masks for horizontal positioning.
  • the figure shows that the deep N-well 235 fully encapsulates the N-well 241 from side to bottom, and does not need to be fully packaged. Only the deep N-well 235 and the N-well 241 are connected. In this case, the potential of the deep N-type well 235 is ensured to pass through the N-well 241 and the outside. The circuit is in contact and does not cause the potential at that location to float.
  • the deep N-well 235 is much deeper than the N-well 241, and the impurity concentration is much lighter.
  • This deep N-well 235 forms a diode with a P-type heavily doped region 266 and a P-type lightly doped region 256.
  • the breakdown voltage of the diode determines the maximum breakdown voltage of the P-LDM0S.
  • the output capacitance of the P-LDM0S is also mainly derived from the junction capacitance of the above diode. The lower the impurity concentration of the deep N-type well, the deeper the depth, the smaller the junction capacitance.
  • the N-well 241 saves a mask like the N-well in the standard PMOS process.
  • the minimum gate line width of the P-LDM0S can be made the same or very close to the PM0S.
  • the final gate minimum linewidth is determined by the Zener Through voltage of the channel. Since the impurity concentration of the N-type well 241 is generally 10 times higher than that of the deep N-type well 235, and the impurity concentration of the P-LDM0S lightly doped region 256 is lower and thinner, the majority of the reverse voltage drop is lowered. Doped region 256.
  • the minimum line width of the P-LDM0S gate can be the same as or very close to the minimum line width of the PM0S gate without causing Zener breakdown of the channel portion.
  • the minimum line width of the gate is much longer than the corresponding PM0S.
  • the P-LDM0 in the present invention can be made small by the minimum gate line width, which not only reduces the channel resistance, but also reduces the capacitance of the gate 270 to the N-type well 241, and can also be achieved by the deep well 235.
  • the impurity concentration is very low and deep, which not only increases the drain-to-base/source breakdown voltage, but also reduces the drain-to-base/source capacitance.
  • the deep P-well 236 and the P-well 242 of the N-LDMOS in FIG. 14 use different masks for horizontal positioning.
  • the deep P-well 236 is shown in the figure and the P-well 242 is fully packaged from side to side. In fact, it is not necessary to have a full package. Only the deep P-type well 236 and the P-type well 242 may be connected. In this case, the potential of the deep P-type well 236 is ensured to be in contact with the external circuit through the P-well 242, so that the potential is not made to float.
  • the deep P-well 236 is much deeper than the P-well 242, and the impurity concentration is much lighter.
  • This deep P-type well 236 forms a diode with an N-type heavily doped region 267 and an N-type lightly doped region 257.
  • the breakdown voltage of the diode determines the maximum breakdown voltage of the N-LDM0S.
  • the output capacitance of the N-LDM0S is also mainly derived from the junction capacitance of the above diode. The lower the impurity concentration of the deep P-type well, the deeper the depth, the smaller the junction capacitance.
  • the P-well 242 like the P-well in the standard OS process, saves a mask.
  • the minimum gate line width of the N-LDM0S can be made to be very close to the OS.
  • the final gate minimum line width is determined by the Zener breakdown voltage of the channel. Since the impurity concentration of the P-type well 242 is generally 10 times higher than that of the deep P-type well 236, and the impurity concentration of the N-LDM0S lightly doped region 257 is lower and thinner than that of the doped region 267, most of the reverse voltage drop will be reduced to light. Doped region 257.
  • the minimum line width of the N-LDM0S gate can be the same as or very close to the minimum line width of the gate of the NMOS OS without causing Zener breakdown of the channel portion.
  • the minimum line width of the gate is much longer than the corresponding NMOS.
  • the N-LDM0 in the present invention can be made small due to the minimum gate line width, which not only reduces the channel resistance, but also reduces the capacitance of the gate 270 to the N-well 242, and can also be achieved by the deep well 236.
  • the impurity concentration is very low and deep, which not only increases the drain to the base/source The voltage is applied and the drain to base/source capacitance is reduced.
  • the epitaxial layer is P-type doped
  • the P-type well of the N-LDM0S is also P-type doped
  • the entire N-LDM0S is short-circuited with other devices on the same epitaxial layer through the P-type epitaxial layer/P-type well.
  • the N-LDM0S can be isolated from the epitaxial layer 222 by the deep N-well 231 and the buried layer 221 as in FIG. If the substrate 211 is N-type, the buried layer 221 may not be required to directly diffuse the deep N-type well to the N-type substrate 211.
  • Figure 15 shows another implementation of such a device.
  • the principle and advantages of the device are the same as those of the device of Figure 14 above.
  • the epitaxial layer 223 is of the N-type
  • the deep N-type well 235 and the N-type well 241 are both N-type
  • the P-LDM0S is made to communicate with other devices on the same epitaxial layer through the epitaxial layer 223.
  • P-LDM0S is sometimes isolated from other devices, P-LDM0S can be isolated from epitaxial layer 222 by deep P-well 232 and P-type buried layer 224 as shown in FIG.
  • the P-type buried layer 224 may not be required, and the deep P-type well 232 may be directly diffused to be in contact with the P-type substrate 211.
  • the device works as above. Since the epitaxial layer 223 is N-type, the deep N-well 235 can be an N-type epitaxial layer 223 to save a mask layer.
  • the deep P-well 232 can also utilize the same impurity fraction as the deep P-well 236 to save a mask layer.
  • Figure 16 shows another implementation of such a device.
  • the deep well 237 in the P-LDM0S is a P type instead of the N type in Fig. 14.
  • This P-type can be either a P-type well formed by P-type doping and a P-type well, or an epitaxial layer 222 can be used to save a mask layer.
  • the P-well 237 and the P-type heavily doped region 266 are connected to other devices on the same substrate through a P-type epitaxial layer. Sometimes it is necessary to isolate this device from other devices on the same substrate, this P-LDM0 should be isolated by the deep N-well 231 surrounding the P-well and the underlying N-type buried layer 221 as in Figure 16.
  • the impurity concentration of the P-well 237 is preferably as low as possible, and the P-well 237 is deeper than the N-well 241. Since the P-well 237 forms a diode with the underlying N-type buried layer 221, the breakdown voltage of this diode limits the breakdown voltage of the P-LDM0S. To increase the breakdown voltage of P-LDM0S, one is to reduce the impurity concentration of this P-type well, and the other is to increase the depth of this P-type well.
  • the concentration is determined by the epitaxial layer, and the depth can be selected by the thickness of the epitaxial layer without undue thermal diffusion process, which simplifies the process.
  • the N-well 241 can be made to have the same minimum line width as the minimum line width of the PM0S gate as in the case of FIG. 14, which not only reduces the channel resistance but also reduces the gate 270. The capacitance to the N-well 241.
  • the N-LDM0S in Fig. 16 is different from that in Fig. 14 in that the deep well 238 is of the N type instead of the P type of Fig. 14. Since the well 238 is already N-type and has been isolated from the P-type substrate, it is not necessary to take special measures to isolate the N-LDMOS from the outside as in FIG. To save a mask, the N-well 238 can have the same impurity concentration profile as the deep N-well 231 isolated from P-LDMOS in FIG.
  • the N-well 238 forms a diode with the underlying P epitaxial layer 222 and the P substrate 211, in order to enhance this
  • the breakdown voltage of the N-LDMOS the deeper the N-type well 238 is, the lower the impurity concentration is, the better.
  • the P-well 242 can be made to have the same minimum line width as the minimum line width of the NM0S gate as in the case of FIG. 14, which not only reduces the channel resistance but also reduces the gate 270.
  • Figure 17 shows the implementation of the device of Figure 16 on an N-type epitaxial layer.
  • epitaxial layer 223 is N-type
  • deep P-well 237 isolates P-LDMOS from surrounding devices.
  • the deeper P-type well is deeper and better, and the doping concentration is as low as possible.
  • the N-LDM0S deep N-well 238 and the N-type heavily doped region 267 are both N-type such that the source/drain of the N-LDMOS is connected to other devices through the epitaxial layer 223.
  • the N-LDM0S requires isolation, as shown in Figure 17, the N-LDM0S can be isolated by the deep P-well 232 and the underlying P-type buried layer 224.
  • the N-LDM0S can be isolated by directly diffusing the deep P-type well into contact with the P-type substrate.
  • the deep N-type well 238 may employ an N-type epitaxial layer 223.
  • the P-LDM0S and N-LDM0S shown in Figures 14 through 17 above are both unilaterally high voltage (usually the drain is high voltage) and the other side is low voltage.
  • the source and drain of P-LDM0S and N-LDM0S can withstand high voltage at the same time, so that only the high-voltage structure of the source/drain in the figure should be copied to the source/drain on the other side.
  • Such a device will be a source.
  • Both the pole and the drain can withstand high voltage symmetrical components.
  • the device shown in Figure 14 becomes a symmetrical device structure in which both the source and the drain can withstand high voltage as shown in Fig. 18. Symmetrical device structures that can withstand high voltages, both source and drain, corresponding to Figures 15, 16, and 17 are not shown here.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un LDMOS, lequel comprend un canal sur la surface d'un substrat semi-conducteur, une électrode de grille par-dessus le canal et une source ou un drain ayant une région fortement dopée et une région faiblement dopée qui est au voisinage proche du canal et de la région fortement dopée. Le LDMOS comprend également un puits dopé inversement avec un type de dopant contraire à celui de la source ou du drain et une région dopée inversement avec un type de dopant contraire à celui de la source ou du drain. Le puits dopé inversement est en dessous du canal et entoure le canal et la région dopée inversement est placée entre la région fortement dopée et le puits dopé inversement. L'invention concerne également un dispositif à semi-conducteur intégré à LDMOS et CMOS.
PCT/CN2008/072196 2007-08-31 2008-08-29 Ldmos et dispositif à semi-conducteur intégré à ldmos et cmos WO2009030165A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN2007101488347A CN101378075B (zh) 2007-08-31 2007-08-31 Ldmos及集成ldmos与cmos的半导体器件
CN200710148834.7 2007-08-31

Publications (1)

Publication Number Publication Date
WO2009030165A1 true WO2009030165A1 (fr) 2009-03-12

Family

ID=40421511

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2008/072196 WO2009030165A1 (fr) 2007-08-31 2008-08-29 Ldmos et dispositif à semi-conducteur intégré à ldmos et cmos

Country Status (2)

Country Link
CN (1) CN101378075B (fr)
WO (1) WO2009030165A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015117038A1 (fr) 2014-01-30 2015-08-06 Texas Instruments Incorporated Transistors intégrés monolithiques pour convertisseur abaisseur de tension
CN110581165A (zh) * 2018-06-07 2019-12-17 赛米控电子股份有限公司 包括半导体本体的二极管

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8138049B2 (en) * 2009-05-29 2012-03-20 Silergy Technology Fabrication of lateral double-diffused metal oxide semiconductor (LDMOS) devices
CN102354686A (zh) * 2011-11-17 2012-02-15 上海先进半导体制造股份有限公司 60v高边ldnmos结构及其制造方法
CN103632942B (zh) * 2012-08-24 2016-02-10 上海华虹宏力半导体制造有限公司 Cmos工艺中集成sonos器件和ldmos器件的方法
CN103730419B (zh) * 2012-10-12 2016-04-06 北大方正集团有限公司 一种阈值电压调节方法
US9502251B1 (en) * 2015-09-29 2016-11-22 Monolithic Power Systems, Inc. Method for fabricating low-cost isolated resurf LDMOS and associated BCD manufacturing process
JP6679908B2 (ja) * 2015-12-11 2020-04-15 セイコーエプソン株式会社 半導体装置及びその製造方法
JP6641958B2 (ja) * 2015-12-11 2020-02-05 セイコーエプソン株式会社 半導体装置及びその製造方法
CN107093625B (zh) * 2017-04-17 2021-06-04 上海华虹宏力半导体制造有限公司 双扩散漏nmos器件及制造方法
CN108493187B (zh) * 2018-03-30 2021-02-05 上海华力微电子有限公司 无回滞效应栅接地nmos静电防护半导体器件及其实现方法
CN111883484B (zh) * 2020-08-14 2023-10-20 上海华虹宏力半导体制造有限公司 开关ldmos器件的制造方法
CN112216745B (zh) * 2020-12-10 2021-03-09 北京芯可鉴科技有限公司 高压非对称结构ldmos器件及其制备方法
CN113451216B (zh) * 2021-06-28 2022-03-25 中国电子科技集团公司第二十四研究所 成套硅基抗辐射高压cmos器件集成结构及其制造方法
CN114420759A (zh) * 2022-02-23 2022-04-29 江苏帝奥微电子股份有限公司 一种集成过压保护二极管的nldmos器件

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0837509A1 (fr) * 1996-05-15 1998-04-22 Texas Instruments Incorporated Transistor LDMOS ayant une région RESURF autoalignée avec une région d'oxyde de champ de type LOCOS
CN1494742A (zh) * 2001-08-30 2004-05-05 ������������ʽ���� 半导体器件及其制造方法
US6825531B1 (en) * 2003-07-11 2004-11-30 Micrel, Incorporated Lateral DMOS transistor with a self-aligned drain region
US20060011981A1 (en) * 2004-07-15 2006-01-19 Samsung Electronis Co., Ltd. High frequency MOS transistor, method of forming the same, and method of manufacturing a semiconductor device including the same
US20060081836A1 (en) * 2004-10-14 2006-04-20 Yoshinobu Kimura Semiconductor device and method of manufacturing the same
US20060197149A1 (en) * 2005-03-07 2006-09-07 Keiji Fujimoto Semiconductor device and fabrication process thereof, and application thereof
US20070013008A1 (en) * 2005-07-13 2007-01-18 Shuming Xu Power LDMOS transistor

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0837509A1 (fr) * 1996-05-15 1998-04-22 Texas Instruments Incorporated Transistor LDMOS ayant une région RESURF autoalignée avec une région d'oxyde de champ de type LOCOS
CN1494742A (zh) * 2001-08-30 2004-05-05 ������������ʽ���� 半导体器件及其制造方法
US6825531B1 (en) * 2003-07-11 2004-11-30 Micrel, Incorporated Lateral DMOS transistor with a self-aligned drain region
US20060011981A1 (en) * 2004-07-15 2006-01-19 Samsung Electronis Co., Ltd. High frequency MOS transistor, method of forming the same, and method of manufacturing a semiconductor device including the same
US20060081836A1 (en) * 2004-10-14 2006-04-20 Yoshinobu Kimura Semiconductor device and method of manufacturing the same
US20060197149A1 (en) * 2005-03-07 2006-09-07 Keiji Fujimoto Semiconductor device and fabrication process thereof, and application thereof
US20070013008A1 (en) * 2005-07-13 2007-01-18 Shuming Xu Power LDMOS transistor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015117038A1 (fr) 2014-01-30 2015-08-06 Texas Instruments Incorporated Transistors intégrés monolithiques pour convertisseur abaisseur de tension
EP3127154A4 (fr) * 2014-01-30 2018-01-17 Texas Instruments Incorporated Transistors intégrés monolithiques pour convertisseur abaisseur de tension
CN110581165A (zh) * 2018-06-07 2019-12-17 赛米控电子股份有限公司 包括半导体本体的二极管
CN110581165B (zh) * 2018-06-07 2024-05-28 赛米控电子股份有限公司 包括半导体本体的二极管

Also Published As

Publication number Publication date
CN101378075B (zh) 2012-10-31
CN101378075A (zh) 2009-03-04

Similar Documents

Publication Publication Date Title
WO2009030165A1 (fr) Ldmos et dispositif à semi-conducteur intégré à ldmos et cmos
US6855581B2 (en) Method for fabricating a high-voltage high-power integrated circuit device
US9281395B2 (en) Semiconductor device and fabrication method thereof
US7575977B2 (en) Self-aligned LDMOS fabrication method integrated deep-sub-micron VLSI process, using a self-aligned lithography etches and implant process
US6660603B2 (en) Higher voltage drain extended MOS transistors with self-aligned channel and drain extensions
US6514810B1 (en) Buried channel PMOS transistor in dual gate CMOS with reduced masking steps
JP3523056B2 (ja) 半導体装置
EP0178649A2 (fr) Dispositif semi-conducteur complémentaire
KR101531882B1 (ko) 반도체 소자 및 그 제조 방법
US20100163990A1 (en) Lateral Double Diffused Metal Oxide Semiconductor Device
JP2005167252A (ja) 集積回路構造体
JPH04276653A (ja) 集積回路デバイスの製造プロセス
CN116487381A (zh) 中高压mos器件及其版图结构和制造方法
KR19980020943A (ko) 절연막 터널링 트랜지스터 및 그 제조방법
TWI793660B (zh) 半導體元件及其製造方法
KR100240682B1 (ko) 반도체장치의 제조방법
KR100840659B1 (ko) 디이모스 소자의 제조 방법
JP4146121B2 (ja) 半導体装置の製造方法
JPH10163338A (ja) 半導体装置とその製造方法
CN100466257C (zh) Cmos半导体器件
KR100385858B1 (ko) 트렌치 드레인 필드판을 갖는 전력소자
JP2002170890A (ja) 半導体装置
US5528066A (en) Bipolar transistor having a collector well with a particular concentration
JP2544438B2 (ja) 半導体装置およびその製造方法
KR100674647B1 (ko) 고전압용 반도체 소자의 제조 방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08800708

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 08800708

Country of ref document: EP

Kind code of ref document: A1

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载