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WO2009028353A1 - Registre à décalage, pilote d'affichage et affichage - Google Patents

Registre à décalage, pilote d'affichage et affichage Download PDF

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Publication number
WO2009028353A1
WO2009028353A1 PCT/JP2008/064763 JP2008064763W WO2009028353A1 WO 2009028353 A1 WO2009028353 A1 WO 2009028353A1 JP 2008064763 W JP2008064763 W JP 2008064763W WO 2009028353 A1 WO2009028353 A1 WO 2009028353A1
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WO
WIPO (PCT)
Prior art keywords
stage
output
shift register
stages
mode
Prior art date
Application number
PCT/JP2008/064763
Other languages
English (en)
Inventor
Gareth John
Patrick Zebedee
Original Assignee
Sharp Kabushiki Kaisha
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Kabushiki Kaisha filed Critical Sharp Kabushiki Kaisha
Publication of WO2009028353A1 publication Critical patent/WO2009028353A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/04—Partial updating of the display screen

Definitions

  • the present invention relates to a shift register and to a display driver and a display including such a shift register.
  • Such a shift register may be used, for example , as or in a clock generator for driving the rows and / or columns of an active matrix display.
  • FIG. 1 of the accompanying drawings shows a typical active matrix display.
  • Such a display is made up of a matrix 2 of picture elements (pixels) , arranged in M rows and N columns . Each row and column is connected to an electrode, with the column electrodes being connected to the N outputs of a data driver 4 and the row electrodes being connected to the M outputs of a scan driver 6.
  • the pixels are addressed one row at a time .
  • the scan driver includes an M-phase clock generator, which produces a series of clock pulses as shown in Figure 2 of the accompanying drawings.
  • Each clock pulse OUTi controls the activation of row i. It is usual for the pulses to be non- overlapping, such that no two pulses are high at the same time .
  • the data driver may also include a B-phase clock generator of the type described, such that each clock pulse OUTi activates block i.
  • a full screen refresh requires all rows to be activated in turn .
  • the time taken for a partial image refresh is the same for a full screen refresh.
  • Rows X to Y in Figure 3 can therefore each be charged for longer than each row in a full screen refresh. This reduces power consumption.
  • a full screen refresh requires each row to be activated at a higher rate .
  • Scan drivers of the type described may be formed directly on the display substrate , reducing the number of connections required to the display. This is advantageous, since it reduces the area occupied by the connector and leads to a display which is more mechanically robust.
  • the circuit may be composed of only n-type transistors rather than a mixture of n- and p-type transistors as commonly used in CMOS circuits .
  • the use of a single type of transistor is advantageous for manufacturing cost.
  • a clock generator for use in a scan driver may be formed from a shift register.
  • US7 145545 describes such a shift register. In this case, all rows are activated simultaneously to pre-charge all data lines to some intermediate data value , as shown in Figure 4 of the accompanying drawings .
  • a start pulse and the simultaneous rise of three clock signals , CK l - CK3 initiate all-on.
  • the scan driver comprises of a number of shift register stages , 32. Each stage has three inputs: R, S and CK.
  • the CK inputs of odd-number stages are connected to a first clock, CK l ; the CK inputs of even-number stages are connected to a second clock, CK2.
  • Figure 6 shows the composition of two stages, 32 , in Figure 5.
  • the circuit is composed of only n-type transistors .
  • Each shift register stage 32 is composed of a control logic block, 14 , and an output stage, 15.
  • Figure 7 of the accompanying drawings illustrates the operation of the scan driver of Figure 6.
  • QN represents the Q output of the control logic block, 14 , of stage N;
  • GOUTN represents the output of the output stage, 1 5 , of stage N , which also forms the output of the scan driver.
  • stage N is set, QN rises to a high logic level, and its output stage , 1 5 , passes the clock to the output.
  • stage N+ l is configured to pass the complement of the clock to its output, so the output initially remains low.
  • the output stage used is common in such circuits: it is composed of two transistors, 10 and 12 , and a bootstrap capacitor, 13. The transistors are controlled by the logic, such that exactly one transistor is activated at any time .
  • the first transistor, 10, passes the clock directly to the output, with no additional logic or buffering; the second, 12 , pulls the output to a low supply voltage Voff.
  • the voltage at the source of an n-type transistor is normally no higher than VG - VTH , where VG is the gate voltage of the transistor and VTH is the threshold of the transistor.
  • the output of the logic, which supplies VG to the output switches is, in turn, no higher than Von, the high supply voltage , and is commonly no higher than Von - VTH , for similar reasons (it is generated by a transistor whose gate voltage is no higher than Von) . It is preferable to pass the full voltage of the clock to the output (otherwise, it would be necessary to increase the voltage of the clock, which leads to higher power consumption) .
  • the bootstrap capacitor, 13 acts to increase the gate voltage of the first transistor when the clock rises . Its operation is as follows : the gate voltage of transistor 10 is raised by the logic to a point where it conducts ; when the clock rises, the rise is conducted to the output; this rise is coupled to the gate of transistor 10 by the capacitor 13 , increasing the gate voltage, and ensuring that transistor 10 continues to conduct until its source and drain voltages are substantially equal.
  • a disadvantage of the circuit in Figure 6 is that stages will attempt to set and reset simultaneously when all outputs are activated . In this case, the logic will fail.
  • the scan driver output may be connected to a substantial capacitive load. It is difficult to design low power single-channel OR gates capable of driving such loads at sufficient speed.
  • a shift register comprising a plurality of stages arranged to be activated in sequence during a first mode of operation, each stage comprising a logic circuit controlling a first output circuit, each of the first output circuits of at least some of the stages comprising a first switch, which connects an output of the stage to an active signal first input of the stage when the stage is active , and a second switch, which, when the stage is inactive, connects the stage output to a second input of the stage for receiving an inactive signal level during the first mode and the active signal level during a second mode of operation for activating the stage outputs of the at least some stages simultaneously.
  • the first and second switches may comprise first and second transistors, respectively. At least one of the first and second transistors may be provided with a bootstrap capacitor.
  • Each of the logic circuits may comprise a reset- set flip- flop .
  • Each of the flip-flops may comprise a reset-over-set flip- flop .
  • the stage output of each stage may be connected to a reset or set input of at least one adjacent stage.
  • each of the at least some stages may have a second output circuit for supplying a reset or set signal at a further output connected to a reset or set input of at least one adjacent stage.
  • Each second output circuit may be connected between the stage output and the further output.
  • Each second output circuit may comprise a third switch connected between the stage output and the further output and arranged to be switched on during the first mode and switched off during the second mode .
  • the third switch may comprise a third transistor.
  • the third transistor may be provided with a further bootstrap capacitor.
  • Each second output circuit may comprise a fourth switch arranged to connect the further output to receive the inactive signal level during the second mode .
  • the fourth switch may comprise a fourth transistor.
  • Each second output circuit may comprise a third switch arranged to connect the further output to an active signal third input of the stage when the stage is active .
  • the third switch may comprise a third transistor.
  • the third transistor may be provided with a further bootstrap capacitor.
  • Each second output circuit may comprise a fourth switch arranged to connect the further output to receive the inactive signal level when the stage is inactive.
  • the fourth switch may comprise a fourth transistor.
  • the first inputs of at least some of the stages may be connected to at least one clock input of the register.
  • the first inputs of at least some of the stages may be connected to at least one pulse width control input of the register for receiving at least one pulse width control signal for determining which of the stages is enabled .
  • the at least some stages may be consecutive.
  • the shift register may comprise a control circuit for supplying to the second inputs the inactive signal level during the first mode and the active signal level during the second mode .
  • Each of the first output circuits of at least some others of the stages may comprise a first switch, which connects an output of the stage to an active signal first input of the stage when the stage is active, and a second switch, which, when the stage is inactive , connects the stage output to a further input of the stage for receiving an inactive signal level during the first mode and the active signal level during a third mode of operation for activating the stage outputs of the at least some other stages simultaneously.
  • the second and third modes may be selectable simultaneously.
  • the shift register may comprise a further control circuit for supplying to the further inputs the inactive signal level during the first mode and the active signal level during the third mode.
  • a display driver comprising a shift register according to the first aspect of the invention.
  • an active matrix display including a display driver according to the second aspect of the invention.
  • the display may comprise a liquid crystal display. It is thus possible to provide an arrangement which provides an "all-on” or “partial all-on” function in a relatively simple and elegant way. For example , an existing arrangement may be used with minimal alteration to its circuit, resulting in minimal change in production yield and cost.
  • Figure 1 is a block diagram illustrating a known type of active matrix display
  • Figure 2 is a waveform diagram illustrating output pulses of a typical scan driver of the display in Figure 1 ;
  • Figure 3 is a waveform diagram illustrating scan driver output pulses in a partial mode of operation
  • Figure 4 is a waveform diagram illustrating known scan driver output pulses during pre-charge ;
  • Figures 5 and 6 are block schematic diagrams of known types of scan driver;
  • Figure 7 is a waveform diagram illustrating the operation of the circuit in Figure 6 ;
  • FIGS 8 and 9 are block schematic diagrams of known types of scan driver
  • Figure 10 is a waveform diagram illustrating the operation of the circuit in Figure 9 during all-on operation
  • Figure 1 1 is a block schematic diagram of a multiple- stage scan driver constituting an embodiment of the invention
  • Figure 12 is a block schematic diagram of one of the stages of Figure 1 1 ;
  • Figure 13 is a waveform diagram illustrating the operation of the circuit in Figure 12 during all-on operation;
  • Figure 14 is a block schematic diagram of one of the stages of Figure 1 1 , constituting another embodiment of the invention;
  • Figure 15 is a block schematic diagram of one of the stages of Figure 1 1 , constituting another embodiment of the invention.
  • Figure 16 is a block schematic diagram of a multiple- stage scan driver constituting another embodiment of the invention.
  • Figure 17 is a block schematic diagram of one of the stages of Figure 16 ;
  • Figure 18 is a block schematic diagram of one of the stages of Figure 16, constituting another embodiment of the invention;
  • Figure 19 is a waveform diagram illustrating the operation of the circuit in Figure 18 during all-on operation
  • Figure 20 is a block schematic diagram of a multiple- stage scan driver constituting another embodiment of the invention.
  • Figure 2 1 is a block schematic diagram of one of the stages of Figure 20, constituting another embodiment of the invention.
  • Figure 22 is a waveform diagram illustrating the operation of the circuit in Figure 2 1 during all-on operation
  • Figure 23 is a block schematic diagram of one of the stages of Figure 20 , constituting another embodiment of the invention.
  • Figure 24 is a block schematic diagram of a multiple- stage scan driver constituting another embodiment of the invention.
  • Figure 25 is a waveform diagram illustrating the operation of the circuit in Figure 24 during a partial mode of operation;
  • Figures 26 and 27 are block schematic diagrams of the stages of Figure 24 , constituting another embodiment of the invention.
  • Figure 28 is a block schematic diagram of a multiple- stage scan driver constituting another embodiment of the invention;
  • Figure 29 is a waveform diagram illustrating the operation of the circuit in Figure 28;
  • Figure 30 is a block schematic diagram of a multiple- stage scan driver constituting another embodiment of the invention.
  • Figure 3 1 is a waveform diagram illustrating the operation of the circuit in Figure 30 during a partial mode of operation.
  • Figure 32 is a waveform diagram illustrating the operation of the circuit in Figure 30 during a partial mode of operation.
  • a first embodiment is shown in Figures 1 1 to 14 and comprises a scan driver in the form of a shift register composed of a plurality of stages, 42.
  • Each stage has four inputs: a reset input (R) , a set input (S) , a clock input (CK) , and an "all on” input (ALLON) .
  • the CK inputs of odd-number stages are connected to a first clock, CK l ; the CK inputs of even-number stages are connected to a second clock, CK2.
  • the clocks are preferably non-overlapping, such that the scan driver outputs are non-overlapping.
  • the clocks may also be complementary, such that the scan driver outputs have coincident edges.
  • the ALLON inputs of all stages are connected to a signal ALLON.
  • Each stage has an output GL.
  • the GL output of each stage forms an output of the driver, GLi, and is connected to the S input of the succeeding (adj acent) stage and the R input of the preceding (adjacent) stage .
  • Figure 12 shows the composition of one stage, 42 , of Figure 1 1 .
  • Each stage is composed of a logic circuit, 34 , and a first output circuit shown as “output switches” and comprising first and second switches 36, 38.
  • the logic circuit has two inputs, S and R, which are connected to the S and R inputs of the stage, respectively, and two outputs Q and QB .
  • the Q output is high when the logic circuit is activated and low when it is deactivated; the QB output is the complement of Q .
  • the logic circuit may be embodied as a reset-over-set flip-flop (an RS flip-flop in which the logic will reset when set, S, and reset, R, inputs are active simultaneously) .
  • the Q output of the logic circuit 34 is connected to the control terminal of the first switch 36 ; the QB output is connected to the control terminal of the second switch 38.
  • the first switch 36 is connected such that its principal conduction path is between the CK input, constituting an active signal first input, and the GL output; the second switch 38 is connected such that its principal conduction path is between the ALLON input and the GL output.
  • the ALLON input constitutes a second input which receives an inactive signal level during a first mode, during which the stages are arranged to be activated in sequence, and an active signal level during a second mode, during which the stage outputs of at least some of the stages are active simultaneously. The at least some stages may be consecutive .
  • the second inputs are connected to a control circuit (not shown) for supplying the active and inactive signal levels .
  • the operation of the circuit is similar to that disclosed in US7038653.
  • the GL outputs are now pulled down to ALLON instead of a low supply voltage .
  • ALLON is inactive and held at a low voltage .
  • ALLON is active , all GL outputs are active simultaneously.
  • Figure 14 shows a transistor-level embodiment of the stage of Figure 12. The connections between the stages are as shown in Figure 1 1 .
  • the scan driver is composed of n-type transistors only.
  • Each stage is composed of a logic circuit, 44 , first and second transistors 56 , 58 , and two bootstrap capacitors 64 , 74.
  • the logic circuit has two inputs, S and R, which are connected to the S and R inputs of the stage, respectively, and two outputs Q and QB .
  • the Q output is high when the logic circuit is activated and low when it is deactivated; the QB output is the complement of Q .
  • the logic circuit may be of the form, 14 , shown in Figure 8.
  • the Q output of the logic circuit is connected to the control terminal of the first transistor 56; the QB output is connected to the control terminal of the second transistor 58.
  • the first transistor 56 is connected such that its principal conduction path is between the CK input and the GL output; the second transistor 58 is connected such that its principal conduction path is between the ALLON input and the GL output.
  • the bootstrap capacitor 64 is connected between the GL output and the Q output of the logic circuit, and serves to ensure the voltage on the control electrode of the transistor
  • the bootstrap capacitor 74 is connected between the GL output and the QB output of the logic circuit. As before, this serves to ensure the voltage on the control electrode of transistor 58 is boosted to a level sufficient for the high level of ALLON to conduct fully to the GL output. However, it is also possible to connect the bootstrap capacitor between the ALLON input and the QB output of the logic circuit, as shown in Figure 15.
  • the second and third embodiments concern isolating the GL outputs from the logic circuits of the succeeding and preceding stages when ALLON is active .
  • the second embodiment is shown in Figures 16 and 1 7.
  • the scan driver is composed of a number of stages, 52. Each stage has five inputs : R, S , CK, ALLON and ALLONB .
  • the CK inputs of odd-number stages are connected to a first clock,
  • CK l the CK inputs of even-number stages are connected to a second clock, CK2.
  • the ALLON and ALLONB inputs of all stages are connected to the ALLON and ALLONB inputs of the scan driver, respectively.
  • Each stage has first and second output circuits providing an output and a further output, GL and OUT, respectively.
  • the GL output of each stage forms an output of the driver, GLi; the OUT output of each stage is connected to the S input of the succeeding (adj acent) stage and the R input of the preceding (adjacent) stage .
  • FIG 17 shows the composition of one stage, 52 , of Figure 16. Each stage is similar to that shown in Figure 12 and only the differences will be described.
  • the ALLON input is connected to the control terminal of a fourth switch 42 ; the complement of ALLON, ALLONB , is connected to the control terminal of a third switch 40.
  • the third switch 40 is connected such that its principal conduction path is between the GL output and the OUT output; the fourth switch 42 is connected such that its principal conduction path is between the OUT output and a low supply voltage Vss constituting an inactive signal level.
  • the switches 40, 42 are connected such that the OUT output is pulled down to the low supply voltage Vss when ALLON is active.
  • the third switch 40 is switched on during the first mode and off during the second mode .
  • the third switch 40 connects the further output to an active signal third input of the stage when the stage is active .
  • Figure 1 8 shows a transistor-level embodiment of the stage of Figure 1 7. Each stage is similar to that shown in
  • the logic circuit may be of the form, 14 , shown in Figure 6.
  • the ALLON input is connected to the control terminal of a fourth transistor 22 ; the complement of ALLON, ALLONB, is connected to the control terminal of a third transistor 50.
  • the third Transistor 50 is connected such that its principal conduction path is between the GL output and the OUT output; the fourth transistor 22 is connected such that its principal conduction path is between the OUT output and the low supply voltage Vss.
  • the transistors 56 and 58 therefore form the output switches; the transistors 50 and 22 form the logic switches.
  • a further bootstrap capacitor, 54 is connected between the ALLONB input and the OUT output and operates as previously described.
  • Figure 19 shows the timing for the signals in Figure 18.
  • FIGS 20 and 2 1 show an embodiment with the CK input connected to the control terminal of the third transistor 50.
  • the scan driver is composed of a number of stages, 62. Each stage has four inputs: R, S , CK and ALLON .
  • the CK inputs of odd-number stages are connected to a first clock, CK l ; the CK inputs of even-number stages are connected to a second clock, CK2.
  • the ALLON inputs of all stages are connected to the ALLON input of the scan driver.
  • Figure 22 shows the timing for the signals in Figure 2 1 .
  • ALLON is active
  • CK 1 and CK2 are both inactive
  • the OUT output is pulled down to a low supply voltage .
  • ALLON is inactive , the GL and OUT outputs are connected when the CK input is active. In this way, the OUT output is maintained inactive .
  • FIG. 23 represents another composition of one stage, 62 , of Figure 20.
  • the arrangement shown in Figure 23 differs from that shown in Figure 2 1 in that the transistors 50 and 22 are replaced by transistors 80 and 82 , whose main conduction paths are connected in series between the clock input CK and the low or "negative" power supply line Vss.
  • the gates of the transistors 80 and 82 are connected to the Q and QB outputs, respectively, of the logic circuit 44.
  • the source of the transistor 80 and the drain of the transistor 82 are connected to the output OUT, which is connected via a bootstrap capacitor 84 to the gate of the transistor 80.
  • the stage shown in Figure 23 thus has a first output circuit including the transistors 46 and 48 for providing the stage output GL and a second output circuit including the transistors 80 and 82 for providing the output OUT, which is used to reset the preceding stage and to set the succeeding stage .
  • the load presented, for example by each scan line and the pixels connected to it, to the stage output GL is typically relatively capacitive and this affects the rising and falling edges of the stage output signals at the stage output GL.
  • the presence of the second output circuit prevents the resetting of the preceding stage and the setting of the succeeding stage from being affected by the capacitive load.
  • Fourth and fifth embodiments allow only some , for example nearly all, of the outputs of a scan driver to be activated simultaneously ('partial-on') , for example when the display is in partial mode and showing a stand-by image on a limited number of rows.
  • Figure 24 shows a scan driver with PARTIALON and pulse width control, PWC , input signals.
  • the scan driver is composed of two types of stage; stages connected to the rows of the partial image (rows X to Y) , 32 , and all other stages, 72. Stages 32 have three inputs : R, S and CK; stages 72 have five inputs: R, S, CK, PARTIALON and PWC .
  • the CK inputs of odd-number stages are connected to a first clock, CK l ; the CK inputs of even-number stages are connected to a second clock, CK2.
  • the PARTIALON and PWC inputs of stages are connected to the PARTIALON and PWC inputs of the scan driver, respectively.
  • Figure 25 shows that all rows except rows X to Y are activated simultaneously when PARTIALON is activated.
  • Pulse width control may be used to select, control or vary the widths of the pulses provided at the GL outputs. Pulses of selected, controlled or varied width synchronised to the clock pulses are supplied to the shift register PWC input and are passed to the GL outputs of the stages 72 in turn during the first mode.
  • the clock pulses supplied to the outputs OUT are used to set and reset the adj acent stages so that such setting and resetting are not affected by pulse width control .
  • Figure 26 shows a transistor-level embodiment of a stage, 72 , in Figure 24. This stage is similar to that shown in Figure 23.
  • Transistor 58 is connected such that its principal conduction path is between the GL output and the PARTIALON input signal; transistor 56 is connected such that its principal conduction path is between the PWC input and the GL output.
  • the input PWC constitutes the first input and receives at least one pulse width control signal for determining which of the stages is enabled.
  • Figure 27 shows a stage , 32 , in Figure 24. This stage is similar to that shown in Figure 14 , except transistor 58 is connected such that its principal conduction path is between the GL output and the low supply voltage Vss.
  • FIG. 28 shows a scan driver similar to Figure 24 and only the differences will be described.
  • Stages 62 have four inputs: R, S , CK and ALLON .
  • the ALLON inputs of stages are connected to the ALLON input of the scan driver.
  • Figures 23 and 26 show transistor-level embodiments of stages 62 and 72 respectively.
  • Figure 29 shows the waveforms for signals in Figure 28. This is similar to Figure 25 ; an all-on capability has been added by simultaneously activating ALLON and PARTIALON .
  • the ALLON inputs of the stages 62 constitute further inputs which receive an inactive signal level during the first mode and the active signal during a third mode of operation for activating the outputs of the stages 62 simultaneously.
  • the active and inactive signal levels may be supplied by a further control circuit (not shown) .
  • the second and third modes are selectable simultaneously so as to provide all-on capability of all the stages 62 and 72.
  • the partial-on mode corresponds to selecting only the second mode .
  • FIG. 30 shows a scan driver similar to Figure 28 and only the differences will be explained.
  • the PARTIALON of odd-number stages outside rows X to Y are connected to a first PARTIALON signal, PARTIALON 1 ; the PARTIALON inputs of even-number stages outside rows X to Y are connected to a second PARTIALON signal, PARTIALON2.
  • FIG 3 1 This shows the waveforms of signals in Figure 30.
  • the polarity of the liquid crystal drive voltage corresponds to an alternating voltage , VCOM . Odd rows outside rows X to Y are activated in one frame; even rows are activated in the next frame when VCOM is reversed. In this way, the polarity of the drive voltage for each row is reversed during alternate frames.
  • Figure 32 operation of a seventh embodiment is illustrated in Figure 32.
  • the advantage of the sixth and seventh embodiments is that a full refresh is no longer required, thus reducing power consumption .

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
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  • Shift Register Type Memory (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

La présente invention concerne un registre à décalage comprenant une pluralité d'étages (42) qui sont activés séquentiellement durant un premier mode de fonctionnement pour activer leurs sorties (GL) tour à tour. Chaque étage (42) comprend un circuit logique (34) qui commande un circuit de sortie. Ce circuit logique (34) comprend en particulier une bascule à déclenchement prioritaire. Chacun des circuits de sortie de l'ensemble ou d'une partie des étages (42) comprend des premier et second commutateurs (36, 38), comprenant par exemple des transistors. Le premier commutateur (36) connecte la sortie (GL) de l'étage pour recevoir un niveau de signal actif, tel qu'un signal d'horloge (CK), lorsque l'étage est actif. Le second commutateur (38) connecte la sortie (GL) à une entrée (ALLON) lorsque l'étage (42) est inactif. L'entrée (ALLON) reçoit un niveau de signal inactif durant le premier mode de fonctionnement. Durant un second mode de fonctionnement destiné à assurer une fonction de type « tout-actif » (« all-on »), l'entrée (ALLON) reçoit le niveau de signal actif.
PCT/JP2008/064763 2007-08-30 2008-08-13 Registre à décalage, pilote d'affichage et affichage WO2009028353A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0716753A GB2452278A (en) 2007-08-30 2007-08-30 A scan pulse shift register for an active matrix LCD display
GB0716753.9 2007-08-30

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WO2009028353A1 true WO2009028353A1 (fr) 2009-03-05

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Cited By (12)

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