+

WO2009026998A2 - Connection of a chip comprising pads and bumps to a substrate comprising metallic strip conductors - Google Patents

Connection of a chip comprising pads and bumps to a substrate comprising metallic strip conductors Download PDF

Info

Publication number
WO2009026998A2
WO2009026998A2 PCT/EP2008/006011 EP2008006011W WO2009026998A2 WO 2009026998 A2 WO2009026998 A2 WO 2009026998A2 EP 2008006011 W EP2008006011 W EP 2008006011W WO 2009026998 A2 WO2009026998 A2 WO 2009026998A2
Authority
WO
WIPO (PCT)
Prior art keywords
chip
connection
substrate
compound according
conductor
Prior art date
Application number
PCT/EP2008/006011
Other languages
German (de)
French (fr)
Other versions
WO2009026998A3 (en
Inventor
Roger Wyss
Original Assignee
Att Technology Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Att Technology Gmbh filed Critical Att Technology Gmbh
Publication of WO2009026998A2 publication Critical patent/WO2009026998A2/en
Publication of WO2009026998A3 publication Critical patent/WO2009026998A3/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/0775Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05568Disposition the whole external layer protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48455Details of wedge bonds
    • H01L2224/48456Shape
    • H01L2224/48458Shape of the interface with the bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48507Material at the bonding interface comprising an intermetallic compound
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0102Calcium [Ca]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01327Intermediate phases, i.e. intermetallics compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Definitions

  • the invention relates to a compound according to the preamble of claim 1.
  • connections in an RF chip or an electronic component with pads or bumps are provided with substrate equipped with metallic tracks, which are suitable for radiofrequency based transponder textile labels, transponder-the-TAG, transponder smart card, transponder inlays, chip modules and others similar IC circuits are used in superior quality.
  • frequency ranges from 1 to 3000 megahertz are provided.
  • Smart cards can be functioning transponders and consist of chip modules and antennas.
  • a chip module consists of at least one chip on a conductor track with an antenna connection.
  • Document EP-A-0 706 152 shows a solution for the construction of smart cards using a substrate with metallic wiring pattern layer (antenna) with chip bonded thereto in conventional bonding technique (US 6,259,408). Another chip-cut substrate is punched over the chip in chip thickness to accommodate the chip, followed by another two films. This is a very complex working process, which places the highest demands on the centering process (indexing of the foils) and on the gluing. The use of multiple substrate layers gives this solution a relatively large thickness, making it very stiff (undesirable in inlets and card making). Due to the above-mentioned problems and requirements, this solution is very costly and not suitable for economical use in environments with increased load and where card flexibility and card quality are required.
  • connection quality Due to the very small dimensions of the chips, the connecting surfaces / bump and the printed conductors, which lie in the micrometer range, the smallest unevenness and tolerances have a negative effect on the connection quality. The required quality is difficult to control and maintain. The profitability of the manufacturing process is thereby enormously impaired.
  • RFID Radio Frequency Identification
  • Such labels must e.g. also be suitable for cooking linen. Due to the moisture, the aforementioned conventional connection of the pads and bumps suffers from the corresponding traces. The plastic / adhesive surrounding the pads / bumps swells and can lift the connection feet by a few nanometers, resulting in a connection interruption. Due to the high temperature of the cooking laundry, thermal expansions are generated in the materials involved, which in turn generate the smallest displacements in the connection and also cause connection interruptions.
  • interconnects and the individual joints are very close to each other (distance about 100 microns) and are not limited, there is also a risk of short circuit on the conductive connection means of the adjacent joints.
  • the process of attaching the globtop is very difficult to control because, on the one hand, the droplet on the carrier, because it is not guided, widens, and on the other hand, contamination is created on both sides of the chipcard module, which can only be removed with difficulty. Furthermore, there is no guarantee that the thin, sensitive wire will actually lie inside the globtop dome, because the dome is lowered uncontrollably due to widening on the support surface.
  • the conductor track structure is prepared by punching before connecting the chip to the conductor track. Due to the many delicate process steps, the production costs for chip cards of this type are high. For these reasons, the design is not suitable for producing high-stress, high-quality and low-cost connections between microchip and interconnect structures on a polymer or leadframe laminate for use in harsh environments, for example for the production of transponders.
  • the document DE-A-195 00 925 shows another method for the production of smart cards.
  • the chip card for contactless data transmission has various steps and elements, According to this method, the separately molded or stamped plastic card body with the following openings: a) a separately finished manufactured transmission module is attached, which is an antenna in the form of at least one coil and / or in Has form of electrically conductive layers.
  • the separately finished transmission module consists of a single metallic printed circuit board (Lead) or can be combined in a special application applied to a carrier body made of plastic.
  • the transmission module has connection surfaces for electrical connection to the connection surfaces of the chip module through openings in the card body.
  • This intermediate product (card body with embedded transmission module without expensive chip module) can now optionally be printed and then visually inspected according to committee criteria. c) A separately finished chip module with chip and on carrier mounted connecting tracks. d) Subsequent connection of the positions a and b and finally the assembly and connection of the position c with functional checks.
  • a transmission module with antenna is to be created separately from the chip module and card body
  • a card body is to be made by spraying or punching
  • the transmission module must be fixed together with the card body
  • the chip module must be installed in the card body with the transmission module.
  • connection chip module with transmission module For the use of chip cards with the chip module and rougher operation (high bending load, elevated temperature and increased pressure and humidity), several problems arise with the connection chip module with transmission module, in particular: a) NCP glued connections that produce contacts only on a pressure basis, are sufficient limited in this case, since the glue swells due to absorption of moisture and creates a contact interruption gap, which leads to functional errors. b) Compounds with conductive glue are not possible for these solutions with a chip module, since the contact distances of the chip are too close to each other. - A -
  • the card body is for reasons of stiffness a relatively thick plastic part made of a polymer such as PET or PEN or PEI.
  • the required heat of soldering is around 232 0 C.
  • the contact on the surface of the plastic must be addressed with about 280 0 C.
  • PEN plastic melt 250oC. So it must be an expensive polyimide plastic having a melting point above 300 0 C used.
  • the transmission module For wirebending the transmission module must be executed in any case with a closed carrier with transmission tracks.
  • the carrier must also be made of a polyimide plastic because of the relatively high bonding temperature. This also leads to high costs, on the one hand Wirebondieri are already higher than soldering costs and on the other hand, the costs for the closed carrier in addition and because polyimide must be used, high.
  • An economical production is not given. A punched lead without a closed support can not be used for this method, because the required adhesive sealant for the additional necessary fixation of the chip module in the card body through the openings in the punch runs out and can be cleaned later only by large expenses. Also, the production facilities are heavily affected by pollution and cause further costs.
  • the antenna structures of the transmission module with the openings in the card body must be designed precisely matching each other prior to connection to the chip module, which makes enormous demands on the indexing (match tolerance) of the layers.
  • the invention has for its object to provide a compound of the type mentioned above, which has an improved connection quality, and in the negative effects of bumps and tolerances of the chips, the pads / bumps and the interconnects as well as the negative temperature and pressure influences can be largely eliminated.
  • the invention aims for a clear, cost-effective production with high quality. This object is achieved according to the invention by a compound having the features of claim 1.
  • openings are made in which the chip or the chip connection area is at least partially immersed.
  • Electrically conductive connecting means are present in the openings and, or as an order on the pads / bumps.
  • connecting means soft solders, metal wires, adhesive and / or sealant are provided.
  • the metal foil is structured and serves as an electrical conductor.
  • the pads / bump no longer need to be placed exactly on the corresponding tracks, but they are introduced with at least part of their height in the openings with connecting means and are anchored stable in position through the walls of the openings and the cured connection means.
  • the connection feet for the connection, but the unevenness or other dimensional deviations no longer matter.
  • the economy and quality of the manufacturing process is thus significantly improved.
  • an intermetallic compound is created at the transition points between the trace, the solder and the connection feet.
  • the entire chip with pads / bumps in the opening in the substrate can be completely immersed and connected with connecting means to the track and be poured with plastic compound, which results in a special protection against pressure, heat and moisture.
  • FIG. 1 shows a section through bonding of a chip provided with connection surfaces with a substrate provided with metallic interconnects according to the prior art
  • Fig. 2 is a sectional view of an embodiment of the invention
  • connection according to the invention in section, with openings made in the polymeric substrate for chip pads or bumps containing connecting means,
  • 5 shows an embodiment in section, in which the chip and the pads or bumps at least partially embedded in the opening of the substrate (4) and are partially encapsulated with sealant
  • 6 shows a section of a variant in which the chip and the connection surfaces or bumps are completely embedded in the opening of the substrate and completely encapsulated with sealing compound
  • the connecting means is a metallic, electrically conductive wire which is connected to the bumps and the interconnects intermetallically in the Wirebond method
  • FIG. 8 shows a section of a variant in which the connecting means is connected in a wire-bonding process to a metallic, electronically conductive wire which extends intermetallically at the connecting surfaces or bumps and at the conductor tracks over at least part of the spirally laid turns.
  • FIG. 9 is a plan view of the embodiment of FIG. 8, without cover sheets and
  • FIG. 10a and FIG. 10b HF smartcard in plan view and side view with the connection according to the invention according to FIG. 7 or FIG. 8, FIG.
  • FIG. 11a and 11b a second application of the connection according to the invention according to FIG. 5 or FIG. 6 for a UHF smartcard in top view and side view, respectively, FIG.
  • FIG. 12a a third application of the solution according to the invention according to FIG. 5 or FIG. 6 for a strap chip module in plan view or longitudinal section along the line G-G according to FIG. 12a, FIG.
  • FIG. 13a and 13b show a fourth application of the connection according to FIG. 4, FIG. 5 or FIG. 6 in a UHF foil inlay in plan view or in longitudinal section,
  • Fig. 14b a side view.
  • FIG. 1 shows a prior art conventional connection of a chip (1, 2) provided with connecting surfaces (2, 2 ') with a polymeric substrate (4) of the laminate (26) provided with metallic conductor tracks (3, 3').
  • the chip (1) may for example have a size of 400x400x150 microns.
  • the conductor tracks (3, 3 ') are preferably made of copper.
  • the chip (1) is placed on the corresponding conductor tracks (3, 3 ') with the, for example, gold-plated connection surfaces (2, T), and the connection feet (2, 2') are materially connected to the conductor tracks (3, 3 ') , usually by a non-conductive adhesive.
  • the corresponding connection means is designated in FIG. 1 with (6).
  • the chip (1) itself is connected to the substrate 4 and the conductor tracks (3, 3 ') cohesively, usually by means of the non-conductive adhesive (6).
  • the result is the case that the adhesive (6) does not dry out to the desired line (dot-dashed line 24), but expands widely on the laminate (26), indicated by arrows D and D " Adhesive quality and there is a risk of moisture penetration into the joints (swelling of the adhesive 6) .
  • connection feet and the conductor tracks the smallest unevenness and tolerances can have a negative effect on the connection quality, which in FIG. 1 does not affect the connection foot (2 ') Conductor track (3 ') "sits", indicated (arrow C). Also, the "lifting" of the pad (2 1 ) (which may cause a connection interruption) may be due to temperature, or caused by swelling of the adhesive 6.
  • Fig. 1 the possible skipping of the conductive connecting means of very close to each other lying joints is indicated by an arrow A, which means a risk of short circuit.
  • FIG. 2 shows a connection according to the invention of the same chip (1) to the substrate (4) and the conductor tracks (3, 3 ').
  • the conductor tracks (3, 3 ') have openings (10, 10') which are open on the chip side and contain electrically conductive connection means (11) (soft solders or conductive adhesives).
  • the connecting surfaces (2, 2 ') are immersed in the connecting means (11) at least with part of their height.
  • connection feet (2, 2 ') available for the connection, but the unevenness or other dimensional deviations no longer matter.
  • the economy of the manufacturing process is thus significantly improved. Even with temperature-related small shifts, there is no connection interruption. Since now the electrically conductive connecting means (1 1) in the openings (10, 10 ') and not on the conductor surface are present, the risk of short circuit is eliminated or at least reduced.
  • connection feet (2, 2 ') with the corresponding conductor tracks (3, 3') via the electrically conductive connection means (1 1) are additionally solidified by a protective coating (15) (preferably a plastic compound, epoxy paint or an adhesive) and covered moisture-proof.
  • a chip (1a) which may be, for example, an RFID (Radio Frequency Identification) chip generation 2, and its connection to the conductor track (3), on a polymeric substrate 4a is laminated.
  • the substrate may e.g. made of PE or PET, PI or PEI, or made of impregnated with epoxy resin fabric.
  • the copper interconnects (3a, 3a ') are mounted on the side of the substrate 4a facing away from the chip (1a). In the substrate 4a through openings (10a, 10a ') per pad or bump (2) are made.
  • connection feet (2a, 2a ', 11d) are immersed at least part of their height.
  • the connecting means (11) as Lötbump (11 d) with the chip pads or bump (2) is supplied; this is such that a soldering tin is applied to the end face (2d ') of the connection surface (2d) of the chip (1).
  • a stored in the opening connection means is therefore no longer mandatory.
  • the conductor track (3) is open on the opposite side of the chip pad.
  • the required Lötsammlung, 220 0 C are optimally supplied to the junction. This via metal (copper) and chip quartz without going over the polymeric substrate.
  • the soldering times are significantly shortened due to metallic heat conduction.
  • the laminate bonding is significantly less stressed. This allows the use of less expensive substrates such as PE and less expensive laminate adhesives.
  • the chip (1 a) is connected to the substrate (4a) by means of an additional adhesive (16a), which may be mixed with soldering flux.
  • the compound is solidified with an additional protective coating (15) and covered moisture-proof, preferably in the form of a plastic film, or an epoxy paint coating or adhesive.
  • the development of the conductor track structure of the conductor foil on the laminate is carried out by etching or by a laser plasma method.
  • 4 shows a chip (1) with a connection surface (2d) which is equipped with an additional solder bump (1 1 d), in such a way that a soldering tin is provided on the end face (2d ') of the connection surface (2d) of the chip (1) (1 1 d) is applied.
  • An embedded in the opening (10a) connecting means (11) is thus no longer mandatory.
  • Fig. 5 shows a second embodiment according to the invention, in which the entire base of the chip (1) with bumps (2) with at least ei nem part of its height in the chip-side opening (1Of) of the substrate (4) dipped is and the pads or bumps (2) of the chip (1) with connecting means (11, 11d) in the recess with the conductor track (3) are connected.
  • the opening (10f) is open on the chip side and bounded on the opposite side of the chip (1) by the conductor track.
  • the conductor track (3) is freely open on the opposite side of the chip pad in this example.
  • the difference from the previous embodiment according to the invention lies in the fact that the chip (1), the connection surfaces and bumps (2) and the affected conductor track part (3) with connecting means (11, 11d) lie in the opening (10f) and with plastic sealant (6,16, 16c) are moisture-proof over at least a part of their heights.
  • the chip is precisely positioned and firmly anchored to the laminate by the chip and connection means guide in the opening.
  • Fig. 6 shows a third embodiment according to the invention and analogous to FIG. 5, in which the chip (1) and its pads or bumps (2, 2 ') immersed entirely in the substrate (4) and with plastic sealant (16 ) are completely poured.
  • the difference from the embodiment according to FIG. 5 lies in the fact that the chip with the connection surfaces and bumps are completely immersed in the substrate and completely surrounded by plastic sealing compound (6, 16, 16c).
  • the connection surfaces or bumps (2) are connected to the conductor track (3) in an intermetallic manner in a particularly rigid, firm and secure manner.
  • the whole chip (1) is completely immersed in the opening (10f) with plastic sealing compounds (6, 16, 16c) and surrounded.
  • the chip is accurately positioned and firmly anchored by the chip potting compound in the opening with the laminate.
  • the conductor track (3) is at least partially exposed on the opposite side of the chip pad freely.
  • the required soldering heat of approximately 220 0 C can be optimally supplied to the junction, this via metal (copper) and chip quartz without going over the polymeric substrate.
  • the soldering times are significantly shortened.
  • the laminate bonding is significantly less stressed. This allows the use of inexpensive substrate such as PE and inexpensive laminate adhesive.
  • the formation of the antenna conductor / antenna structure (3) by etching or lasing can also take place here after complete connection of the chip to the conductor foil and casting of the opening 10f with sealing compound (6, 16, 16c). This procedure •,. is preferred so that the opening, without polluting the plant, shed clean and can then be dried.
  • This design withstands chip, bumps and joints for increased pressure, temperature and humidity loads. These have an advantageous effect for continuous use in laundries (passing through calender rolls is made possible, etc.), high temperature pressure and humidity environment.
  • connection means (27; ).
  • the chip (1) is positioned in the opening (1 Of) with Die Attach adhesive (20) and glued to the conductor foil (3).
  • the chip (1) and the connection surfaces / bumps (2) with the connecting wires (21) are completely embedded in the opening (10f) of the substrate (4) and completely molded with plastic sealant (16).
  • the chip is exactly positioned, and firmly anchored by the chip potting compound in the opening (10f) with the laminate (26).
  • the conductor track (3) is at least partially exposed on the opposite side of the chip pad.
  • the required heat of welding temperature above 220 0 C
  • the laminate bonding is significantly less thermally stressed.
  • the wirebond process can be greatly accelerated.
  • this inventive method allows the use of less expensive substrates such as PE and less expensive laminate adhesive.
  • the formation of the antenna conductor (3) / antenna structure (22) by etching, laser or plasma method can also advantageously after complete connection of the chip to the antenna conductor, and after pouring the opening (10) with the sealant (6, 16) This is analogous to Fig. 2, Fig. 4, Fig. 5.
  • a hundred percent controlled sealing compound order is guaranteed and the connection is of the highest quality.
  • the chip, the bumps and joints with the wire (21) withstand increased pressure, temperature and humidity loads.
  • Fig. 8 shows a fifth embodiment in which a metallically electrically conductive wire (21) with the pads / bumps (2,2 ') and the interconnects (3) is intermetallically connected (Wirebondvon).
  • the chip (1) is positioned in the opening (10f) with Die attach adhesive (20) and glued to the conductor foil (3).
  • the chip (1) and the connecting surfaces / bumps (2,2 ') with the connecting wires (21) are completely embedded in the opening (10f) of the substrate (4) and completely encapsulated with plastic sealant (6, 16).
  • plastic sealant (6, 16) plastic sealant
  • the conductor track (3) is embodied here as a spiral antenna / coil antenna, as used for the production of HF smartcads (FIG. 9).
  • FIG. 8 illustrates how the connection of the start and end of the spiral antenna antenna track (3) with the pads / bumps) of the chip (1) through the connecting wire (21) in Wirebond compiler in the simplest, most universal and cost-effective manner is solved. Furthermore, it is clearly visible how the loops of the antenna cross the chips and how the beginning and the end of the coil antenna (3) are connected to the chip (1).
  • the formation of the antenna conductor (3) / antenna structure (3; 31) by etching, laser or plasma method can also be advantageously carried out after complete connection of the chip to the antenna conductor foil and after pouring the opening (10f) with sealing compound (6,16). This is one to one hundred percent Controlled sealing compound ensures and the connection is of the highest quality.
  • the chip, the bumps and the joints with the wire (21) are resistant to elevated pressure, temperature and humidity loads. These have an advantageous effect for continuous use at high temperatures and or high pressure and or high humidity.
  • FIG. 9 shows a top view of the solution according to the invention of FIG. 8.
  • the cover films and the sealant (16) have been omitted here for the sake of simplicity.
  • the optimal solution possibility of the connecting means (27, 28) and the simple bridging of the chip (1) over the antenna loops (3) by using the connecting wire (21), which allows a great flexibility with regard to the connection distances, are apparent.
  • FIG. 10a and 10b show an application for HF smart card (35), which is constructed according to the invention of FIG. 8 and FIG.
  • the spiral antenna (3) is made up of the antenna layer which is integrated (connected) to the substrate (4).
  • the entire smart card (35) is realized from a thickness of 0.1 mm and upwards. Again, the simple and inexpensive bridging of the antenna loop is clearly visible.
  • the two cover sheets (23) required for smart cards are applied to the laminate (26) by lamination.
  • the cover sheets are made of paper or polymer films and can be provided with fonts and logos before or after lamination.
  • FIG. 11a and 11b show an application for UHF smart card (36), which is constructed according to the invention according to FIG. 6 and FIG.
  • the dipole antenna is made up of the antenna layer (3) which is integrated with the substrate (4).
  • the entire smartcard (36) has a thickness from 0.1 mm. Again, the simple and inexpensive and thus optimal connection (40) of the antennas (trace) (3) to the chip pad (2) is clearly visible.
  • the two cover sheets (23) required for smart cards are applied to the laminate (26) by lamination.
  • the cover sheets (23) are made of paper or polymer films and can be provided with fonts and logos, before or after lamination. Smart card with UHF antennas respond to a greater distance than HF antennas. The choice of antenna type is made according to their requirement.
  • FIGs 12a and 12b show an application for UHF chip modules (37). These can be found in separately fabricated antennas, e.g. Metal antennas woven into textile or large antennas made in plastic application.
  • the connection to the antenna track (3) can be soldered or glued or mechanical.
  • This embodiment is constructed analogously as in FIG. 5 or FIG. 6 or FIG. 7 in the context of the invention and constructed in a thickness of the chip module from 0.1 mm. Also, the simple and inexpensive construction is clearly perceptible.
  • the chip (1) is completely covered by the substrate (4).
  • the chip module is suitable for heavy loads (laundry machines, high temperatures and pressures).
  • FIGS. 13a and 13b show an application for UHF inlay (38), which is constructed analogously to the connection according to FIG. 5 or FIG. 6 or FIG.
  • the dipole antenna is formed from the antenna layer (3) integrated with the substrate (4).
  • the total inlet thickness is realized from 0.1 mm. Also, the simple and inexpensive construction is clearly visible.
  • Figures 14a and 14b show an application for RF inlay (39) constructed in accordance with the invention of Figures 8 and 9.
  • the spiral antenna is formed of the antenna layer (3) integrated with the substrate (4). Again, the simple and inexpensive bridging of the antenna loop and thus the simple design of the solution is well visible.
  • the connection variants according to the invention described above are examples and, compared with the conventional connection solutions, have a significantly improved quality of connection and are much easier to manufacture, more cost-effective and usable in harsh and damp environments, such as in laundries.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

A connection of an RF chip (1) comprising pads (2; 2') is established by connecting said pads (2; 2') to substrate and strip conductors in an opening (10a; 10f) of a laminate. The connection to the strip conductors (3, 31) integrated into the substrate (4) is established via the chip pads (2). Once the connection has been established, the opening (10, 10', 10f) comprising the chip and the pads is filled with a sealing material that increases the compressive strength of the entire chip module. Preferably, the strip conductor structures are formed once the connection process of the chip (1) has been completed, thus significantly improving the cost efficiency and quality of the chip, simplifying the production processes, and optimizing a permanent safe connection between the chip and the strip conductors. Said connections can also be perfectly used in tough environments, e.g. in laundries.

Description

Verbindung eines mit Anschlussflächen und Bumps versehenen Chips mit einem mit metallischen Leiterbahnen versehenen Substrat Connection of a chip provided with pads and bumps with a substrate provided with metallic interconnects

Die Erfindung betrifft eine Verbindung gemäss dem Oberbegriff des Anspruches 1.The invention relates to a compound according to the preamble of claim 1.

Solche Verbindungen bei einem RF-Chip oder einem elektronischen Baustein mit Anschlussflächen bzw. Bumps sind mit metallischen Leiterbahnen bestücktes Substrat versehen, welche für auf Radiofrequenz basierenden Transponder-Textiletiketten, Transpon-der-TAG, Transponder-Smartcard, Transponder-Inlays, Chipmodule sowie weitere ähnli-che IC- Schaltkreise in hochstehender Qualität verwendet werden. Hiefür sind Frequenz-bereiche von 1 bis 3000 Megahertz vorgesehen.Such connections in an RF chip or an electronic component with pads or bumps are provided with substrate equipped with metallic tracks, which are suitable for radiofrequency based transponder textile labels, transponder-the-TAG, transponder smart card, transponder inlays, chip modules and others similar IC circuits are used in superior quality. For this purpose, frequency ranges from 1 to 3000 megahertz are provided.

Chipkarten können funktionierende Transponder sein und bestehen aus Chipmodulen und Antennen. Ein Chipmodul besteht aus mindestens einem Chip auf einer Leiterbahn mit einem Antennenanschluss.Smart cards can be functioning transponders and consist of chip modules and antennas. A chip module consists of at least one chip on a conductor track with an antenna connection.

Die heute bekannten Lösungen zur Herstellung der oben erwähnten Produkte verlangen ein aufwendiges Klebeverfahren mit Cyan-Acrylatklebern oder ein Hotmelt-Verfahren für die Verbindung zwischen dem Substrat und dem Chip. Auch ist die Kontaktverbindung zwischen der Anschlussfläche / Bump und der Leiterbahn mit Kleber wegen dem Quellen des Kunststoffes im Leim äusserst anfällig. Auch muss wegen den verschiedenen Temperaturausdehnungskoeffizienten der verschiedenen Kunststoffe und des Klebers mit starker Verwölbung und Delaminierung gerechnet werden.The solutions known today for the production of the above-mentioned products require a complicated adhesive process with cyan-acrylate adhesives or a hotmelt process for the connection between the substrate and the chip. Also, the contact connection between the pad / bump and the trace is highly susceptible to adhesive because of the swelling of the plastic in the glue. Also, due to the different coefficients of thermal expansion of the various plastics and the adhesive, it is necessary to reckon with severe warping and delamination.

Aus der Druckschrift US-A-6,259,408 ist bekannt, ein Chipmodul zu bauen, bei der die Anschlussflächen / Bumps (Höcker) der Chips auf die Oberfläche der Leiterbahnen aufgesetzt werden und diese durch Kleben miteinander in Kontakt zu halten, derart, dass ein metallischer Berührungskontakt entsteht, wobei auch vorgeschlagen wird, den Chip mit dem Substrat, beispielsweise mittels eines Klebstoffes, zusätzlich zu fixieren. Kunststoff-Folien sind wegen dessen Herstellungsverfahren durch Walz- und Giess- prozesse, sehr glatt und uneben. Dadurch findet der zusätzliche Klebstoff (hier Globtop in der Fachsprache genannt) kaum Möglichkeit, sich genügend zu verankern. Die Bump- Klebeverbindung und die zusätzliche Fixierungsart des Chips mit Anschlussflächen / Bumps sind nicht in der Lage, grossere äussere Kräfte standzuhalten, die in täglichen Prozessen (z.B. Wäscherei oder Tragen in Geldbeuteln) auftreten. Anwendungen bei hoher Feuchte, erhöhtem Druck und Temperaturen sind damit nicht möglich.From US-A-6,259,408 is known to build a chip module in which the pads / bumps (bumps) of the chips are placed on the surface of the tracks and hold them by gluing in contact, such that a metallic contact arises, wherein it is also proposed to fix the chip with the substrate, for example by means of an adhesive in addition. Plastic foils are very smooth and uneven due to their manufacturing processes by rolling and casting processes. As a result, the additional adhesive (here called Globtop in technical language) has little opportunity to anchor itself sufficiently. The bump bond and the additional fixation style of the chip / bump chip are unable to withstand greater external forces encountered in daily processes (eg, laundry or carrying in purses). Applications with high humidity, increased pressure and temperatures are therefore not possible.

Die Druckschrift EP-A-O 706 152 zeigt eine Lösung für den Bau von Chipkarten, bei der ein Substrat mit metallischem Leiterbahnstrukturen-Layer (Antenne) mit darauf in herkömmlicher Klebe-Technik (US 6,259,408) verbundenen Chip zu verwenden. Über den Chip wird ein weiteres Substrat mit ausgestanzter Fläche in Chipdicke zur Aufnahme des Chip laminiert, gefolgt mit weiteren zwei Folien. Es handelt sich hier um einen sehr aufwändigen Arbeitsprozess, welche höchste Anforderung an den Zentrierungsprozess (Indexierung der Folien) und an die Verleimung stellt. Die Verwendung von mehreren Substratlagen gibt dieser Lösung eine relativ grosse Dicke und macht sie dadurch sehr steif (in Inlets und Kartenbau unerwünscht). Durch die oben erwähnte Problematik und Anforderungen ist diese Lösung sehr kostenintensiv und nicht verwendbar für den wirtschaftlichen Einsatz in Umgebungen mit erhöhter Belastung und wo Kartenflexibilität und Kartenqualität verlangt sind.Document EP-A-0 706 152 shows a solution for the construction of smart cards using a substrate with metallic wiring pattern layer (antenna) with chip bonded thereto in conventional bonding technique (US 6,259,408). Another chip-cut substrate is punched over the chip in chip thickness to accommodate the chip, followed by another two films. This is a very complex working process, which places the highest demands on the centering process (indexing of the foils) and on the gluing. The use of multiple substrate layers gives this solution a relatively large thickness, making it very stiff (undesirable in inlets and card making). Due to the above-mentioned problems and requirements, this solution is very costly and not suitable for economical use in environments with increased load and where card flexibility and card quality are required.

Durch die sehr kleinen Abmasse der Chips, der Anschlussflächen /Bump und der Leiterbahnen, welche im Mikrometer-Bereich liegen, wirken sich kleinste Unebenheiten und Toleranzen negativ auf die Verbindungsqualität aus. Die erforderliche Qualität ist schwierig zu kontrollieren und zu halten. Die Wirtschaftlichkeit des Herstellungsprozesses wird dadurch enorm beeinträchtigt.Due to the very small dimensions of the chips, the connecting surfaces / bump and the printed conductors, which lie in the micrometer range, the smallest unevenness and tolerances have a negative effect on the connection quality. The required quality is difficult to control and maintain. The profitability of the manufacturing process is thereby enormously impaired.

Oft werden Etiketten für Textilwaren mit so genannten RFID (Radio Frequency Identifi- cation)-Chips versehen, die in Prozess- oder Verkaufslogistik Anwendung finden sowie auch zum Diebstahlschutz dienen können. Derartige Etiketten müssen z.B. auch für Kochwäsche geeignet sein. Durch die Feuchtigkeit leidet die vorher erwähnte, herkömmliche Verbindung der Anschlussflächen und Bumps mit den entsprechenden Leiterbahnen. Der die Anschlussflächen/ Bumps umliegende Kunst- bzw. Klebstoff quillt und kann die Anschlussfüsse um einige Nanometer abheben, was einen Verbindungsunterbruch zur Folge hat. Durch die hohe Temperatur bei der Kochwäsche werden Wärmedehnungen in beteiligten Materialien erzeugt, die wiederum kleinsten Verschiebungen in der Verbindung erzeugen und ebenfalls Verbindungsunterbrüche verursachen.Often labels for textiles are provided with so-called RFID (Radio Frequency Identification) chips, which can be used in process or sales logistics as well as serve to protect against theft. Such labels must e.g. also be suitable for cooking linen. Due to the moisture, the aforementioned conventional connection of the pads and bumps suffers from the corresponding traces. The plastic / adhesive surrounding the pads / bumps swells and can lift the connection feet by a few nanometers, resulting in a connection interruption. Due to the high temperature of the cooking laundry, thermal expansions are generated in the materials involved, which in turn generate the smallest displacements in the connection and also cause connection interruptions.

Da die Leiterbahnen und die einzelnen Verbindungsstellen sehr nahe beieinander liegen (Abstand ca. 100 μm) und nicht begrenzt sind, besteht über die leitenden Verbindungsmittel der benachbarten Verbindungsstellen ausserdem eine Kurzschlussgefahr.Since the interconnects and the individual joints are very close to each other (distance about 100 microns) and are not limited, there is also a risk of short circuit on the conductive connection means of the adjacent joints.

In der Druckschrift DE-A-196 18 103 wird eine Chipkartenmodul-Ausführung vorgeschlagen, bei der das Wirebond-Verfahren angewendet wird. Sehr nachteilig bei diesem Vorschlag ist, dass der Wirebonddraht auf jeden Fall über die Oberkante des Verbindungssteges des Trägers verläuft und durch einen sogenannten Globtop gegen Beschädigungen geschützt werden muss. Der Grund dafür ist der, dass der Chipanschluss und die Anschlüsse der Kontaktflächen nicht in der gleichen Kavität liegen können, was bedingt, dass der Chip durch aus dem Träger gebildete Verbindungsstege getragen werden muss. Der Bonddraht muss diesen Verbindungssteg des Trägers überqueren. Zum Schutz des Anschlusses am Chip und des Bonddrahtes (-bogens) muss ein von der Trägeroberfläche erhöhter Globtop aufgebracht werden. Diese Erhöhung wirkt sich sehr nachteilig aus, da keine ebene Fläche mehr gegeben ist. Der Prozess für das Anbringen des Globtops ist sehr schwierig zu kontrollieren, da sich einerseits der Tropfen auf dem Träger, weil nicht geführt, breit macht (verläuft) und andererseits Verschmutzungen auf beiden Seiten des Chipkartenmoduls entstehen, die nur mühsam entfernt werden können. Weiter ist nicht gewährleistet, dass der dünne empfindliche Draht auch wirklich innerhalb der Globtop-Kuppe liegt, dies weil sich die Kuppe durch das Verbreitern auf der Trägeroberfläche unkontrolliert senkt. Die Leiterbahnstruktur ist vor dem Verbinden des Chips mit der Leiterbahn durch Stanzen ausgearbeitet. Durch die vielen heiklen Prozessschritte sind die Herstellungskosten für Chipkarten dieser Art hoch. Aus diesen Gründen ist die Ausführung nicht geeignet zur Herstellung von hoch beanspruchbaren, qualitativ guten und kostengünstigen Verbindungen zwischen Microchip und Leiterbahnstrukturen auf einen Polymer- oder Leadframe-Laminat für den Einsatz in rauer Umgebung, dies zum Beispiel zur Herstellung von Transpondern.In the document DE-A-196 18 103 a smart card module design is proposed in which the Wirebond method is used. Very disadvantageous in this proposal is that the Wirebonddraht in any case runs over the upper edge of the connecting web of the carrier and must be protected by a so-called Globtop against damage. The reason for this is that the chip connection and the terminals of the contact surfaces can not be in the same cavity, which requires that the chip must be supported by connecting webs formed from the carrier. The bonding wire must cross this connecting web of the carrier. To protect the connection on the chip and the bonding wire (arc), a globtop raised from the surface of the carrier must be applied. This increase has a very disadvantageous effect, since no more flat surface is given. The process of attaching the globtop is very difficult to control because, on the one hand, the droplet on the carrier, because it is not guided, widens, and on the other hand, contamination is created on both sides of the chipcard module, which can only be removed with difficulty. Furthermore, there is no guarantee that the thin, sensitive wire will actually lie inside the globtop dome, because the dome is lowered uncontrollably due to widening on the support surface. The conductor track structure is prepared by punching before connecting the chip to the conductor track. Due to the many delicate process steps, the production costs for chip cards of this type are high. For these reasons, the design is not suitable for producing high-stress, high-quality and low-cost connections between microchip and interconnect structures on a polymer or leadframe laminate for use in harsh environments, for example for the production of transponders.

Die Druckschrift DE-A-195 00 925 zeigt ein weiteres Verfahren zur Herstellung von Chipkarten. Die Chipkarte zur kontaktlosen Datenübertragung weist verschiedene Schritte und Elemente auf, Gemäß diesem Verfahren wird dem separat gespritzten oder gestanzten Kartenkörper aus Kunststoff mit folgenden Öffnungen: a) ein separat fertig hergestelltes Übertragungsmodul angebaut, welches eine Antenne in Form von mindestens einer Spule und/oder in Form elektrisch leitender Schichten aufweist. Das separat fertig gefertigtes Übertragungsmodul besteht aus einer einzigen metallischen Leiterplatte (Lead) oder kann in einer speziellen Anwendung kombiniert auf einen Trägerkörper aus Kunststoff aufgebracht sein. Das Übertragungsmodul weist Anschlussflächen zur elektrischen Ankopplung an die Anschlussflächen des Chipmoduls durch Öffnungen im Kartenkörper auf. b) Ein fertig gefertigtes Kartenkörper dass bereits bedruckt sein kann. Dieses Zwischenerzeugnis (Kartenkörper mit eingelagertem Übertragungsmodul ohne teures Chipmodul) kann nun gegebenenfalls bedruckt und anschliessend optisch nach Ausschusskriterien begutachtet werden. c) Ein separat fertig gefertigtes Chipmodul mit Chip und auf Träger aufgebrachten Anschlussleiterbahnen. d) Nachträgliche Verbindung der Positionen a und b und zuletzt die Montage und Verbindung der Position c mit Funktionskontrollen.The document DE-A-195 00 925 shows another method for the production of smart cards. The chip card for contactless data transmission has various steps and elements, According to this method, the separately molded or stamped plastic card body with the following openings: a) a separately finished manufactured transmission module is attached, which is an antenna in the form of at least one coil and / or in Has form of electrically conductive layers. The separately finished transmission module consists of a single metallic printed circuit board (Lead) or can be combined in a special application applied to a carrier body made of plastic. The transmission module has connection surfaces for electrical connection to the connection surfaces of the chip module through openings in the card body. b) A finished card body already printed. This intermediate product (card body with embedded transmission module without expensive chip module) can now optionally be printed and then visually inspected according to committee criteria. c) A separately finished chip module with chip and on carrier mounted connecting tracks. d) Subsequent connection of the positions a and b and finally the assembly and connection of the position c with functional checks.

Es zeigt sich, dass der Aufwand zur Herstellung von Chipkarten nach diesem Verfahren sehr kostenintensiv und umständlich ist, weilIt turns out that the effort for the production of smart cards by this method is very costly and cumbersome, because

1 ) vorgängig ein Chipmodul aus polymerem Substrat mit Leiterbahn und mit mindestens ein Chip erstellt werden muss;1) before a chip module of polymeric substrate with conductor and with at least one chip must be created;

2) ein Übertragungsmodul mit Antenne separat vom Chipmodul und Kartenköper zu erstellen ist;2) a transmission module with antenna is to be created separately from the chip module and card body;

3) ein Kartenkörper durch Spritzen oder Stanzen anzufertigen ist;3) a card body is to be made by spraying or punching;

4) das Übertragungsmodul mit dem Kartenkörper zusammen fixiert werden muss;4) the transmission module must be fixed together with the card body;

5) das Chipmodul im Kartenkörper mit dem Übertragungsmodul eingebaut werden muss.5) the chip module must be installed in the card body with the transmission module.

Wegen den vielen erforderlichen Arbeitsschritten mit relativ kritischen Arbeitsprozessen, resultieren daraus hohe Ausschussraten. Diese wirken sich erheblich negativ auf die Kosten aus.Because of the many required work steps with relatively critical work processes, this results in high reject rates. These have a significant negative impact on the costs.

Für den Einsatz der Chipkarten mit dem Chipmodul und rauerem Betrieb (hohe Biegebelastung, erhöhte Temperatur und erhöhter Druck und Feuchtigkeit) entstehen etliche Probleme mit der Verbindung Chipmodul mit Übertragungsmodul, wie insbesondere: a) NCP geklebte Verbindungen, die Kontakte nur auf Druckbasis erzeugen, genügen hier nur beschränkt, da der Leim durch Aufnahme von Feuchtigkeit aufquillt und einen Kontakt-Unterbruchspalt erzeugt, was zu Funktionsfehlern führt. b) Verbindungen mit leitendem Leim sind für diese Lösungen mit einem Chipmodul nicht möglich, da die Kontaktabstände der Chip zu nahe beieinander liegen. - A -For the use of chip cards with the chip module and rougher operation (high bending load, elevated temperature and increased pressure and humidity), several problems arise with the connection chip module with transmission module, in particular: a) NCP glued connections that produce contacts only on a pressure basis, are sufficient limited in this case, since the glue swells due to absorption of moisture and creates a contact interruption gap, which leads to functional errors. b) Compounds with conductive glue are not possible for these solutions with a chip module, since the contact distances of the chip are too close to each other. - A -

Die Leimmenge lässt sich nicht in so kleiner Menge dosieren, so dass der Leim den kleinen Leitertrennspalt überquert und Fehler durch Kurzschlüsse zwischen den einzelnen Kontaktstellen entstehen. c) Es zeigt sich, dass die Erstellung der Verbindung durch Weichlöten zwischen Chipmodul und Übertragungsmodul ein Erfordernis ist.The amount of glue can not be dosed in such a small amount, so that the glue crosses the small conductor separating gap and errors caused by short circuits between the individual contact points. c) It turns out that the creation of the connection by soldering between chip module and transmission module is a requirement.

Mit diesem Verfahren ist das Löten der Verbindung Chipmodul-Leiterbahn sehr schwierig, da die Lötwärme von unten und von oben durch den Kartenkörper und oder den Träger geführt werden muss. Es entstehen folgende sehr negativ auswirkende Probleme:With this method, the soldering of the connection chip module trace is very difficult because the soldering heat must be guided from below and from above through the card body and or the carrier. The following very negative effects arise:

1.) Der Kartenkörper ist aus Steifheitsgründen ein relativ dicker Kunststoffteil aus einem Polymer z.B. PET oder PEN oder PEI. Die erforderliche Lötwärme beträgt um die 232 0C. Der Kontakt an der Oberfläche des Kunststoffs muss mit ca. 2800C angegangen werden. Bei dieser Temperatur beginnt bereits der aus Kostengründen verwendete PET- ; PEN- Kunststoff zu schmelzen (250oC). Es muss also ein teurer Polyimid-Kunststoff mit einem Schmelzpunkt über 3000C verwendet werden.1.) The card body is for reasons of stiffness a relatively thick plastic part made of a polymer such as PET or PEN or PEI. The required heat of soldering is around 232 0 C. The contact on the surface of the plastic must be addressed with about 280 0 C. At this temperature already starts the PET used for cost reasons; PEN plastic melt (250oC). So it must be an expensive polyimide plastic having a melting point above 300 0 C used.

2.) Dieser Kunststoff ist erhältlich, aber sehr teuer, ca. 15 bis 20 mal höher als ein Kunststoff aus PET. Somit ist dieser Kunststoff für die Anwendung als Kartenköper zu teuer und könnte nur für Anwendungen, bei denen Kosten und Belastung unproblematische sind, eingesetzt werden. Leider gilt das besagte auch für den Träger des Übertragungsmodul. Die Wirtschaftlichkeit ist nicht gegeben.2.) This plastic is available but very expensive, about 15 to 20 times higher than a plastic made of PET. Thus, this plastic is too expensive to use as card stock and could be used only for applications where cost and stress are unproblematic. Unfortunately, the said also applies to the carrier of the transmission module. The economy is not given.

3.) Ein weiterer Nachteil der Wärmezuführung von aussen über den Kunststoff zur Verbindungsstelle ist die schlechte Wärmeleitung des Kunststoffes, kombiniert mit dem grossen Wärmeleitweg. Der grosse Wärmeleitweg ergibt sich wegen der verlangten Steifheit des Kartenkörpers, was ein dicker Kunststoff erfordert. Diese schlechte Wärmeleitung verlangsamt den automatischen Prozess enorm, was wiederum zu hohen Kosten führt.3.) Another disadvantage of the heat supply from the outside via the plastic to the junction is the poor heat conduction of the plastic, combined with the large Wärmeleitweg. The large heat conduction results because of the required stiffness of the card body, which requires a thicker plastic. This poor heat conduction slows down the automatic process enormously, which in turn leads to high costs.

Zum Wirebonden muss das Übertragungsmodul auf jeden Fall mit einem geschlossenem Träger mit Übertragungsleiterbahnen ausgeführt werden. Der Träger muss wegen der relativ hohen Bondtemperatur ebenfalls aus einem Polyimid-Kunststoff ausgeführt werden. Dies führt ebenfalls zu hohen Kosten, einerseits sind Wirebondkosten schon höher als Lötkosten und anderseits sind die Kosten für den geschlossenen Träger zusätzlich und weil Polyimid verwendet werden muss, hoch. Eine wirtschaftliche Fertigung ist nicht gegeben. Ein Stanzlead ohne geschlossenen Träger kann für dieses Verfahren nicht verwendet werden, weil die erforderliche Klebe-Dichtmasse für die zusätzlich notwendige Fixierung des Chipmoduls im Kartenkörper durch die Öffnungen im Stanzlead ausläuft und nur durch grosse Aufwendungen nachträglich gereinigt werden kann. Auch werden die Produktionsanlagen durch Verschmutzung stark in Mitleidenschaft gezogen und verursachen weitere Kosten.For wirebending the transmission module must be executed in any case with a closed carrier with transmission tracks. The carrier must also be made of a polyimide plastic because of the relatively high bonding temperature. This also leads to high costs, on the one hand Wirebondkosten are already higher than soldering costs and on the other hand, the costs for the closed carrier in addition and because polyimide must be used, high. An economical production is not given. A punched lead without a closed support can not be used for this method, because the required adhesive sealant for the additional necessary fixation of the chip module in the card body through the openings in the punch runs out and can be cleaned later only by large expenses. Also, the production facilities are heavily affected by pollution and cause further costs.

Ferner müssen die Antennenstrukturen des Übertragungsmoduls mit den Öffnungen im Kartenkörper präzis aufeinander passend vor dem Verbinden mit dem Chipmodul ausgearbeitet sein, was enorm hohe Anforderungen an die Indexierung (Übereinstimmungstoleranz) der Schichten stellt.Furthermore, the antenna structures of the transmission module with the openings in the card body must be designed precisely matching each other prior to connection to the chip module, which makes enormous demands on the indexing (match tolerance) of the layers.

Dieses Verfahren ist daher für eine intermetallische Lötverbindung zwischen Chip und Antennenleiter zum einen zu unwirtschaftlich (zusätzlicher Träger) für die Leiterbahnstrukturen und zum anderen lässt sich die Verbindungsöffnung nicht verschmutzungsfrei abdichten.This method is therefore for an intermetallic solder joint between the chip and antenna conductor on the one hand too uneconomical (additional support) for the conductor track structures and on the other hand, the connection opening can not seal pollution-free.

Der Erfindung liegt die Aufgabe zugrunde, eine Verbindung der eingangs genannten Art zu schaffen, die eine verbesserte Verbindungsqualität aufweist, und bei der die negativen Auswirkungen von Unebenheiten und Toleranzen der Chips, der Anschlussflächen / Bumps und der Leiterbahnen sowie auch die negativen Temperatur- und Druckeinflüsse weitgehend eliminiert werden können. Ausserdem wird mit der Erfindung eine übersichtliche, kostengünstige Produktion bei hoher Qualität angestrebt. Diese Aufgabe wird erfindungsgemäss durch eine Verbindung mit den Merkmalen des Anspruches 1 gelöst.The invention has for its object to provide a compound of the type mentioned above, which has an improved connection quality, and in the negative effects of bumps and tolerances of the chips, the pads / bumps and the interconnects as well as the negative temperature and pressure influences can be largely eliminated. In addition, the invention aims for a clear, cost-effective production with high quality. This object is achieved according to the invention by a compound having the features of claim 1.

Weitere bevorzugte Ausgestaltungen der erfindungsgemässen Verbindung bilden den Gegenstand der abhängigen Ansprüche.Further preferred embodiments of the inventive compound form the subject of the dependent claims.

Erfindungsgemäss sind in einem Substrat eines Laminates aus der Polymer- Substratfolie und einer Metallfolie Öffnungen angefertigt, in denen der Chip oder die Chipanschlussfläche mindestens teilweise eingetaucht sind. Elektrisch leitende Verbindungsmittel sind in den Öffnungen und, oder als Auftrag auf die Anschlussflächen / Bumps vorhanden. Als Verbindungsmittel sind Weichlote, Metalldrähte, Kleber und/oder Dichtmasse vorgesehen. Die Metallfolie ist strukturiert und dient als elektrischen Leiter.According to the invention, in a substrate of a laminate of the polymer substrate film and a metal foil, openings are made in which the chip or the chip connection area is at least partially immersed. Electrically conductive connecting means are present in the openings and, or as an order on the pads / bumps. As connecting means soft solders, metal wires, adhesive and / or sealant are provided. The metal foil is structured and serves as an electrical conductor.

Dabei müssen die Anschlussflächen / Bump nicht mehr exakt auf die entsprechenden Leiterbahnen aufgesetzt werden, sondern sie werden mit mindestens einem Teil ihrer Höhe in die Öffnungen mit Verbindungsmittel eingeführt und sind durch die Wandungen der Öffnungen und das ausgehärtete Verbindungsmittel lagestabil verankert. Somit steht nicht nur mehr Fläche von den Anschlussfüssen für die Verbindung zur Verfügung, sondern die Unebenheiten oder sonstige Abmassabweichungen spielen keine Rolle mehr. Die Wirtschaftlichkeit und Qualität des Herstellungsprozesses wird somit erheblich verbessert. Auch bei temperaturbedingten kleinen Verschiebungen kommt es zu keinem Verbindungsunterbruch. Da nun die elektrisch leitenden Verbindungsmittel geführt in den Öffnungen und nicht auf der Leiterbahnoberfläche vorhanden sind, wird auch die Kurzschlussgefahr weitgehend eliminiert oder zumindest vermindert. Bei Anwendungen von Weichloten entsteht eine intermetallische Verbindung an den Übergangsstellen zwischen Leiterbahn, Lot und Anschlussfüssen.In this case, the pads / bump no longer need to be placed exactly on the corresponding tracks, but they are introduced with at least part of their height in the openings with connecting means and are anchored stable in position through the walls of the openings and the cured connection means. Thus, not only is more area available from the connection feet for the connection, but the unevenness or other dimensional deviations no longer matter. The economy and quality of the manufacturing process is thus significantly improved. Even with temperature-related small shifts, there is no connection interruption. Since now the electrically conductive connection means are guided in the openings and not on the track surface, the risk of short circuit is largely eliminated or at least reduced. In soft solder applications, an intermetallic compound is created at the transition points between the trace, the solder and the connection feet.

Gemäss der Erfindung kann aber auch der ganze Chip mit Anschlussflächen / Bumps in die Öffnung im Substrat vollständig eingetaucht und mit Verbindungsmittel mit der Leiterbahn verbunden und mit Plastikmasse eingegossen sein, womit sich ein besonderer Schutz gegen Druck, Wärme und Feuchtigkeit ergibt. Dies macht den Transpon- der auch fähig für den Einsatz unter schwersten Bedingungen wie: hoher Druck, hohe Temperatur- und grosse Feuchtigkeitseinwirkung (Wäscherei-Kailander oder Autoclave), das heisst, dass die erfindungsgemässe Verbindung im Transponder eingesetzt werden kann in feuchte Umgebung und Wäschereien bei Waschtemperaturen bis zu 900C, in Autoclaven bis 1380C und in Wäscherei-Kailander mit Oberflächentemperaturen (+Druck) bis 1700C.According to the invention, however, the entire chip with pads / bumps in the opening in the substrate can be completely immersed and connected with connecting means to the track and be poured with plastic compound, which results in a special protection against pressure, heat and moisture. This makes the transponder also capable of use under the most severe conditions such as: high pressure, high temperature and high humidity (laundry Kailander or Autoclave), which means that the inventive compound can be used in transponder in wet environment and laundries at washing temperatures up to 900C, in autoclaves up to 1380C and in laundry-kailander with surface temperatures (+ pressure) up to 1700C.

Die Erfindung wird nachfolgend anhand der Zeichnung näher erläutert. Es zeigt rein schematisch:The invention will be explained in more detail with reference to the drawing. It shows purely schematically:

Fig. 1 einen Schnitt durch Kleben eines mit Anschlussflächen versehenen Chips mit einem mit metallischen Leiterbahnen versehenen Substrat gemäss dem Stand der Technik,1 shows a section through bonding of a chip provided with connection surfaces with a substrate provided with metallic interconnects according to the prior art,

Fig. 2 ein im Schnitt dargestelltes Ausführungsbeispiel einer erfindungsge-mässenFig. 2 is a sectional view of an embodiment of the invention

Verbindung eines mit Anschlussflächen und Bumps versehenen Chips mit einem in metallischen Leiterbahnen versehenen Öffnungen,Connection of a chip provided with pads and bumps with an openings provided in metallic tracks,

Fig. 3 ein Ausführungsbeispiel einer erfindungsgemässen Verbindung im Schnitt, mit im polymeren Substrat angefertigten Öffnungen für Chipanschlussflächen bzw. Bumps beinhaltend Verbindungsmittel,3 an embodiment of a connection according to the invention in section, with openings made in the polymeric substrate for chip pads or bumps containing connecting means,

Fig. 4 ein Ausführungsbeispiel eines Chips mit Anschlussflächen bzw. Bumps beinhaltend das Verbindungsmittel im Schnitt,4 shows an embodiment of a chip with pads or bumps including the connecting means in section,

Fig. 5 ein Ausführungsbeispiel im Schnitt, bei welchem der Chip und die Anschlussflächen bzw. Bumps mindestens teilweise in die Öffnung des Substrates (4) eingelassen und teilweise mit Dichtmasse eingegossen sind, Fig. 6 einen Schnitt einer Variante, bei welcher der Chip und die Anschluss-flächen bzw. Bumps vollständig in die Öffnung des Substrates eingelassen und vollständig mit Dichtmasse eingegossen sind,5 shows an embodiment in section, in which the chip and the pads or bumps at least partially embedded in the opening of the substrate (4) and are partially encapsulated with sealant, 6 shows a section of a variant in which the chip and the connection surfaces or bumps are completely embedded in the opening of the substrate and completely encapsulated with sealing compound,

Fig. 7 einen Schnitt eines Ausführungsbeispiels, bei der das Verbindungsmittel ein metallischer, elektrisch leitender Draht das an den Anschlussflächen bzw. Bumps und an den Leiterbahnen intermetallisch im Wirebond-Verfahren verbunden ist,7 is a section of an embodiment in which the connecting means is a metallic, electrically conductive wire which is connected to the bumps and the interconnects intermetallically in the Wirebond method,

Fig. 8 einen Schnitt einer Variante, bei der das Verbindungsmittel ein metallischer, elektronisch leitender Draht das an den Anschlussflächen oder Bumps und an den Leiterbahnen intermetallisch, über mindestens ein Teil der spiralmässig ausgelegten Windungen erstreckt, im Wirebond-Verfahren verbunden ist,8 shows a section of a variant in which the connecting means is connected in a wire-bonding process to a metallic, electronically conductive wire which extends intermetallically at the connecting surfaces or bumps and at the conductor tracks over at least part of the spirally laid turns.

Fig. 9 eine Draufsicht auf die Ausführung gemäss Fig. 8, ohne Deckfolien und9 is a plan view of the embodiment of FIG. 8, without cover sheets and

Klebemasse,Adhesive,

Fig. 10a und Fig. 10b, HF-Smartcard in Drauf- bzw. Seitenansicht mit der erfin- dungsgemässen Verbindung nach Fig. 7 bzw. Fig. 8,10a and FIG. 10b, HF smartcard in plan view and side view with the connection according to the invention according to FIG. 7 or FIG. 8, FIG.

Fig. 11a und Fig. 11 b, eine zweite Anwendung der erfindungsgemässen Verbindung nach der Fig. 5 oder Fig. 6 für eine UHF-Smartcard in Drauf- bzw. Seitenansicht,11a and 11b, a second application of the connection according to the invention according to FIG. 5 or FIG. 6 for a UHF smartcard in top view and side view, respectively, FIG.

Fig. 12a und Fig. 12b, eine dritte Anwendung der erfindungsgemässen Lösung nach der Fig. 5 oder Fig. 6 für einen Strap-Chipmodul in Draufsicht bzw. Längsschnitt entlang der Linie G - G nach Fig. 12a,12a and FIG. 12b, a third application of the solution according to the invention according to FIG. 5 or FIG. 6 for a strap chip module in plan view or longitudinal section along the line G-G according to FIG. 12a, FIG.

Fig. 13a und Fig. 13b eine vierte Anwendung der Verbindung nach Fig. 4, Fig. 5 oder Fig. 6 in einem UHF Folien Inlay in Draufsicht bzw. im Längsschnitt,13a and 13b show a fourth application of the connection according to FIG. 4, FIG. 5 or FIG. 6 in a UHF foil inlay in plan view or in longitudinal section,

Fig. 14a und Fig. 14b eine fünfte Anwendung der Verbindung nach der Fig. 7 und Fig. 8 für einen HF Folien Inlay im Schnitt gemäss der Linie K - K nachFIGS. 14a and 14b show a fifth application of the connection according to FIGS. 7 and 8 for a HF foil inlay in section along line K - K in FIG

Fig. 14b einer Seitenansicht.Fig. 14b a side view.

Fig.1 zeigt eine dem Stand der Technik entsprechende, herkömmliche Verbindung eines mit Anschlussflächen (2, 2') versehenen Chips (1 ) mit einem mit metallischen Leiterbahnen (3, 3') versehenen polymeren Substrat (4) des Laminates (26). Der Chip (1 ) kann beispielsweise eine Grosse von 400x400x150 μm aufweisen. Die Leiterbahnen (3, 3') bestehen vorzugsweise aus Kupfer. Der Chip (1 ) wird mit den zum Beispiel vergoldeten Anschlussflächen (2, T) auf die entsprechenden Leiterbahnen (3, 3') aufgesetzt, und die Anschlussfüsse (2, 2') werden mit den Leiterbahnen (3, 3') stoffschlüssig verbunden, in der Regel durch einen nicht leitenden Kleber. Das entsprechende Verbindungsmittel ist in Fig. 1 mit (6) bezeichnet. Auch der Chip (1 ) selber wird mit dem Substrat 4 und den Leiterbahnen (3, 3') stoffschlüssig, in der Regel mittels des nicht leitenden Klebstoffes (6) verbunden. Dabei ergibt sich der Fall, dass der Klebstoff (6) nicht nach der Wunschlinie (strichpunktierte Linie 24) austrocknet, sondern sich weiträumig auf dem Laminat (26) ausläuft, mit Pfeile D und D" dargestellt. Das Auslaufen des Klebers verschlechtert ganz wesentlich die Klebequalität und es entsteht die Gefahr des Eindringens von Feuchtigkeit in die Verbindungsstellen (Aufquellen des Klebstoffes 6). Dies führt zu Korrosion und Oxydation der Kontaktstellen. Weiter hebt sich durch die Wasseraufnahme die Verbindung Anschlussfläche (2) / Leiterbahn (3) voneinander im Mikrometerbereich ab (Aufquellen), was dazu führt, dass der Transponder schon nach kurzer Einsatzzeit ausfällt.1 shows a prior art conventional connection of a chip (1, 2) provided with connecting surfaces (2, 2 ') with a polymeric substrate (4) of the laminate (26) provided with metallic conductor tracks (3, 3'). The chip (1) may for example have a size of 400x400x150 microns. The conductor tracks (3, 3 ') are preferably made of copper. The chip (1) is placed on the corresponding conductor tracks (3, 3 ') with the, for example, gold-plated connection surfaces (2, T), and the connection feet (2, 2') are materially connected to the conductor tracks (3, 3 ') , usually by a non-conductive adhesive. The corresponding connection means is designated in FIG. 1 with (6). Also, the chip (1) itself is connected to the substrate 4 and the conductor tracks (3, 3 ') cohesively, usually by means of the non-conductive adhesive (6). The result is the case that the adhesive (6) does not dry out to the desired line (dot-dashed line 24), but expands widely on the laminate (26), indicated by arrows D and D " Adhesive quality and there is a risk of moisture penetration into the joints (swelling of the adhesive 6) .This leads to corrosion and oxidation of the contact points.Also rises by the water absorption, the connection pad (2) / conductor track (3) from each other in the micrometer range (Swelling), which means that the transponder fails after a short period of use.

Wie bereits erwähnt, können sich bei den sehr kleinen Abmassen der Chips (1 ), der Anschlussfüsse und der Leiterbahnen die kleinsten Unebenheiten und Toleranzen negativ auf die Verbindungsqualität auswirken, was in Fig. 1 beim Anschlussfuss (2'), der nicht ganz auf der Leiterbahn (3') „sitzt", angedeutet ist (Pfeil C). Auch kann das „Anheben" der Anschlussfläche (21) (was ein Verbindungsunterbruch zur Folge haben kann) temperaturbedingt sein, oder durch Anquellen des Klebstoffes 6 verursacht werden. In Fig. 1 ist auch mit einem Pfeil A das mögliche Überspringen der leitenden Verbindungsmittel der sehr nahe beieinander liegenden Verbindungsstellen angedeutet, welches eine Kurzschlussgefahr bedeutet.As already mentioned, in the case of the very small dimensions of the chips (1), the connection feet and the conductor tracks, the smallest unevenness and tolerances can have a negative effect on the connection quality, which in FIG. 1 does not affect the connection foot (2 ') Conductor track (3 ') "sits", indicated (arrow C). Also, the "lifting" of the pad (2 1 ) (which may cause a connection interruption) may be due to temperature, or caused by swelling of the adhesive 6. In Fig. 1, the possible skipping of the conductive connecting means of very close to each other lying joints is indicated by an arrow A, which means a risk of short circuit.

Fig. 2 zeigt eine erfindungsgemässe Verbindung des gleichen Chips (1 ) mit dem Substrat (4) und den Leiterbahnen (3, 3'). Die Leiterbahnen (3, 3') weisen Öffnungen (10, 10') auf, die chipseitig offen stehen und elektrisch leitende Verbindungsmittel (11 ) (Weichlote oder leitende Kleber) beinhalten. Die Anschlussflächen (2, 2') sind zumindest mit einem Teil ihrer Höhe in die Verbindungsmittel (11 ) eingetaucht. Somit steht nicht nur mehr Fläche von Anschlussfüssen (2, 2') für die Verbindung zur Verfügung, sondern die Unebenheiten oder sonstige Abmassabweichungen spielen keine Rolle mehr. Die Wirtschaftlichkeit des Herstellungsprozesses wird somit erheblich verbessert. Auch bei temperaturbedingten kleinen Verschiebungen kommt es zu keinem Verbindungsunterbruch. Da nun die elektrisch leitenden Verbindungsmittel (1 1 ) in den Öffnungen (10, 10') und nicht auf der Leiterbahnoberfläche vorhanden sind, wird auch die Kurzschlussgefahr eliminiert oder zumindest vermindert.FIG. 2 shows a connection according to the invention of the same chip (1) to the substrate (4) and the conductor tracks (3, 3 '). The conductor tracks (3, 3 ') have openings (10, 10') which are open on the chip side and contain electrically conductive connection means (11) (soft solders or conductive adhesives). The connecting surfaces (2, 2 ') are immersed in the connecting means (11) at least with part of their height. Thus, not only is more area of connection feet (2, 2 ') available for the connection, but the unevenness or other dimensional deviations no longer matter. The economy of the manufacturing process is thus significantly improved. Even with temperature-related small shifts, there is no connection interruption. Since now the electrically conductive connecting means (1 1) in the openings (10, 10 ') and not on the conductor surface are present, the risk of short circuit is eliminated or at least reduced.

Der stoffschlüssig, über klebende Dichtmasse (16) mit dem Substrat (4) und der Leiterbahnen (3) verbundene Chip 1 , dessen Anschlussfüsse (2, 2') mit den entsprechenden Leiterbahnen (3, 3') über die elektrisch leitenden Verbindungsmittel (1 1 ) verbunden sind, ist zusätzlich durch einen Schutzüberzug (15) (vorzugsweise eine Kunststoffmasse, Epoxy-Lack oder ein Kleber) verfestigt und feuchtigkeitsdicht abgedeckt.The materially connected, via adhesive sealing compound (16) to the substrate (4) and the conductor tracks (3) connected chip 1, the connection feet (2, 2 ') with the corresponding conductor tracks (3, 3') via the electrically conductive connection means (1 1) are additionally solidified by a protective coating (15) (preferably a plastic compound, epoxy paint or an adhesive) and covered moisture-proof.

Fig.3 zeigt eine erste Ausführungsart gemäss der Erfindung bei der ein Chip (1a), bei dem es sich beispielsweise um einen RFID (Radio Frequency Identification)-Chip Generation 2 handeln kann, und deren Verbindung mit der Leiterbahn (3), die auf einem polymeren Substrat 4a laminiert ist. Das Substrat kann z.B. aus PE oder PET, PI oder PEI, oder aus mit Epoxydharz getränktem Gewebe bestehen. Bei diesem Ausführungsbeispiel sind die Kupferleiterbahnen (3a, 3a') auf der dem Chip (1a) abgewandten Seite des Substrates 4a angebracht. Im Substrat 4a sind durchgehende Öffnungen (10a, 10a') pro Anschlussfläche bzw. Bump (2) angefertigt. Diese sind chipseitig offen und auf der Gegenseite durch die Leiterbahn verschlossen und beinhalten die elektrisch leitende Verbindungsmittel (11 ) (Weichlote oder leitende Kleber) in welche die Anschlussfüsse (2a, 2a', 11 d) zumindest mit einem Teil ihrer Höhe eingetaucht sind. Dadurch ist der Chip exakt positioniert und durch die Bump- und Verbindungsmittelführung in der Öffnung fest zum Laminat verankert.3 shows a first embodiment according to the invention in which a chip (1a), which may be, for example, an RFID (Radio Frequency Identification) chip generation 2, and its connection to the conductor track (3), on a polymeric substrate 4a is laminated. The substrate may e.g. made of PE or PET, PI or PEI, or made of impregnated with epoxy resin fabric. In this embodiment, the copper interconnects (3a, 3a ') are mounted on the side of the substrate 4a facing away from the chip (1a). In the substrate 4a through openings (10a, 10a ') per pad or bump (2) are made. These are open on the chip side and closed on the opposite side by the conductor track and contain the electrically conductive connection means (11) (soft solders or conductive adhesives) in which the connection feet (2a, 2a ', 11d) are immersed at least part of their height. As a result, the chip is accurately positioned and firmly anchored to the laminate in the opening by the bump and Verbindungsungsmittelführung.

Bei einer anderen Lösung wird das Verbindungsmittel (11 ) als Lötbump (11 d) mit den Chipanschlussflächen bzw. Bump (2) zugeführt; dies, derart, dass an der Stirnseite (2d') der Anschlussfläche (2d) des Chips (1) ein Lötzinn aufgebracht ist. Ein in der Öffnung eingelagertes Verbindungsmittel ist damit nicht mehr zwingend erforderlich. Die Leiterbahn (3) liegt auf der Gegenseite der Chipanschlussfläche frei offen. Dadurch kann die erforderliche Lötwärme, 2200C, zur Verbindungsstelle optimal zugeführt werden. Dies via Metall (Kupfer) und Chipquarz ohne über das polymere Substrat zu gehen. Dadurch werden die Lötzeiten auf Grund metallischer Wärmeleitung wesentlich verkürzt. Die Laminatklebung wird bedeutend weniger beansprucht. Dies erlaubt die Anwendung von kostengünstigeren Substraten wie z.B. PE und kostengünstigeren Laminatklebern.In another solution, the connecting means (11) as Lötbump (11 d) with the chip pads or bump (2) is supplied; this is such that a soldering tin is applied to the end face (2d ') of the connection surface (2d) of the chip (1). A stored in the opening connection means is therefore no longer mandatory. The conductor track (3) is open on the opposite side of the chip pad. As a result, the required Lötwärme, 220 0 C, are optimally supplied to the junction. This via metal (copper) and chip quartz without going over the polymeric substrate. As a result, the soldering times are significantly shortened due to metallic heat conduction. The laminate bonding is significantly less stressed. This allows the use of less expensive substrates such as PE and less expensive laminate adhesives.

Der Chip (1 a) ist mittels eines zusätzlichen Klebstoffes (16a), welches mit Lötflussmittel durchmischt sein kann, mit dem Substrat (4a) verbunden. Die Verbindung ist mit einem zusätzlichen Schutzüberzug (15) verfestigt und feuchtigkeitsdicht abgedeckt, dies vorzugsweise in Form einer Kunststoff-Folie, oder eines Epoxy- Lack-Überzuges oder einer Klebemasse. Die Ausarbeitung der Leiterbahn-Struktur aus der Leiterbahnfolie am Laminat erfolgt durch Ätzen oder durch ein Laser-Plasmaverfahren. Fig. 4 zeigt ein Chip (1 ) mit Anschlussfläche (2d) welcher mit zusätzlichem Lötbump (1 1 d) ausgerüstet ist, dies, derart, dass an der Stirnseite (2d') der Anschlussfläche (2d) des Chips (1 ) ein Lötzinn (1 1 d) aufgebracht ist. Ein in der Öffnung (1Oa) eingelagertes Verbindungsmittel (11 ) ist damit nicht mehr zwingend erforderlich.The chip (1 a) is connected to the substrate (4a) by means of an additional adhesive (16a), which may be mixed with soldering flux. The compound is solidified with an additional protective coating (15) and covered moisture-proof, preferably in the form of a plastic film, or an epoxy paint coating or adhesive. The development of the conductor track structure of the conductor foil on the laminate is carried out by etching or by a laser plasma method. 4 shows a chip (1) with a connection surface (2d) which is equipped with an additional solder bump (1 1 d), in such a way that a soldering tin is provided on the end face (2d ') of the connection surface (2d) of the chip (1) (1 1 d) is applied. An embedded in the opening (10a) connecting means (11) is thus no longer mandatory.

Fig. 5 zeigt eine zweite Ausführungsart gemäss der Erfindung, bei der die ganze Grundfläche des Chips (1) mit Anschlussflächen bzw. Bumps (2) mit mindestens ei-nem Teil ihrer Höhe in die chipseitige Öffnung (1Of) des Substrates (4) eingetaucht ist und die Anschlussflächen bzw. Bumps (2) des Chips (1) mit Verbindungsmitteln (11 ,11d) in der Vertiefung mit der Leiterbahn (3) verbunden sind. Die Öffnung (1Of) ist chipseitig offen und auf der Gegenseite des Chip (1 ) durch die Leiterbahn begrenzt. Die Leiterbahn (3) liegt auf der Gegenseite der Chipanschlussfläche in diesem Beispiel frei offen. Dadurch kann die erforderliche Lötwärme von 2200C zur Verbindungsstelle optimal zugeführt werden. Dies via Metall (Kupfer) und Chipquarz ohne über das poly- mere Substrat zu gehen. Dadurch werden die Lötzeiten (weil metallische Wärmeleitung) wesentlich verkürzt. Die Laminatklebung wird bedeutend weniger beansprucht. Dies erlaubt die Anwendung von kostengünstigen Substraten wie z.B. PE und kostengünstigen Laminatkleber.Fig. 5 shows a second embodiment according to the invention, in which the entire base of the chip (1) with bumps (2) with at least ei nem part of its height in the chip-side opening (1Of) of the substrate (4) dipped is and the pads or bumps (2) of the chip (1) with connecting means (11, 11d) in the recess with the conductor track (3) are connected. The opening (10f) is open on the chip side and bounded on the opposite side of the chip (1) by the conductor track. The conductor track (3) is freely open on the opposite side of the chip pad in this example. As a result, the required soldering heat of 220 0 C can be optimally supplied to the junction. This via metal (copper) and chip quartz without going over the polymeric substrate. As a result, the soldering times (because metallic heat conduction) are significantly shortened. The laminate bonding is significantly less stressed. This allows the use of low-cost substrates such as PE and inexpensive laminate adhesive.

Der Unterschied zu der vorherigen erfindungsgemässen Ausführung liegt darin, dass der Chip (1 ), die Anschlussflächen und Bumps (2) und der betroffene Leiterbahnteil(3) mit Verbindungsmitteln (11 , 11d) in der Öffnung (10f) liegen und mit Plastik-Dichtmasse (6,16, 16c) über mindestens einen Teil ihrer Höhen feuchtigkeitssicher umgössen sind. Dadurch ist der Chip exakt positioniert und durch die Chip- und Verbindungsmittelführung in der Öffnung fest zum Laminat verankert.The difference from the previous embodiment according to the invention lies in the fact that the chip (1), the connection surfaces and bumps (2) and the affected conductor track part (3) with connecting means (11, 11d) lie in the opening (10f) and with plastic sealant (6,16, 16c) are moisture-proof over at least a part of their heights. As a result, the chip is precisely positioned and firmly anchored to the laminate by the chip and connection means guide in the opening.

Ein weiterer Unterschied liegt darin, dass das Ätzen oder Lasern der Antennenleiter (3) /Antennenstruktur (3) nach dem vollständigen Verbinden des Chips (1 ) mit dem Antennenleiter (3) und nach dem Ausgiessen der Öffnung (10f) mit Dichtmasse (6, 16, 16c) erfolgen kann. Damit wird ein zu 100%tig kontrollierter Dichtmassenauftrag begrenzt durch die Ränder der Öffnung (10f) gewährleistet und die Verbindung ist von höchster Qualität und sehr kostengünstig gegenüber anderen bekannten Verfahren. Dieses Vorgehen ist sehr wichtig, damit die Öffnung ohne die Anlage zu verschmutzen sauber vergossen und anschliessend getrocknet werden kann.Another difference is that the etching or lasing of the antenna conductor (3) / antenna structure (3) after complete connection of the chip (1) with the antenna conductor (3) and after pouring the opening (10f) with sealing compound (6, 16, 16c) can take place. Thus, a 100% tig controlled sealing mass order is limited by the edges of the opening (10f) guaranteed and the connection is of the highest quality and very inexpensive compared to other known methods. This procedure is very important, so that the opening without the system to pollute cleanly poured and then dried.

Fig. 6 zeigt eine dritte Ausführungsart gemäss der Erfindung und analog der Fig. 5, bei welcher der Chip (1 ) und dessen Anschlussflächen bzw. Bumps (2, 2') gänzlich im Substrat (4) eingetaucht und mit Plastik-Dichtmasse (16) vollständig eingegossen sind. Der Unterschied zur Ausführung gemäss Figur 5 liegt darin, dass der Chip mit den Anschlussflächen und Bumps hier vollständig im Substrat eingetaucht und mit Plastik- Dichtmasse (6, 16, 16c) vollständig umgössen sind. Dadurch werden die Anschlussflächen bzw. Bumps (2) besonders steif, fest und sicher mit der Leiterbahn (3) intermetallisch verbunden. Der ganze Chip (1 ) ist mit Plastik-Dichtmassen (6, 16, 16c) vollständig in der Öffnung (10f) eingetaucht und umgössen. Dadurch ist der Chip exakt positioniert und durch die Chip- Vergussmasse in der Öffnung fest mit dem Laminat verankert.Fig. 6 shows a third embodiment according to the invention and analogous to FIG. 5, in which the chip (1) and its pads or bumps (2, 2 ') immersed entirely in the substrate (4) and with plastic sealant (16 ) are completely poured. The difference from the embodiment according to FIG. 5 lies in the fact that the chip with the connection surfaces and bumps are completely immersed in the substrate and completely surrounded by plastic sealing compound (6, 16, 16c). As a result, the connection surfaces or bumps (2) are connected to the conductor track (3) in an intermetallic manner in a particularly rigid, firm and secure manner. The whole chip (1) is completely immersed in the opening (10f) with plastic sealing compounds (6, 16, 16c) and surrounded. As a result, the chip is accurately positioned and firmly anchored by the chip potting compound in the opening with the laminate.

Die Leiterbahn (3) liegt mindestens teilweise auf der Gegenseite der Chipanschlussfläche frei offen liegen. Dadurch kann die erforderliche Lötwärme von annähernd 2200C zur Verbindungsstelle optimal zugeführt werden, dies via Metall (Kupfer) und Chipquarz ohne über das polymere Substrat zu gehen. Dadurch werden die Lötzeiten (weil metallische Wärmeleitung) wesentlich verkürzt. Die Laminatklebung wird bedeutend weniger beansprucht. Dies erlaubt die Anwendung von kostengünstigem Substrat wie z.B. PE und kostengünstigem Laminatkleber.The conductor track (3) is at least partially exposed on the opposite side of the chip pad freely. As a result, the required soldering heat of approximately 220 0 C can be optimally supplied to the junction, this via metal (copper) and chip quartz without going over the polymeric substrate. As a result, the soldering times (because metallic heat conduction) are significantly shortened. The laminate bonding is significantly less stressed. This allows the use of inexpensive substrate such as PE and inexpensive laminate adhesive.

Das Bilden der Antennenleiter / Antennenstruktur (3) durch Ätzen oder Lasern kann auch hier nach dem vollständigen Verbinden des Chips mit der Leiterbahnfolie und Ausgiessen der Öffnung 10f mit Dichtmasse (6, 16, 16c) erfolgen. Dieses Vorgehen •,. wird bevorzugt, damit die Öffnung, ohne die Anlage zu verschmutzen, sauber vergossen und anschliessend getrocknet werden kann.The formation of the antenna conductor / antenna structure (3) by etching or lasing can also take place here after complete connection of the chip to the conductor foil and casting of the opening 10f with sealing compound (6, 16, 16c). This procedure •,. is preferred so that the opening, without polluting the plant, shed clean and can then be dried.

Durch diese Ausführung widersteht der Chip, die Anschlussflächen bzw. Bumps und Verbindungsstellen erhöhten Druck-, Temperatur- und Feuchtigkeitsbelastungen. Diese wirken sich vorteilhaft für den Dauereinsatz in Wäschereien (Durchfahren durch Kalanderwalzen ist dadurch ermöglicht, etc.), hohe Temperatur- Druck- und Feuchte- Umgebung aus.This design withstands chip, bumps and joints for increased pressure, temperature and humidity loads. These have an advantageous effect for continuous use in laundries (passing through calender rolls is made possible, etc.), high temperature pressure and humidity environment.

Fig. 7 zeigt ein viertes Ausführungsbeispiel gemäss der Erfindung, bei der als Verbindungsmittel (27; 28) ein die Anschlussflächen / Bumps (2) und die Leiterbahnen (3; 28) intermetallisch verbindender metallischer, elektrisch leitender Draht (21 ) vorgesehen ist (Wirebondverfahren). Der Chip (1 ) ist in der Öffnung (1 Of) mit Die-Attach-Kleber (20) positioniert und an die Leiterbahnfolie (3) geklebt. Der Chip (1 ) und die Anschlussflächen / Bumps (2) mit den Verbindungsdrähten (21 ) sind ganz in die Öffnung (10f) des Substrates (4) eingelassen und vollständig mit Kunststoff-Dichtmasse (16) eingegossen. Dadurch ist der Chip exakt positioniert, und durch die Chip-Vergussmasse in der Öffnung (10f) mit dem Laminat (26) fest verankert.7 shows a fourth exemplary embodiment according to the invention, in which a metal, electrically conductive wire (21) which intermetallically connects the connection surfaces / bumps (2) and the conductor tracks (3, 28) is provided as connection means (27; ). The chip (1) is positioned in the opening (1 Of) with Die Attach adhesive (20) and glued to the conductor foil (3). The chip (1) and the connection surfaces / bumps (2) with the connecting wires (21) are completely embedded in the opening (10f) of the substrate (4) and completely molded with plastic sealant (16). As a result, the chip is exactly positioned, and firmly anchored by the chip potting compound in the opening (10f) with the laminate (26).

Die Leiterbahn (3) liegt auf der Gegenseite der Chipanschlussfläche mindestens teilweise frei offen. Dadurch kann die erforderliche Schweisswärme (Temperatur über 2200C), welche an der Verbindungsstelle entsteht, optimal abgeführt bzw. kontrolliert werden. Dies via Metall (Kupfer) und Chipquarz auf entsprechende Kühlplatten, ohne über das polymere Substrat zu gehen. Dadurch wird die Schweissqualität wesentlich verbessert. Die Laminatklebung wird bedeutend weniger thermisch beansprucht. Der Wirebond-Prozess kann stark beschleunigt werden. Weiter erlaubt dieses erfindungs- gemässe Verfahren die Anwendung von kostengünstigerem Substrate wie z.B. PE und kostengünstigerem Laminatkleber.The conductor track (3) is at least partially exposed on the opposite side of the chip pad. As a result, the required heat of welding (temperature above 220 0 C), which arises at the junction, be optimally dissipated or controlled. This via metal (copper) and chip quartz on appropriate cooling plates, without going over the polymeric substrate. This significantly improves the quality of the weld. The laminate bonding is significantly less thermally stressed. The wirebond process can be greatly accelerated. Furthermore, this inventive method allows the use of less expensive substrates such as PE and less expensive laminate adhesive.

Das Bilden der Antennenleiter (3) / Antennenstruktur (22) durch Ätzen, Lasern- oder Plasmaverfahren kann auch hier vorteilhafterweise nach dem vollständigen Verbinden des Chips mit dem Antennenleiter, und nach dem Ausgiessen der Öffnung (10) mit der Dichtmasse (6, 16) erfolgen, dies analog der Fig. 2, Fig. 4, Fig. 5. Hierbei wird ein zu hundertprozentig kontrollierter Dichtmassenauftrag gewährleistet und die Verbindung ist von bester Qualität. Durch diese Ausführung widerstehen der Chip, die Anschlussflächen bzw. Bumps und Verbindungsstellen mit dem Draht (21 ) erhöhten Druck-, Temperatur- und Feuchtigkeitsbelastungen.The formation of the antenna conductor (3) / antenna structure (22) by etching, laser or plasma method can also advantageously after complete connection of the chip to the antenna conductor, and after pouring the opening (10) with the sealant (6, 16) This is analogous to Fig. 2, Fig. 4, Fig. 5. Here, a hundred percent controlled sealing compound order is guaranteed and the connection is of the highest quality. With this design, the chip, the bumps and joints with the wire (21) withstand increased pressure, temperature and humidity loads.

Fig. 8 zeigt ein fünftes Ausführungsbeispiel, bei dem ein metallisch elektrisch leitender Draht (21 ) mit den Anschlussflächen / Bumps (2,2') und den Leiterbahnen (3) intermetallisch verbunden ist (Wirebondverfahren). Der Chip (1) ist in der Öffnung (10f) mit Die- Attach-Kleber (20) positioniert und an die Leiterbahnfolie (3) geklebt. Der Chip (1 ) und die Anschlussflächen / Bumps (2,2') mit den Verbindungsdrähten (21 ) sind vollständig in die Öffnung (10f) des Substrates (4) eingelassen und vollständig mit Kunststoff- Dichtmasse (6, 16) eingegossen. Dadurch ist der Chip exakt positioniert und durch die Chip-Vergussmasse in der Öffnung (10f) fest zum Laminat (26) verankert.Fig. 8 shows a fifth embodiment in which a metallically electrically conductive wire (21) with the pads / bumps (2,2 ') and the interconnects (3) is intermetallically connected (Wirebondverfahren). The chip (1) is positioned in the opening (10f) with Die attach adhesive (20) and glued to the conductor foil (3). The chip (1) and the connecting surfaces / bumps (2,2 ') with the connecting wires (21) are completely embedded in the opening (10f) of the substrate (4) and completely encapsulated with plastic sealant (6, 16). As a result, the chip is precisely positioned and firmly anchored by the chip potting compound in the opening (10f) to the laminate (26).

Die Leiterbahn (3) ist hier als Spiralantenne/Spulenantenne ausgeführt, wie sie für die Herstellung von HF-Smartcads (Fig. 9) eingesetzt wird. In der Fig. 8 ist verdeutlicht, wie die Verbindung der Anfangs- und Endstelle der spiralartigen Antennenleiterbahn (3) mit den Anschlussflächen /Bumps) des Chips(1 ) durch den Verbindungsdraht (21 ) im Wirebondverfahren auf einfachste, universale und kosten-günstige Weise gelöst ist. Weiter ist deutlich sichtbar gemacht, wie die Schleifen der Antenne den Chips unterkreuzen und wie der Anfang und das Ende der Spulenantenne (3) mit dem Chips (1 ) verbunden sind. Das Bilden der Antennenleiter (3) / Antennenstruktur (3;31 ) durch Ätzen, Lasernoder Plasmaverfahren kann auch hier vorteilhafterweise nach dem vollständigen Verbinden des Chips mit der Antennenleiterfolie und nach dem Ausgiessen der Öffnung (10f) mit Dichtmasse (6,16) erfolgen. Hierbei wird ein zu hundertprozentig kontrollierter Dichtmassenauftrag gewährleistet und die Verbindung ist von bester Qualität. Durch diese Ausführung ist der Chip, die Anschlussflächen bzw. Bumps und die Verbindungsstellen mit dem Draht (21 ) beständig bei erhöhten Druck-, Temperatur- und Feuchtigkeits-Belastungen. Diese wirken sich vorteilhaft aus für den Dauereinsatz bei hohen Temperaturen und oder hohem Druck und oder grosser Feuchte.The conductor track (3) is embodied here as a spiral antenna / coil antenna, as used for the production of HF smartcads (FIG. 9). In Fig. 8 illustrates how the connection of the start and end of the spiral antenna antenna track (3) with the pads / bumps) of the chip (1) through the connecting wire (21) in Wirebondverfahren in the simplest, most universal and cost-effective manner is solved. Furthermore, it is clearly visible how the loops of the antenna cross the chips and how the beginning and the end of the coil antenna (3) are connected to the chip (1). The formation of the antenna conductor (3) / antenna structure (3; 31) by etching, laser or plasma method can also be advantageously carried out after complete connection of the chip to the antenna conductor foil and after pouring the opening (10f) with sealing compound (6,16). This is one to one hundred percent Controlled sealing compound ensures and the connection is of the highest quality. By this design, the chip, the bumps and the joints with the wire (21) are resistant to elevated pressure, temperature and humidity loads. These have an advantageous effect for continuous use at high temperatures and or high pressure and or high humidity.

Fig. 9 zeigt eine Draufsicht auf die erfindungsgemässe Lösung der Fig. 8. Die Deckfolien und die Dichtmasse (16) sind hier zur vereinfachten Darstellung weggelassen worden. Ersichtlich ist die optimale Lösungsmöglichkeit der Verbindungsmittel (27, 28) und die einfache Überbrückung des Chips (1 ) über die Antennenschleifen (3) durch Anwendung des Verbindungsdrahtes (21 ), das eine grosse Flexibilität bezüglich der Ver- bindungsabstände zulässt.9 shows a top view of the solution according to the invention of FIG. 8. The cover films and the sealant (16) have been omitted here for the sake of simplicity. The optimal solution possibility of the connecting means (27, 28) and the simple bridging of the chip (1) over the antenna loops (3) by using the connecting wire (21), which allows a great flexibility with regard to the connection distances, are apparent.

Fig. 10a und Fig. 10b zeigen eine Anwendung für HF- Smartcard (35), die gemäss der Erfindung nach Fig. 8 und Fig. 9 aufgebaut ist. Die Spiralantenne (3) ist aus dem An- tennenlayer, welcher mit dem Substrat (4) integriert (verbunden) ist, ausgearbeitet. Die gesamte Smart-card (35) ist ab einer Dicke ab 0,1 mm realisiert. Auch hier ist die einfache und kostengünstige Überbrückung der Antennenschleife gut ersichtlich. Die zwei für Smartcards erforderlichen Deckfolien (23) werden durch Auflaminieren auf das Laminat (26) aufgebracht. Die Deckfolien sind aus Papier- oder aus Polymerefolien und können mit Schriften und Logos vor oder nach dem Laminieren versehen werden.10a and 10b show an application for HF smart card (35), which is constructed according to the invention of FIG. 8 and FIG. The spiral antenna (3) is made up of the antenna layer which is integrated (connected) to the substrate (4). The entire smart card (35) is realized from a thickness of 0.1 mm and upwards. Again, the simple and inexpensive bridging of the antenna loop is clearly visible. The two cover sheets (23) required for smart cards are applied to the laminate (26) by lamination. The cover sheets are made of paper or polymer films and can be provided with fonts and logos before or after lamination.

Fig. 11a und Fig. 1 1 b zeigen eine Anwendung für UHF- Smartcard (36), die gemäss der Erfindung nach Figur 6 und Figur 7 aufgebaut ist. Die Dipolantenne ist aus dem Antennenlayer (3), welcher mit dem Substrat (4) integriert ist, ausgearbeitet. Die gesamte Smartcard (36) hat eine Dicke ab 0,1 mm. Auch hier ist der einfache und kostengünstige und damit optimale Anschluss (40) der Antennen (Leiterbahn) (3) zur Chip- Anschlussfläche (2) gut ersichtlich. Die zwei für Smartcards erforderlichen Deckfolien (23) werden durch Auflaminieren auf das Laminat (26) aufgebracht. Die Deckfolien (23) sind aus Papier- oder aus Polymerfolien und können mit Schriften und Logos, vor oder nach dem Laminieren, versehen werden. Smartcard mit UHF-Antennen sprechen auf eine grossere Distanz an als Ausführung mit HF-Antennen. Die Wahl der Antennenart wird nach deren Anforderung getroffen.11a and 11b show an application for UHF smart card (36), which is constructed according to the invention according to FIG. 6 and FIG. The dipole antenna is made up of the antenna layer (3) which is integrated with the substrate (4). The entire smartcard (36) has a thickness from 0.1 mm. Again, the simple and inexpensive and thus optimal connection (40) of the antennas (trace) (3) to the chip pad (2) is clearly visible. The two cover sheets (23) required for smart cards are applied to the laminate (26) by lamination. The cover sheets (23) are made of paper or polymer films and can be provided with fonts and logos, before or after lamination. Smart card with UHF antennas respond to a greater distance than HF antennas. The choice of antenna type is made according to their requirement.

Fig. 12a und Fig. 12b zeigen eine Anwendung für UHF-Chipmodule (37). Diese finden in separat gefertigten Antennen, wie z.B. in Textil eingewobenen Metallantennen oder in Plastik ausgearbeitete grosse Antennen Anwendung. Die Verbindung mit der Antennen Leiterbahn (3) kann dabei gelötet oder geleimt oder mechanisch sein. Diese Ausführung ist im Rahmen der Erfindung analog wie nach Fig. 5 oder Fig. 6 oder Fig.7 aufgebaut und in einer Dicke des Chipmoduls ab 0, 1 mm gebaut. Auch ist der einfache und kostengünstige Aufbau deutlich wahrnehmbar dargestellt. Ersichtlich in Fig. 6 bzw. Fig. 7 ist, wie der Chip (1 ) vollkommen durch das Substrat (4) abgedeckt ist. Der Chipmodul ist für grosse Belastungen geeignet (Wäscherei-Maschinen, hohe Temperaturen und Drücke.)Figures 12a and 12b show an application for UHF chip modules (37). These can be found in separately fabricated antennas, e.g. Metal antennas woven into textile or large antennas made in plastic application. The connection to the antenna track (3) can be soldered or glued or mechanical. This embodiment is constructed analogously as in FIG. 5 or FIG. 6 or FIG. 7 in the context of the invention and constructed in a thickness of the chip module from 0.1 mm. Also, the simple and inexpensive construction is clearly perceptible. As can be seen in Fig. 6 and Fig. 7, the chip (1) is completely covered by the substrate (4). The chip module is suitable for heavy loads (laundry machines, high temperatures and pressures).

Fig. 13a und Fig. 13b zeigen eine Anwendung für UHF-Inlay (38), die analog wie die Verbindung nach Fig. 5 oder Fig. 6 oder Fig. 7 aufgebaut ist. Die Dipolantenne ist aus dem Antennenlayer (3), welches mit dem Substrat (4) integriert ist, gebildet. Die gesamte Inlet-Dicke ist ab 0,1 mm realisiert. Auch ist der einfache und kostengünstige Aufbau deutlich ersichtlich.FIGS. 13a and 13b show an application for UHF inlay (38), which is constructed analogously to the connection according to FIG. 5 or FIG. 6 or FIG. The dipole antenna is formed from the antenna layer (3) integrated with the substrate (4). The total inlet thickness is realized from 0.1 mm. Also, the simple and inexpensive construction is clearly visible.

Fig. 14a und Fig. 14b zeigen eine Anwendung für HF-Inlay (39), die gemäss der Erfindung nach Fig. 8 und Fig. 9 aufgebaut ist. Die Spiralantenne ist aus dem Antennenlayer (3), welches mit dem Substrat (4) integriert ist, gebildet. Auch hier ist die einfache und kostengünstige Überbrückung der Antennenschleife und somit der einfache Aufbau der Lösung gut ersichtlich. Die vorstehend beschriebenen erfindungsgemässen Verbindungsvarianten stellen Beispiele dar, und weisen gegenüber den herkömmlichen Verbindungslösungen eine wesentlich verbesserte Verbindungsqualität und sind in ihrer Herstellung wesentlich einfacher, kostengünstiger und in rauer und feuchter Umgebung, wie zum Beispiel in Wäschereien, einsetzbar.Figures 14a and 14b show an application for RF inlay (39) constructed in accordance with the invention of Figures 8 and 9. The spiral antenna is formed of the antenna layer (3) integrated with the substrate (4). Again, the simple and inexpensive bridging of the antenna loop and thus the simple design of the solution is well visible. The connection variants according to the invention described above are examples and, compared with the conventional connection solutions, have a significantly improved quality of connection and are much easier to manufacture, more cost-effective and usable in harsh and damp environments, such as in laundries.

LEGENDE:LEGEND:

1 Chip1 chip

1 a Chip1 a chip

1 b Chip1 b chip

1 c Chip1 c chip

2, 2' Anschlussfläche2, 2 'connection surface

2a, 2a1 Anschlussfäche2a, 2a 1 Anschlussfäche

2b Anschlussfläche / Bump2b pad / bump

2c Anschlussfläche2c connection area

2d Anschlussfläche2d connection surface

2d' Stirnseite des Anschlussfläche2d 'end face of the pad

2d" Mantelseite des Anschlussfläche2d "shell side of the connection surface

3, 3' Leiterbahnen3, 3 'tracks

3a, 3a' Leiterbahnen3a, 3a 'conductor tracks

3b Leiterbahn3b trace

3, 3' Leiterbahnen3, 3 'tracks

3b, 3b1 Leiterbahnen3b, 3b 1 tracks

3b", 3b" " Leiterbahnen3b ", 3b" "printed conductors

3c Leiterbahn3c trace

4 polymeres Substrat4 polymeric substrate

4a polymeres Substrat4a polymeric substrate

5 Verbindungsmittel, leitender Leim5 bonding agent, conductive glue

6 Klebstoff, elektrisch nicht leitend6 adhesive, electrically non-conductive

10; 10' Öffnung in der Leiterbahn10; 10 'opening in the conductor track

10a, 10. ϊ Öffnung im Substrat10a, 10. ϊ Opening in the substrate

10b Öffnung in der Leiterbahn10b opening in the conductor track

10e Öffnung in der Leiterbahn10e opening in the conductor track

10f Öffnung im Substrat10f opening in the substrate

1 1 Verbindungsmittel, Lote1 1 connecting means, solders

1 1 d Verbindungsmittel (Lötbumps)1 1 d Connection means (solder bumps)

13b Verdickter Teil13b Thickened part

15 Schutzüberzug15 protective cover

16 Dichtmasse, (Underfill), elektrisch nicht leitend16 sealant, (underfill), electrically non-conductive

16a Klebstoff16a glue

16b Kunststoffmasse16b plastic mass

16c Klebstoff mit Lötflussmittel16c adhesive with solder flux

18 Schlitz18 slot

20 Klebstoff für Die-Attach20 adhesive for die attach

21 Draht- Verbindungsmittel für Wirebondverfahren21 Wirebonds for Wirebondverfahren

22 Abstand zwischen den Leiterbahnen22 Distance between the tracks

23 Deckfolien23 cover sheets

26 Laminat26 laminate

27, 28 Verbindungsmittel27, 28 connecting means

31 Antennenstruktur31 antenna structure

35, 36 Smartcard35, 36 Smartcard

37 UHF-Chipmodul37 UHF chip module

38 UHF-Inlay38 UHF inlay

39 HF-Inlay39 RF inlay

40 Anschluss40 connection

C Abstand zwischen zwei Leiterbahnen D Verlaufender Klebstoff h2 Höhe der Dichtmasse über den Chip h1 Höhe der Anschlussfläche / Bumps x1 Öffnungsmass x2 Öffnungsmass x3 öffnungsmass C Distance between two tracks D Bending adhesive h2 Height of sealing compound above chip h1 Height of connecting surface / bumps x1 Opening size x2 Opening size x3 Opening dimension

Claims

PATENTANSPRÜCHE 1. Verbindung eines mit Anschlussflächen bzw. Bumps versehenen Chips (1 ) für Herstellung von Chipmodulen, Tags, Inlays für textile Etiketten, Chipkarten oder dergleichen, mit einem Laminat (26) aus metallischen Leiterbahnen (3, 3'; 3a, 3a'; 3b, 3b', 3b", 3b1") und einem Substrat (4) insbesondere aus polymeren Kunststoffen und mit Verbindungsmitteln (5, 11 , 11d ,21 ) zur Verbindung der Anschlussflächen bzw. Bumps (2) mit den Leiterbahnen, wobei die Leiterbahnen Antennenstrukturen für Transponder bilden oder nach aussen führende elektrische Kontakte für eine nachträgliche Verbindung mit Antennenstrukturen aufweisen, dadurch gekennzeichnet, dass das Laminat (26) mit Öffnungen (10, 10'; 10a, 10a'; 10b; 10e; 10f) und/oder Vertiefungen versehen ist, in welche die Chip-Anschlussflächen (2, 2'; 2a, 2a'; 2b; 2c; 2d) und/oder der komplette Chip (1 ) mit mindestens einem Teil der Höhe eingetaucht sind, und in welcher die elektrische Verbindung des Chips über das in der korrespondierenden Öffnung liegenden Verbindungsmittel (5, 11 , 11d, 21 ) mit der jeweiligen Leiterbahn (3, 3'; 3a, 3a'; 3b, 3b', 3b", 3b'") erfolgt.1. Connection of a chips or chips provided with bumps (1) for the production of chip modules, tags, inlays for textile labels, chip cards or the like, with a laminate (26) of metallic interconnects (3, 3 ', 3a, 3a'; 3b, 3b ', 3b ", 3b 1 ") and a substrate (4), in particular of polymeric plastics, and with connection means (5, 11, 11d, 21) for connecting the bumps (2) to the conductor tracks, wherein the Conductor tracks form antenna structures for transponders or have external electrical contacts for subsequent connection to antenna structures, characterized in that the laminate (26) with openings (10, 10 '; 10a, 10a';10b;10e; 10f) and / or Recesses is provided, in which the chip pads (2, 2 '; 2a, 2a';2b;2c; 2d) and / or the complete chip (1) are immersed with at least a portion of the height, and in which the electrical Connection of the chip over that in the correspondent Erenden opening lying connecting means (5, 11, 11d, 21) with the respective conductor track (3, 3 '; 3a, 3a '; 3b, 3b ', 3b ", 3b'"). 2. Verbindung nach Anspruch 1 , dadurch gekennzeichnet, dass die Verbindung auch für Einsatz in rauer Umgebung vorgesehen ist, wie hohe äussere Druck-, hohe Temperatur- und grosse Feuchtigkeitseinwirkung oder den Einsatz in der Wäscherei vorgesehen ist.2. A compound according to claim 1, characterized in that the compound is also intended for use in harsh environment, such as high external pressure, high temperature and high humidity or use in the laundry is provided. 3. Verbindung nach Anspruch 1 oder 2, dadurch gekennzeichnet, dass die An- schluss- und Leiterbahnstrukturen in der metallischen Leiterbahnfolie nach dem vollständigen Verbindungsprozess des Chips (1 ) auf die unstrukturierte Leiterbahnfolie erzeugbar ist.3. A compound according to claim 1 or 2, characterized in that the connection and conductor track structures in the metallic conductor foil after the complete connection process of the chip (1) on the unstructured conductor foil can be generated. 4. Verbindung nach Anspruch 1 , dadurch gekennzeichnet, dass die Anschluss- und Leiterbahnstrukturen in der metallischen Leiterbahnfolie vor dem Verbindungsprozess des Chips mit der Leiterbahn (1 ) durch Löten, Schweissen und/oder Vergiessen mit Kunststoff erzeugbar ist. 4. A compound according to claim 1, characterized in that the connection and conductor track structures in the metallic conductor foil before the connection process of the chip with the conductor track (1) by soldering, welding and / or casting with plastic can be generated. 5. Verbindung nach einem der Ansprüche 1 bis 4, dadurch gekennzeichnet, dass der Chip (1 ) und das Verbindungsmittel (5,1 1 , 11d) substratseitig eingebaut sind, dass die Öffnung im Substrat (4) vor dem Laminieren mit der Leiterbahnfolie (3) durchgehend bis zur Leiterbahn Oberfläche (3) ausgeführt ist, derart, dass der Chip-Bump (2) darin aufgenommen und mit mindestens einem Teil seiner Höhe eintaucht, wobei die Dicke des Substrates (4) und der Leiterbahn (3) beliebig ist.5. A compound according to any one of claims 1 to 4, characterized in that the chip (1) and the connecting means (5.1, 11d) are mounted on the substrate side, that the opening in the substrate (4) before lamination with the conductor foil ( 3) is carried out continuously to the conductor track surface (3), such that the chip bump (2) is received therein and immersed with at least a portion of its height, wherein the thickness of the substrate (4) and the conductor track (3) is arbitrary , 6. Verbindung nach einem der Ansprüche 1 bis 4, dadurch gekennzeichnet, dass der Chip (1 ) und das Verbindungsmittel (5, 11 , 11d) Leiterbahnseitig eingebaut sind, dass die Öffnung oder Vertiefung (10) in der Leiterbahn ausgeführt ist, derart, das der Chip-Bump oder die Anschlussflächen (2) mit den mit mindestens einen Teil seiner Höhe darin aufgenommen ist, wobei die Dicke des Substrates (4) und die Dicke der Leiterbahn (3) beliebig ist.6. A compound according to any one of claims 1 to 4, characterized in that the chip (1) and the connecting means (5, 11, 11d) are conductor track side installed, that the opening or depression (10) is designed in the conductor track, in such that the chip bump or the pads (2) is received with the at least a part of its height therein, wherein the thickness of the substrate (4) and the thickness of the conductor track (3) is arbitrary. 7. Verbindung nach einem der Ansprüche 1 bis 4, dadurch gekennzeichnet, dass der Chip (1 ) und das Verbindungsmittel (5, 1 1 , 1 1d, 21 ) substratseitig eingebaut sind, dass die Öffnung (1 Of) im Substrat (4) vor dem Laminieren mit der Leiterbahnfolie (3) durchgehend bis zur Leiterbahn Oberfläche (3) ausgeführt ist, derart, dass die ganze Grundfläche des Chips (1) mit den Anschlussflächen mit mindestens einem Teil der Chiphöhe mit den Anschlussflächen bzw. Bump (2) darin eintaucht, wobei die Dicke des Substrates (4) mindestens die Höhe der Anschlussfläche bzw, Bump (2) bis maximal 1 mm über die Höhe des Chips mit den Bump (2) beträgt und die Dicke der Leiterbahn (3) beliebig ist.7. A compound according to any one of claims 1 to 4, characterized in that the chip (1) and the connecting means (5, 1 1, 1 1d, 21) are installed on the substrate side, that the opening (1 Of) in the substrate (4) before lamination with the conductor foil (3) is carried out continuously to the conductor surface (3), such that the entire base of the chip (1) with the pads with at least part of the chip height with the pads or bump (2) therein dips, wherein the thickness of the substrate (4) is at least the height of the pad or bump (2) to a maximum of 1 mm above the height of the chip with the bump (2) and the thickness of the conductor track (3) is arbitrary. 8. Verbindung nach einem der Ansprüche 1 bis 7, dadurch gekennzeichnet, dass die Verbindung der Anschlussflächen bzw. Bumps (2) im Flipchip-Verfahren mit der entsprechenden Leiterbahn (3) über Verbindungsmittel (5,11 ,1 Id) erzeugbar ist, wobei das Verbindungsmittel (5, 1 1 ,1 1 d) auf der Leiterbahn (3) und oder auf den Anschlussflächen bzw. Bumps (2) angelagert sind und dass mindestens ein Teilungsabstand von Leiterbahn (3) zu Leiterbahn (3) zwischen den Anschlussflächen bzw. Bump (2) des Chips (1 ) verläuft.8. A compound according to any one of claims 1 to 7, characterized in that the connection of the pads or bumps (2) in the flip-chip method with the corresponding conductor track (3) via connecting means (5,11, 1 Id) can be generated, wherein the connecting means (5, 1 1, 1 1 d) are deposited on the conductor track (3) and / or on the connecting surfaces or bumps (2) and that at least one pitch of the conductor track (3) to the conductor track (3) between the connecting surfaces or Bump (2) of the chip (1) runs. 9. Verbindung nach Anspruch 8, dadurch gekennzeichnet, dass die Verbindungsmittel (5) leitend, wie Weichlote oder elektrisch leitende Kleber oder nicht leitende Klebstoffe sind.9. A compound according to claim 8, characterized in that the connecting means (5) are conductive, such as soft solders or electrically conductive adhesives or non-conductive adhesives. 10. Verbindung nach Anspruch 8, dadurch gekennzeichnet, dass die Anschlussflächen (2d') bzw. Bumps (2d,) des Chips (1 b) vor dem Einbringen in die Öffnungen (10, 10'; 10a, 10a'; 10b; 10e) mit elektrisch leitenden Verbindungsmitteln (11d), wie Löt- bumps, ausgeführt sind, welche die elektrischen Verbindungen herstellen.10. A compound according to claim 8, characterized in that the connection surfaces (2d ') and bumps (2d,) of the chip (1b) before insertion into the openings (10, 10', 10a, 10a ', 10b, 10e ) with electrically conductive connection means (11d), such as solder bumps, which produce the electrical connections. 1 1. Verbindung nach einem der Ansprüche 1 bis 6, dadurch gekennzeichnet, dass die Verbindung der Anschlussflächen bzw. Bumps (2) mit der entsprechenden Leiterbahn (3) über Verbindungsmittel (21 ), die als metallisch, elektrisch leitende Drähte ausgeführt sind erfolgt, wobei eine intermetallische Verbindung zwischen Verbindungsmittel, Anschlussflächen bzw. Bumps (2) und den Leiterbahnen (3) vorliegt, und wobei das Verbindungsmittel (21 ) und der Chip (1 ) in der korrespondierenden sub- stratseitigen Öffnung (10f) eingetaucht sind, wobei der Chip (1 ) mit seiner den Anschlussflächen / Bump (2) gegenüber liegenden Oberfläche mit den Leiterbahnen klebend verbunden ist, wobei die Substratdicke (4) gleich oder grösser als die Höhe des Chip (1 ) mit dessen Anschlussfüssen (2) und Anschlussdrähten (21 ) ist, und wobei die Leiterbahnen beliebig dick ausgeführt sind.1 1. A compound according to any one of claims 1 to 6, characterized in that the connection of the pads or bumps (2) with the corresponding conductor track (3) via connecting means (21), which are designed as metallic, electrically conductive wires, wherein an intermetallic connection between connecting means, bumps (2) and the conductor tracks (3) is present, and wherein the connecting means (21) and the chip (1) in the corresponding sub stratseitigen opening (10f) are immersed Chip (1) with its the pads / Bump (2) opposite surface is adhesively connected to the tracks, the substrate thickness (4) equal to or greater than the height of the chip (1) with its connection feet (2) and connecting wires (21 ), and wherein the conductor tracks are made arbitrarily thick. 12. Verbindung nach einem der Ansprüche 1 bis 1 1 , dadurch gekennzeichnet, dass die Öffnung (10, 10'; 10b; 10e) im Substrat (4) oder in der Leiterbahn (3) durch Stanzen oder andere mechanische Verfahren oder chemisch oder elektrolytisch vor dem Laminieren des Antennenleiters (3) erzeugbar ist. 12. A compound according to any one of claims 1 to 1 1, characterized in that the opening (10, 10 ', 10b, 10e) in the substrate (4) or in the conductor track (3) by punching or other mechanical processes or chemically or electrolytically before the lamination of the antenna conductor (3) can be generated. 13. Verbindung nach einem der Ansprüche 1 bis 12, dadurch gekennzeichnet, dass die Öffnung (1Of) im Substrat nach der Verbindung mit einer elektrisch isolierenden Kunststoffmasse (6, 16;16c) bis maximal der Höhe der Oberfläche des Substrats (4) verfestigend abgedichtet ist.13. A compound according to any one of claims 1 to 12, characterized in that the opening (1Of) in the substrate after the connection with an electrically insulating plastic compound (6, 16; 16c) to a maximum of the height of the surface of the substrate (4) sealed solidifying is. 14. Verbindung nach einem der vorhergehenden Ansprüche 1 bis 14, dadurch gekennzeichnet, dass die metallischen Leiterbahnen (3, 31; 3a, 3a'; 3b, 3b', 3b", 3b'") auf polymeren Substraten (4; 4a) aus PA oder PE, PET, PEN, PEI, PI oder aus einem Gewebe mit Epoxyd-Kleber laminiert sind und dass die Leiterbahnen (3, 3'; 3a, 3a'; 3b, 3b', 3b", 3b1") aus Kupfer bestehen.14. A compound according to one of the preceding claims 1 to 14, characterized in that the metallic conductor tracks (3, 3 1 , 3 a, 3 a ', 3 b, 3 b', 3 b ", 3 b '") on polymeric substrates (4, 4 a) are laminated from PA or PE, PET, PEN, PEI, PI or a fabric with epoxy adhesive and that the conductor tracks (3, 3 ', 3a, 3a', 3b, 3b ', 3b ", 3b 1 ") from Copper exist. 15. Verbindung nach einem der Ansprüche 1 bis 14, dadurch gekennzeichnet, dass der Chip (1 , 1a, 1 b, 1c) ein RFID (Radio Frequency Identification)-Chip und oder eine Schwingkreisschaltung ist.15. A compound according to any one of claims 1 to 14, characterized in that the chip (1, 1a, 1 b, 1 c) is an RFID (Radio Frequency Identification) chip and or a resonant circuit. 16. Verbindung nach einem der Ansprüche 1 bis 15, dadurch gekennzeichnet, dass der stoffschlüssig mit dem Substrat (4, 4a) verbundene Chip (1 , 1a, 1 b), dessen Anschlussflächen bzw. Bump (2, 2'; 2a, 2a'; 2b) mit den entsprechenden Leiterbahnen über die elektrisch leitenden Verbindungsmittel (11 ,1 1d) verbunden sind, zusätzlich durch einen Schutzüberzug (15) vorzugsweise aus einer Kunststofffolie oder aus Epo- xyd-Lack oder aus einem Kleber verfestigt und feuchtigkeitsdicht abgedeckt ist.16. A compound according to any one of claims 1 to 15, characterized in that the cohesively connected to the substrate (4, 4a) chip (1, 1a, 1 b), the bump surfaces (2, 2 ', 2a, 2a 2b) are connected to the corresponding conductor tracks via the electrically conductive connection means (11, 11d), additionally solidified by a protective cover (15), preferably made of a plastic film or of epoxy paint or of an adhesive, and covered in a moisture-proof manner. 17. Verbindung nach einem der Ansprüche 1 bis 16, gekennzeichnet durch ein Hochfrequenz (HF oder UHF)-Smartcard enthaltend.17. A compound according to any one of claims 1 to 16, characterized by a high frequency (HF or UHF) Smartcard containing. 18. Verbindung nach einem der Ansprüche 1 bis 17, gekennzeichnet durch ein Strap- Chipmodul enthaltend.18. A compound according to any one of claims 1 to 17, characterized by a strap chip module containing. 19. Verbindung nach einem der Ansprüche 1 bis 18, gekennzeichnet durch einen Ultrahochfrequenz-Inlay enthaltend.19. A compound according to any one of claims 1 to 18, characterized by an ultra-high frequency inlay containing. 20. Maschine bzw. Maschinenanlage für die Herstellung einer Verbindung nach einem der Ansprüche 1 bis 19.20. Machine or machinery for the production of a compound according to one of claims 1 to 19. 21. Verfahren zur Herstellung einer Verbindung nach einem der Ansprüche 1 bis 19, dadurch gekennzeichnet dass die Öffnungen im Substrat (4) vor, indes die Antennenstrukturen nach dem Laminieren des Substrats (4) mit der Leiterbahn (3, 3'; 3a, 3a'; 3b, 3b', 3b", 3b'") erzeugt werden. 21. A method for producing a compound according to any one of claims 1 to 19, characterized in that the openings in the substrate (4) before, while the antenna structures after laminating the substrate (4) with the conductor track (3, 3 ', 3a, 3a 3b, 3b ', 3b ", 3b'").
PCT/EP2008/006011 2007-08-27 2008-07-23 Connection of a chip comprising pads and bumps to a substrate comprising metallic strip conductors WO2009026998A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CH01338/07 2007-08-27
CH13382007 2007-08-27

Publications (2)

Publication Number Publication Date
WO2009026998A2 true WO2009026998A2 (en) 2009-03-05
WO2009026998A3 WO2009026998A3 (en) 2009-04-23

Family

ID=40339716

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2008/006011 WO2009026998A2 (en) 2007-08-27 2008-07-23 Connection of a chip comprising pads and bumps to a substrate comprising metallic strip conductors

Country Status (1)

Country Link
WO (1) WO2009026998A2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2290590A3 (en) * 2009-08-14 2011-07-27 Giesecke & Devrient GmbH Portable data carrier
DE102010041917A1 (en) * 2010-10-04 2012-04-05 Smartrac Ip B.V. Method for manufacturing circuit device, involves making contact portion of semiconductor chip to project into contacting tub of strip guard

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2599893B1 (en) * 1986-05-23 1996-08-02 Ricoh Kk METHOD FOR MOUNTING AN ELECTRONIC MODULE ON A SUBSTRATE AND INTEGRATED CIRCUIT CARD
US6440773B1 (en) * 1997-12-22 2002-08-27 Hitachi, Ltd. Semiconductor device
DE10109348A1 (en) * 2001-02-27 2002-09-12 Infineon Technologies Ag Arrangement with a chip having an integrated circuit and a carrier or a carrier element
JP3478281B2 (en) * 2001-06-07 2003-12-15 ソニー株式会社 IC card
WO2005062246A1 (en) * 2003-12-19 2005-07-07 Axalto Sa Identification document

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2290590A3 (en) * 2009-08-14 2011-07-27 Giesecke & Devrient GmbH Portable data carrier
EP2595095A1 (en) * 2009-08-14 2013-05-22 Giesecke & Devrient GmbH Portable data carrier
DE102010041917A1 (en) * 2010-10-04 2012-04-05 Smartrac Ip B.V. Method for manufacturing circuit device, involves making contact portion of semiconductor chip to project into contacting tub of strip guard
DE102010041917A8 (en) * 2010-10-04 2012-06-21 Smartrac Ip B.V. Circuit arrangement and method for its production
DE102010041917B4 (en) * 2010-10-04 2014-01-23 Smartrac Ip B.V. Circuit arrangement and method for its production

Also Published As

Publication number Publication date
WO2009026998A3 (en) 2009-04-23

Similar Documents

Publication Publication Date Title
DE69806515T2 (en) ELECTRONIC DEVICE WITH DISPOSABLE CHIP AND METHOD FOR THE PRODUCTION THEREOF
DE112004001727B4 (en) Method of manufacturing an electronic module
EP0140230B1 (en) Integrated circuit record carrier and process for making the same
EP2350928B1 (en) Method for producing an rfid transponder product, and rfid transponder product produced using the method
DE69824679T2 (en) Non-contact electronic card and method of making such a card
DE19500925A1 (en) Integrated circuit (I.C) card or "chip" card
DE69805404T2 (en) METHOD FOR PRODUCING CONTACTLESS CARDS WITH ANTENNA CONNECTION BY SOLDERED WIRES
DE102009043587A1 (en) Functional laminate
WO1997034247A2 (en) Smart card, connection arrangement and method of producing a smart card
DE10297573B4 (en) Intelligent label and method for its production
EP2338207A1 (en) Rfid transponder antenna
DE102009012255A1 (en) circuitry
DE19709985A1 (en) Smart card for data transmission using contact- or contactless technology
DE102005038132B4 (en) Chip module and chip card
EP1428260B1 (en) Non-conductive substrate forming a strip or a panel, on which a plurality of carrier elements are configured
DE19702532B4 (en) Smart card and method for creating connection contacts on two main surfaces
DE19532755C1 (en) Chip module for chip card used as telephone or identification card
EP4334841A1 (en) Data-bearing card and semi-finished product and wiring layout for same, and method for producing same
DE602004004647T2 (en) METHOD FOR ASSEMBLING AN ELECTRONIC COMPONENT ON A SUBSTRATE
WO2009026998A2 (en) Connection of a chip comprising pads and bumps to a substrate comprising metallic strip conductors
WO2008138531A1 (en) Contactless transmission system, and method for the production thereof
DE10210841B4 (en) Module and method for the production of electrical circuits and modules
DE102006009540A1 (en) Substrate for a substrate-based electronic device and electronic device with improved reliability
DE102005007643A1 (en) Method and device for contacting semiconductor chips on a metallic substrate
EP2595095B1 (en) Portable data carrier

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08774037

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 08774037

Country of ref document: EP

Kind code of ref document: A2

点击 这是indexloc提供的php浏览器服务,不要输入任何密码和下载