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WO2009026364A1 - Numériseur de tension seuil pour réseau de transistors à seuil programmable - Google Patents

Numériseur de tension seuil pour réseau de transistors à seuil programmable Download PDF

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Publication number
WO2009026364A1
WO2009026364A1 PCT/US2008/073716 US2008073716W WO2009026364A1 WO 2009026364 A1 WO2009026364 A1 WO 2009026364A1 US 2008073716 W US2008073716 W US 2008073716W WO 2009026364 A1 WO2009026364 A1 WO 2009026364A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistors
codewords
voltage
ramp
word line
Prior art date
Application number
PCT/US2008/073716
Other languages
English (en)
Inventor
Pantas Sutardja
Original Assignee
Marvell World Trade Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Marvell World Trade Ltd. filed Critical Marvell World Trade Ltd.
Priority to JP2010521997A priority Critical patent/JP5252665B2/ja
Publication of WO2009026364A1 publication Critical patent/WO2009026364A1/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/026—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5002—Characteristic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/563—Multilevel memory reading aspects
    • G11C2211/5634—Reference cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5644—Multilevel memory comprising counting devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/16—Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters 

Definitions

  • a memory cell 14-i may comprise a transistor 50 having a threshold voltage V ⁇ .
  • the transistor 50 may comprise a floating gate G (hereinafter gate G), a source S, and a drain D.
  • FIG. 2B a graph of drain current (I 0 ) versus gate-to-source voltage (V G s) of the transistor 50 is shown.
  • the threshold voltage V ⁇ of the transistor 50 is an intercept on the V G s axis for a predetermined value of the drain current.
  • the threshold voltage V ⁇ is a value of V G s that generates the predetermined drain current.
  • the transistor 50 may have two programmable threshold voltages V T i and V T 2 depending on the amount of charge stored in the gate G.
  • the threshold voltage of the transistor 50 is V ⁇ .
  • the threshold voltage of the transistor 50 is V T2 -
  • a gate voltage i.e., V G s
  • V G s a gate voltage having a value greater than or equal to V ⁇ or V T2 may be necessary to turn on the transistor 50 (i.e., to generate the predetermined drain current).
  • the gate voltage is less than the threshold voltage V ⁇
  • the transistor 50 is off, and the drain current is low (approximately zero).
  • the gate voltage is greater than or equal to the threshold voltage V ⁇
  • the transistor 50 turns on, and the drain current becomes high (i.e., equal to the predetermined drain current corresponding to the V ⁇ ).
  • the value of the gate voltage that generates the high drain current represents the threshold voltage V ⁇ of the transistor 50.
  • a binary search algorithm can be used to measure the threshold voltage.
  • the threshold voltage could be measured to N-bit accuracy in N search cycles, where N is an integer greater than 1.
  • the WL decoder 16 selects a word line comprising memory cells 14-1 , 14-2, ..., 14-i, ..., and 14-n (collectively memory cells 14) when the states of the memory cells are to be determined.
  • Each of the memory cells 14 includes a transistor similar to the transistor 50. The transistors are shown as capacitances C that store the charge in the gates.
  • the staircase voltage can be increased in (2 N - 1 ) steps when the memory cells 14 have 2 N states each.
  • N 2. Accordingly, the staircase voltage that can be increased in three steps.
  • the settling time T s1 of V G s of a first transistor on the selected word line is shown.
  • the first transistor is a transistor of the memory cell 14-1 that is adjacent to the WL decoder 16.
  • the V G s of the first transistor rises and settles to a value equal to the first voltage after time T s i.
  • the current sensing amplifier that measures the drain current that flows through the first transistor must wait for a time period equal to T s1 for the V G s to settle before measuring the drain current.
  • the step of waiting for the settling time before sensing the drain current is repeated for each subsequent stepped up voltage if necessary until the threshold voltage of the first transistor is determined.
  • system further comprises a synchronizing module that synchronizes the N control signals to a clock that is used to generate the codewords.
  • the system further comprises a code converter that converts the codewords to Gray-code codewords.
  • the control module stores one of the Gray-code codewords for one of the N transistors when the corresponding one of the N control signals is generated.
  • the code converter converts one of the Gray-code codewords to one of the codewords.
  • an integrated circuit comprises the system and further comprises a memory array and a word line decoder.
  • the memory array includes the N bit lines, the second word line, and the second N transistors.
  • the word line decoder selects the second word line and outputs the first ramp voltage to the second word line.
  • the IC further comprises the reference word line and the N reference transistors.
  • the word line decoder selects the reference word line and outputs the first and second ramp voltages to the reference word line based on a temperature of the IC.
  • a method comprises outputting a first voltage, which is generated based on received codewords, to a first word line that communicates with N transistors each having programmable threshold voltages, where N is an integer greater than 1.
  • the method further comprises sensing currents through the N transistors via N bit lines, respectively, and generating control signals when current through a corresponding one of the N transistors is greater than or equal to a predetermined current.
  • the method further comprises converting the codewords to Gray-code codewords, storing one of the Gray-code codewords for one of the N transistors when the corresponding one of the N control signals is generated, and converting one of the Gray-code codewords to one of the codewords.
  • the method further comprises generating compensation values for the N bit lines based on the first and second ones of the codewords for the N reference transistors, respectively.
  • the method further comprises generating the compensation values by subtracting the second ones of the codewords from the first ones of the codewords for the N reference transistors, respectively.
  • the method further comprises generating the codewords using a counter, generating the first and second ramp voltages converting the codewords using a digital-to-analog converter (DAC), and incrementing the counter at a different rate when generating the second ramp voltage than when generating the first ramp voltage.
  • DAC digital-to-analog converter
  • the system further comprises control means for determining one of the codewords for one of the N transistors when a corresponding one of the control signals is generated, and generating measured values of the threshold voltages of the N transistors by compensating the ones of the codewords based on at least one of a position of the corresponding ones of the N transistors and a temperature.
  • the first voltage includes a linear ramp voltage.
  • the system further comprises code converting means for converting the codewords to Gray-code codewords.
  • the control means stores one of the Gray-code codewords for one of the N transistors when the corresponding one of the N control signals is generated.
  • the code converting means converts one of the Gray-code codewords to one of the codewords.
  • an integrated circuit comprises the system and further comprises a memory array and a word line decoder.
  • the memory array comprises the N bit lines, the first word line, and the N transistors.
  • control means generates the compensation values by subtracting the second ones of the codewords from the first ones of the codewords for the N reference transistors, respectively.
  • the ramp generating means outputs the first ramp voltage to a second word line that communicates with second N transistors having programmable threshold voltages.
  • the current sensing means sense currents through the second N transistors via the N bit lines, respectively.
  • the control means determines a third one of the codewords for one of the second N transistors when current through one of the second N transistors is greater than or equal to the predetermined current, and generates measured values of the threshold voltages by subtracting the compensation values from the third ones of the codewords, respectively.
  • the system further comprises code converting means for converting the codewords to Gray-code codewords.
  • the computer program further comprises outputting the first ramp voltage to a second word line that communicates with second N transistors having programmable threshold voltages.
  • the computer program further comprises sensing currents through the second N transistors via the N bit lines, respectively.
  • the computer program further comprises determining a third one of the codewords for one of the second N transistors when current through one of the second N transistors is greater than or equal to the predetermined current.
  • the computer program further comprises generating measured values of the threshold voltages by subtracting the compensation values from the third ones of the codewords, respectively.
  • FIG. 5 is a functional block diagram of a memory IC according to the present disclosure.
  • FIG. 6 is a detailed functional block diagram of the memory IC of FIG. 5;
  • the speed of measuring the threshold voltages can be further increased by increasing the resolution of the digital code. Specifically, the time interval between successive digital codes can be reduced to less than a time constant of the word line. For example, a high-resolution linearly stepping digital code may be used. Any resulting inaccuracies in the digital values of the threshold voltages are reduced by generating correction values for each bit line using calibration. The correction codes are combined with the digital values to generate accurate digital values of the threshold voltages. [0141] The present disclosure is organized as follows. First, a linear system model of the word line is introduced, and calibration is briefly discussed. Next, a system for digitizing threshold voltages of transistors is discussed. Thereafter, calibration is discussed in detail.
  • the WL decoder 16 and the BL decoder 18 may select the transistors of the spare row 122.
  • the programming module 1 14 may program all the transistors of the spare row 122 to the predetermined threshold voltage.
  • the current sensing amplifiers 22 and the bit lines may communicate with the transistors of the spare row 122.
  • any reference to transistors during calibration includes transistors of the reference row in the memory array 12 and transistors of the spare row 122.
  • the ramp control module 1 16 decreases the rate of the ramp (ramp rate).
  • a ramp rate is the rate at which the ramp voltage changes.
  • the ramp rate may be V volts/sec during normal operation. Accordingly, the ramp control module 1 16 decreases the ramp rate to less than V volts/sec during calibration.
  • the HDD PCB 302 includes a read/write channel module (hereinafter, "read channel") 309, a hard disk controller (HDC) module 310, a buffer 31 1 , nonvolatile memory 312, a processor 313, and a spindle/VCM driver module 314.
  • the read channel 309 processes data received from and transmitted to the preamplifier device 308.
  • the HDC module 310 controls components of the HDA 301 and communicates with an external device (not shown) via an I/O interface 315.
  • the external device may include a computer, a multimedia device, a mobile computing device, etc.
  • the I/O interface 315 may include wireline and/or wireless communication links.
  • the DVD control module 321 may receive data from the buffer 322, nonvolatile memory 323, the processor 324, the spindle/FM driver module 325, the analog front-end module 326, the write strategy module 327, the DSP module 328, and/or the I/O interface 329.
  • the processor 324 may process the data, including encoding, decoding, filtering, and/or formatting.
  • the DSP module 328 performs signal processing, such as video and/or audio coding/decoding.
  • the processed data may be output to the buffer 322, nonvolatile memory 323, the processor 324, the spindle/FM driver module 325, the analog front-end module 326, the write strategy module 327, the DSP module 328, and/or the I/O interface 329.
  • the DVDA 320 may include a preamplifier device 331 , a laser driver 332, and an optical device 333, which may be an optical read/write (ORW) device or an optical read-only (OR) device.
  • a spindle motor 334 rotates an optical storage medium 335, and a feed motor 336 actuates the optical device 333 relative to the optical storage medium 335.
  • the laser driver When reading data from the optical storage medium 335, the laser driver provides a read power to the optical device 333.
  • the optical device 333 detects data from the optical storage medium 335, and transmits the data to the preamplifier device 331.
  • Memory 364 may include random access memory (RAM) and/or nonvolatile memory.
  • Nonvolatile memory may include any suitable type of semiconductor or solid-state memory, such as flash memory (including NAND and NOR flash memory), phase change memory, magnetic RAM, and multi-state memory, in which each memory cell has more than two states.
  • the storage device 366 may include an optical storage drive, such as a DVD drive, and/or a hard disk drive (HDD).
  • the power supply 362 provides power to the components of the cellular phone 358.
  • the teachings of the disclosure can be implemented in memory 383 and associated circuitry of a set top box 378.
  • the set top box 378 includes a set top control module 380, a display 381 , a power supply 382, memory 383, a storage device 384, and a network interface 385. If the network interface 385 includes a wireless local area network interface, an antenna (not shown) may be included.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne la lecture et le calibrage de réseaux de transistors à seuil programmable multiniveau. Un système comprend un générateur de tension (106), des amplificateurs de lecture de courant (22) et un module de commande (102). Le générateur de tension fournit en sortie une première tension, qui est générée en se basant sur des mots de code reçus, à une première ligne de mots qui communique avec N transistors (14) ayant chacun des tensions à seuil programmable, où N est un entier supérieur à 1. Les amplificateurs de lecture de courant (22) lisent des courants à travers les N transistors via N lignes de bits, respectivement, et génèrent des signaux de commande lorsqu'un courant traversant l'un des N transistors correspondants est supérieur ou égal à un courant prédéterminé. Le module de commande génère des valeurs mesurées des tensions seuil des N transistors en compensant les mots de code en se basant sur au moins une d'une position des transistors correspondants parmi les N transistors et d'une température.
PCT/US2008/073716 2007-08-20 2008-08-20 Numériseur de tension seuil pour réseau de transistors à seuil programmable WO2009026364A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010521997A JP5252665B2 (ja) 2007-08-20 2008-08-20 閾値がプログラム可能なトランジスタアレイ用の閾値電圧デジタル化装置

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US96553507P 2007-08-20 2007-08-20
US60/965,535 2007-08-20
US12/193,380 US7800951B2 (en) 2007-08-20 2008-08-18 Threshold voltage digitizer for array of programmable threshold transistors
US12/193,380 2008-08-18

Publications (1)

Publication Number Publication Date
WO2009026364A1 true WO2009026364A1 (fr) 2009-02-26

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Country Status (5)

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US (5) US7800951B2 (fr)
JP (2) JP5252665B2 (fr)
KR (1) KR101534788B1 (fr)
TW (1) TWI473089B (fr)
WO (1) WO2009026364A1 (fr)

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US8717824B2 (en) 2007-08-20 2014-05-06 Marvell World Trade Ltd. Threshold voltage digitizer for array of programmable threshold transistors
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KR102218722B1 (ko) 2014-06-09 2021-02-24 삼성전자주식회사 불휘발성 메모리 시스템 및 메모리 컨트롤러의 동작 방법
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JP6239665B2 (ja) 2016-03-16 2017-11-29 株式会社東芝 半導体装置
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JP2019169212A (ja) * 2018-03-22 2019-10-03 東芝メモリ株式会社 半導体メモリ装置
US10891080B1 (en) * 2018-06-04 2021-01-12 Mentium Technologies Inc. Management of non-volatile memory arrays
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JP2021047936A (ja) 2019-09-17 2021-03-25 キオクシア株式会社 メモリシステムおよびメモリシステムの制御方法
JP2021047966A (ja) 2019-09-19 2021-03-25 キオクシア株式会社 半導体メモリ装置及び方法
KR102768163B1 (ko) * 2019-11-12 2025-02-19 삼성전자주식회사 위치 정보를 식별하여 셀프 캘리브레이션을 수행하는 메모리 장치 및 그것을 포함하는 메모리 모듈
JP2021140847A (ja) * 2020-03-05 2021-09-16 キオクシア株式会社 半導体記憶装置
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US8149626B2 (en) 2012-04-03
TWI473089B (zh) 2015-02-11
KR20100063018A (ko) 2010-06-10
US20090052256A1 (en) 2009-02-26
US20120176846A1 (en) 2012-07-12
JP5252665B2 (ja) 2013-07-31
US20130322182A1 (en) 2013-12-05
US20110310672A1 (en) 2011-12-22
US7800951B2 (en) 2010-09-21
JP5737695B2 (ja) 2015-06-17
JP2010537360A (ja) 2010-12-02
US8014206B2 (en) 2011-09-06
US8488398B2 (en) 2013-07-16
TW200921670A (en) 2009-05-16
US20110001547A1 (en) 2011-01-06
KR101534788B1 (ko) 2015-07-24
JP2013152780A (ja) 2013-08-08

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