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WO2009006032A2 - Signalisation d'une ligne de données commune et procédé - Google Patents

Signalisation d'une ligne de données commune et procédé Download PDF

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Publication number
WO2009006032A2
WO2009006032A2 PCT/US2008/067446 US2008067446W WO2009006032A2 WO 2009006032 A2 WO2009006032 A2 WO 2009006032A2 US 2008067446 W US2008067446 W US 2008067446W WO 2009006032 A2 WO2009006032 A2 WO 2009006032A2
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WO
WIPO (PCT)
Prior art keywords
data
circuit
frequency
common
data line
Prior art date
Application number
PCT/US2008/067446
Other languages
English (en)
Other versions
WO2009006032A3 (fr
Inventor
Ashok Kumar Kapoor
Original Assignee
Dsm Solutions, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dsm Solutions, Inc. filed Critical Dsm Solutions, Inc.
Publication of WO2009006032A2 publication Critical patent/WO2009006032A2/fr
Publication of WO2009006032A3 publication Critical patent/WO2009006032A3/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
    • H04L27/12—Modulator circuits; Transmitter circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
    • H04L27/14—Demodulator circuits; Receiver circuits
    • H04L27/144—Demodulator circuits; Receiver circuits with demodulation using spectral properties of the received signal, e.g. by using frequency selective- or frequency sensitive elements
    • H04L27/148—Demodulator circuits; Receiver circuits with demodulation using spectral properties of the received signal, e.g. by using frequency selective- or frequency sensitive elements using filters, including PLL-type filters

Definitions

  • the present invention relates generally to integrated circuits, and more particularly to a common data line signaling and method for semiconductor devices.
  • each data transmitting circuit has a dedicated data line wiring connected between the data transmitting circuit and the data receiving circuit.
  • a large area of the semiconductor device is consumed by the large number of data line wirings.
  • FIG. 1 An example illustrating the conventional approach of data line wiring and data transmission in a semiconductor device is set forth in a block schematic diagram in FIG. 1 and given the general reference character 100.
  • Semiconductor device 100 includes data transmission circuits 110 to 140, and data receiving circuits 160 to 190.
  • Data transmission circuit 110 transmits data to data receiving circuit 160 along a dedicated data line wiring 150.
  • Data transmission circuit 120 transmits data to data receiving circuit 170 along a dedicated data line wiring 152.
  • Data transmission circuit 130 transmits data to data receiving circuit 180 along a dedicated data line wiring 156.
  • Data transmission circuit 140 transmits data to data receiving circuit 190 along a dedicated data line wiring 154. Although only four data transmission circuits (110 to 140) and four data receiving circuits (160 to 190) are shown, semiconductor device 100 can include many such circuits with each data transmission circuit including a dedicated data line wiring.
  • each data line wiring typically uses the same wiring layer, for example a metal wiring layer.
  • the data line wiring can also be typically laid out in a wiring channel, which may be excluded from having circuitry such as transistors. In such a case, the data line wiring can consume a lot of area, which makes the semiconductor device 100 have a larger "die size". With a larger "die size", fewer chips (i.e. semiconductor devices) can be manufactured on a single silicon wafer, which increases manufacturing costs.
  • a semiconductor device including a common data line in which data may be simultaneously transmitted to and from transmitter/receiver circuits may include a plurality of common data lines. Each common data line may be coupled to a plurality of data transmitter/receiver circuits, respectively. Data may be transmitted from a first data transmitter/receiver circuit on a first common data line to a second data transmitter/receiver circuit on a second common data line while data is being transmitted from another data transmitter/receiver circuit from any common data line to a third data transmitter/receiver circuit on the first common data line. In this way, the number of data lines may be reduced.
  • data may be provided to a common data line after being frequency modulated.
  • data may be provided to a common data line after undergoing a phase shift modulation.
  • data may be provided to a common data line after an amplitude modulation is performed.
  • a bridge circuit may be provided between a first common data line and a second common data line.
  • FIG. 1 is a block schematic diagram of conventional approach of data line wiring and data transmission in a semiconductor device.
  • FIG. 2 is a block schematic diagram of a common data line sharing circuit according to an embodiment.
  • FIG. 3 is a block schematic diagram of a transmitter circuit according to an embodiment.
  • FIG. 4 is a block schematic diagram of a receiver circuit according to an embodiment.
  • FIG. 5 is a graph illustrating a frequency response of a band pass filter according to an embodiment.
  • FIG. 6 is a frequency spectrum diagram according to an embodiment indicating the frequency spectrum of modulated data signals output from transmitter circuits.
  • FIG. 7 is a timing diagram illustrating the operation of data line sharing circuit according to an embodiment.
  • FIG. 8 is a block schematic diagram of a common data line sharing circuit according to an embodiment is set forth.
  • FIG. 9 is a block schematic diagram of a transmitter circuit according to an embodiment.
  • FIG. 10 is a block schematic diagram of a receiver circuit according to an embodiment.
  • FIG. 11 is a block schematic diagram of a common data line signaling system according to an embodiment.
  • FIG. 12 is a block schematic diagram of a data transmitter/receiver circuit according to an embodiment.
  • FIG. 13 is a block schematic diagram of a data transmitter/receiver circuit according to an embodiment.
  • FIG. 14 is a block schematic diagram of a common data line signaling system according to an embodiment.
  • FIG. 2 a block schematic diagram of a common data line sharing circuit according to an embodiment is set forth and given the general reference character 200.
  • Common data line sharing circuit 200 can be integrated on a single semiconductor device.
  • Common data line sharing circuit 200 can include transmitter circuits (210 to 240) and receiver circuits (260 to 290). Transmitter circuits (210 to 240) and receiver circuits (260 to 290) may share a common data line 250.
  • Common data line 250 can be a data line wiring using, for example, a metal wiring layer or the like in a semiconductor device.
  • Each transmitter circuit may transmit data that has undergone a frequency modulation at a predetermined carrier frequency.
  • Transmitter circuit 210 may transmit data (Sl) that has undergone a frequency modulation at a carrier frequency fi.
  • Transmitter circuit 220 may transmit data (S2) that has undergone a frequency modulation at a carrier frequency f 2 .
  • Transmitter circuit 230 may transmit data (S3) that has undergone a frequency modulation at a carrier frequency f 3 .
  • Transmitter circuit 240 may transmit data (S4) that has undergone a frequency modulation at a carrier frequency f 4 .
  • Carrier frequencies are different distinct frequencies in an operational frequency spectrum of the components (such as bipolar junction transistors) used to configure the transmission circuits (210 to 240).
  • the bipolar junction transistors may have a cutoff frequency of about 30-50 GHz.
  • Each receiver circuit (260 to 290) can allow a respective predetermined frequency band to pass from a predetermined transmitter circuit (210 to 240).
  • Receiver circuit 260 may allow a band around predetermined frequency fj to pass while filtering out the frequencies (f 2 , f 3 , and f 4 ).
  • Receiver circuit 270 may allow a band around predetermined frequency f 2 to pass while filtering out the frequencies (fi, f 3 , and f 4 ).
  • Receiver circuit 280 may allow a band around predetermined frequency f 3 to pass while filtering out the frequencies (fj ,f 2 , and f 4 ).
  • Receiver circuit 290 may allow a band around predetermined frequency f 4 to pass while filtering out the frequencies (f ⁇ , f 2 , and f 3 ). In this way, transmitter circuits (210 to 240) can transmit data to a predetermined receiver circuit (260 to 290) along a common data line 250 by transmitting data at a respective predetermined carrier frequency (fi to f 4 ).
  • the common data line sharing circuit 200 of FIG. 2 shows four transmitter circuits (210 to 240) and four receiver circuits (260 to 290), there may be any number of transmitter and/or receiver circuits having predetermined carrier frequencies.
  • Transmitter circuit 300 may be used as the transmitter circuits (210 to 240) in the common data line sharing circuit 200 of FIG. 2.
  • Transmitter circuit 300 can include a data circuit 310 and a frequency modulator 320.
  • Data circuit 310 may serially provide a stream of digital data 312, corresponding to data output Dn, at a predetermined clock frequency to frequency modulator 320.
  • Frequency modulator 320 may perform a frequency modulation operation on the stream of data.
  • the frequency modulator may receive a base frequency modulation signal at a frequency of f c + (n-l) ⁇ f and a digital data modulating frequencies (f s o and f sl ) where n is from 1 to N and N is the number of transmitter circuits (210 to 240), f c may be a base carrier frequency, and ⁇ f may be a frequency spectrum spacing between the modulated digital data signals (Sl to S4).
  • Digital data modulating frequencies (f s0 and f sl ) correspond to added frequency for a data zero (f s0 ) and an added frequency for a data one (f s i).
  • a resultant modulated data signal 322 can then be transmitted to the common data line (for example, common data line 250 of FIG. 2).
  • the modulated data signal 322 can correspond to a modulated digital data signal Sn (i. e. Sl to S4, in FIG. 2).
  • Receiver circuit 400 may be used as receiver circuits (260 to 290) in the common data line sharing circuit 200 of FIG. 2.
  • Receiver circuit 400 can include a band pass filter 410, a demodulator circuit 420, a data converter 430, and a data circuit 440.
  • Band pass filter 410 can receive frequency modulated data 322 and may provide a band pass filtering function around a predetermined carrier frequency f n . In other words, frequencies around the predetermined carrier frequency f n are allowed to pass to demodulator circuit 420 while other frequencies are attenuated and essentially do not pass through.
  • the predetermined carrier frequency f n as a predetermined frequency (fi to f 4 )
  • Frequency modulated data 322 can be received by a common data line (for example, common data line 250 of FIG. 2).
  • Demodulator circuit 420 receives the modulated data signal 412 and removes the predetermined carrier frequency f n to provide the demodulated data (i.e. the original data from data circuit 310) to data converter 430.
  • demodulator circuit 420 may provide a signal to data converter 430 having only data modulating frequency f s i if the data is a data one and data modulating frequency f s0 if the data is a data zero.
  • Data converter 430 may detect the data modulating frequency (f s o or f sl ) of the received signal to provide data (i.e. the stream of digital data 312 originally provided by data circuit 310.
  • Data converter 430 may be an analog to digital converter.
  • the frequency response loss curve 510 of FIG. 5 can be a frequency response of a band pass filter 410 of FIG. 4 for a predetermined carrier frequency f n of a transmitter circuit (210 to 240).
  • Band pass filter 410 can have a band pass section 520 in the frequency response loss curve 510. Essentially, frequencies around the predetermined carrier frequency f n (to include the peak frequency deviation of the predetermined modulated data signal) are allowed to pass through the band pass filter 410 while attenuating or essentially blocking other frequencies.
  • Transmitter circuits (210 to 240) operate in a different frequency domain. This may be accomplished by separating the carrier frequencies (f ls f 2 , f 3 , and f 4 ) sufficiently so that respective peak frequency deviation of each modulated signal does not result in an overlap, as will be explained with reference to FIG. 6 in conjunction with FIG. 2.
  • FIG. 6 a frequency spectrum diagram according to an embodiment indicating the frequency spectrum of modulated data signals (S 1 to S4) output from transmitter circuits (210 to 240) of FIG. 2.
  • Frequency modulator circuit 320 of transmitter circuit 210 may further provide digital data modulating frequency (f s o or f s i) depending on whether the data being transmitted has a data zero or a data one logic value
  • Receiver circuit 260 may include a band pass filter (such as band pass filter 410, for example) that allows the band pass frequencies BPl to pass through while attenuating and thereby blocking other signals. In this way, only signals in the frequency spectrum transmitted from transmitter circuit 210 may be received by receiver circuit 260.
  • Frequency modulator circuit 320 of transmitter circuit 220 may further provide digital data modulating frequency (f s0 or f s i) depending on whether the data being transmitted has a data zero or a data one logic value.
  • Receiver circuit 270 may include a band pass filter (such as band pass filter 410, for example) that allows the band pass frequencies BP2 to pass through while attenuating and thereby blocking other signals. In this way, only signals in the frequency spectrum transmitted from transmitter circuit 220 may be received by receiver circuit 270.
  • Frequency modulator circuit 320 of transmitter circuit 230 may further provide digital data modulating frequency (f s o or f sl ) depending on whether the data being transmitted has a data zero or a data one logic value.
  • Receiver circuit 280 may include a band pass filter (such as band pass filter 410, for example) that allows the band pass frequencies BP3 to pass through while attenuating and thereby blocking other signals. In this way, only signals in the frequency spectrum transmitted from transmitter circuit 230 may be received by receiver circuit 280.
  • Frequency modulator circuit 320 of transmitter circuit 240 may further provide digital data modulating frequency (f s0 or f s i) depending on whether the data being transmitted has a data zero or a data one logic value.
  • Receiver circuit 290 may include a band pass filter (such as band pass filter 410, for example) that allows the band pass frequencies BP4 to pass through while attenuating and thereby blocking other signals. In this way, only signals in the frequency spectrum transmitted from transmitter circuit 240 may be received by receiver circuit 290.
  • guard band frequency range between the frequency spectrums for each modulated data signal (Sl to S4). This is to prevent any signal interference due to, for example, the inability to create a band pass filter with sharp enough edges and thereby increase signal integrity.
  • FIG. 7 A timing diagram illustrating the operation of data line sharing circuit 200 according to an embodiment is set forth in FIG. 7.
  • a data line sharing circuit 200 of FIG. 2 including transmitter circuits (260 to 290), such as a transmitter circuit 300 of FIG. 3, and receiver circuits (260 to 290), such as receiver circuit 400 of FIG. 3 will now be described with reference to the timing diagram of FIG. 7 in conjunction with FIGS. 2-6.
  • the timing diagram of FIG. 7 shows the data output Dn (not shown) comprising data outputs (Dl to D4) of the respective data circuits 310, and modulated data signals (Sl to S4) of respective transmitter circuits (210 to 240).
  • Transmitter circuit 210 may include a data circuit 310 that provides a data signal Dl and a frequency modulator 320 that provides a modulated data signal Sl.
  • Transmitter circuit 220 may include a data circuit 310 that provides a data signal D2 and a frequency modulator 320 that provides a modulated data signal S2.
  • Transmitter circuit 230 may include a data circuit 310 that provides a data signal D3 and a frequency modulator 320 that provides a modulated data signal S3.
  • Transmitter circuit 240 may include a data circuit 310 that provides a data signal D4 and a frequency modulator 320 that provides a modulated data signal S4.
  • data circuit 310 in transmitter circuit 210 can provide a data signal Dl having a logic "1" level.
  • Frequency modulator 320 in transmitter circuit 210 can provide a modulated signal Sl having frequency of f c + f sl .
  • transmitter circuits (220 to 240) may be disabled and provide modulated data signals (S2 to S4) having a high impedance state. Because transmitter circuits (220 to 240) are disabled, the data signals (D2 to D4) are in a "don't care" condition.
  • the band pass filter 410 in receiver circuit 260 allows the modulated data signal S 1 to pass through because the frequency of data signal S 1 falls within the band pass frequency BPl.
  • modulated data signal Sl can be passed to the demodulator 420 of receiver circuit 260.
  • Demodulator 420 removes the predetermined carrier frequency f c to provide a signal having a digital data modulating frequency f sl corresponding to a data one (i.e. a logic "1" level) to the data converter 430 of receiver circuit 260.
  • Data converter 430 may detect the data modulating frequency f sl to provide a digital data one to data circuit 440.
  • data circuit 310 in transmitter circuit 210 can provide a data signal Dl that transitions from a logic "1" level to the logic "0" level.
  • Frequency modulator 320 in transmitter circuit 210 can provide a modulated signal Sl having a frequency of f c + f s0 .
  • transmitter circuits (220 to 240) may still be disabled and provide modulated data signals (S2 to S4) having a high impedance state. Because transmitter circuits (220 to 240) are disabled, the data signals (D2 to D4) remain in a "don't care" condition.
  • the band pass filter 410 in receiver circuit 260 allows the modulated data signal Sl to pass through because the frequency of data signal Sl falls within the band pass frequency BPl.
  • modulated data signal Sl can be passed to the demodulator 420 of receiver circuit 260.
  • Demodulator 420 removes the predetermined carrier frequency f c to provide a demodulated data signal having a digital data modulating frequency f s0 corresponding to a data zero (i.e. a logic "0" level) to the data converter 430 of receiver circuit 260.
  • Data converter 430 may detect the data modulating frequency f s0 to provide a digital data zero to data circuit 440.
  • data circuit 310 in transmitter circuit 210 can provide a data signal Dl that remains in the logic "0" level and the operation of transmitter circuit 210 and receiver circuit 360 can remain the same.
  • transmitter circuit 220 becomes enabled and data circuit 310 in transmitter circuit 220 can provide a data signal D2 having a logic "1" level.
  • Frequency modulator 320 in transmitter circuit 220 can provide a modulated signal S2 having a frequency of f c + ⁇ f + f s j.
  • transmitter circuits (330 and 340) may be disabled and provide modulated data signals (S3 and S4) having a high impedance state. Because transmitter circuits (330 and 340) are disabled, the data signals (D3 and D4) are in a "don't care" condition.
  • the band pass filter 410 in receiver circuit 260 allows the modulated data signal S 1 to pass through because the frequency of modulated data signal Sl falls within the band pass frequency BPl (however, modulated data signal S2 does not pass through because the frequency of modulated data signal S2 does not fall within the band pass frequency BPl).
  • modulated data signal Sl can be passed to the demodulator 420 of receiver circuit 260.
  • Demodulator 420 removes the predetermined carrier frequency f c to provide a signal having a digital data modulating frequency f sl corresponding to a data one (i.e. a logic "1" level) to the data converter 430 of receiver circuit 260.
  • Data converter 430 may detect the data modulating frequency f sl to provide a digital data one to data circuit 440. Also at this time, the band pass filter 410 in receiver circuit 270 allows the modulated data signal S2 to pass through because the frequency of modulated data signal S2 falls within the band pass frequency BP2 (however, modulated data signal Sl does not pass through because the frequency of modulated data signal S 1 does not fall within the band pass frequency BPl). In this way, modulated data signal S2 can be passed to the demodulator 420 of receiver circuit 270. Demodulator 420 removes the predetermined carrier frequency f c + ⁇ f to provide a signal having a digital data modulating frequency f sl corresponding to a data one (i.e.
  • Data converter 430 may detect the data modulating frequency f s i to provide a digital data one to data circuit 440.
  • modulated data signals (Sl and S3) do not fall within the band pass frequencies (BP3 to BP4) of band pass filters 410 in respective receiver circuits (280 and 290)
  • modulated data signals (Sl and S2) are essentially blocked from passing to the respective frequency demodulators 420 and no data is received by receiver circuits (280 and 290).
  • transmitter circuit 210 is transmitting data through common data line 250 to receiver circuit 260 at the same time transmitter circuit 220 is transmitting data through common data line 250 to receiver circuit 270.
  • data circuit 310 in transmitter circuit 210 can provide a data signal Dl that transitions from a logic "0" level to the logic "1" level.
  • Frequency modulator 320 in transmitter circuit 210 can provide a modulated signal Sl having a frequency of f c + f sl .
  • data circuit 310 in transmitter circuit 220 can provide a data signal D2 that transitions from a logic "1" level to the logic "0" level.
  • Frequency modulator 320 in transmitter circuit 220 can provide a modulated signal S2 having a frequency of f c + ⁇ f + f s o- Also, at time t3, transmitter circuit 230 becomes enabled and data circuit 310 in transmitter circuit 230 can provide a data signal D3 having a logic "1" level. Frequency modulator 320 in transmitter circuit 230 can provide a modulated signal S3 having a frequency of f c + 2 ⁇ f + f sl . At this time, transmitter circuit 240 may be disabled and provide a modulated data signal S4 having a high impedance state. Because transmitter circuit 240 is disabled, the data signal D4 is in a "don't care" condition.
  • the band pass filter 410 in receiver circuit 260 allows the modulated data signal Sl to pass through because the frequency of modulated data signal Sl falls within the band pass frequency BPl (however, modulated data signals (S2 and S3) do not pass through because the frequency of modulated data signals (S2 and S3) do not fall within the band pass frequency BPl).
  • modulated data signal Sl can be passed to the demodulator 420 of receiver circuit 260.
  • Demodulator 420 removes the predetermined carrier frequency f c to provide a demodulated data signal having a digital modulating frequency f sl corresponding to a data one (i.e. a logic "1" level) to the data converter 430 of receiver circuit 260.
  • the band pass filter 410 in receiver circuit 270 allows the modulated data signal S2 to pass through because the frequency of modulated data signal S2 falls within the band pass frequency BP2 (however, modulated data signals (Sl and S3) do not pass through because the frequency of modulated data signals (Sl and S3) do not fall within the band pass frequency BP2).
  • modulated data signal S2 can be passed to the demodulator 420 of receiver circuit 270.
  • Demodulator 420 removes the predetermined carrier frequency f c + ⁇ f to provide a demodulated data signal having a digital data modulating frequency f s0 corresponding to a data zero (i.e. a logic "0" level) to the data converter 430 of receiver circuit 270.
  • Data converter 430 may detect the data modulating frequency f s0 to provide a digital data zero to data circuit 440. Also at this time, the band pass filter 410 in receiver circuit 280 allows the modulated data signal S3 to pass through because the frequency of modulated data signal S3 falls within the band pass frequency BP3 (however, modulated data signals (Sl and S2) do not pass through because the frequency of modulated data signals (Sl and S2) do not fall within the band pass frequency BP3). In this way, modulated data signal S3 can be passed to the demodulator 420 of receiver circuit 280.
  • Demodulator 420 removes the predetermined carrier frequency f e + 2 ⁇ f to provide a demodulated data signal having a digital data modulating frequency f sl corresponding to a data one (i.e. a logic "1" level) to the data converter 430 of receiver circuit 280.
  • Data converter 430 may detect the data modulating frequency f sl to provide a digital data one to data circuit 440.
  • modulated data signals (Sl toS3) do not fall within the band pass frequency BP4 of band pass filters 410 in respective receiver circuit 290, modulated data signals (Sl to S3) are essentially blocked from passing to the respective modulator 420 and no data is received by receiver circuit 290.
  • transmitter circuit 210 is transmitting data through common data line 250 to receiver circuit 260 at the same time transmitter 220 is transmitting data through common data line 250 to receiver circuit 270 and transmitter circuit 230 is transmitting data through common data line 250 to receiver circuit 280.
  • data signals Dl to D3 may transition various times.
  • respective modulated data signals (Sl to S3) may have increasing or decreasing frequencies accordingly, however, the frequencies of modulated data signals (Sl to S3) stay within the respective band pass frequencies (BPl to BP3). In this way, the transmitter circuits (210 to 230) can transmit data to the proper respective receiver circuits (260 to 290).
  • data circuit 310 in transmitter circuit 210 can provide a data signal Dl that transitions remain at a logic "1".
  • Frequency modulator 320 in data circuit 210 can provide a modulated signal Sl having a frequency of f c + f s i.
  • data circuit 310 in transmitter circuit 220 can provide a data signal D2 that has a logic "0" level.
  • Frequency modulator 320 in data circuit 220 can provide a modulated signal S2 having a frequency of f c + ⁇ f + f s0 .
  • Data circuit 310 in transmitter circuit 230 can provide a data signal D3 that transitions from a logic "0" level to the logic "1" level.
  • Frequency modulator 320 in data circuit 230 can provide a modulated signal S3 having a frequency of f c + 2 ⁇ f + f sl . Also, at time t4, transmitter circuit 240 becomes enabled and data circuit 310 in transmitter circuit 240 can provide a data signal D4 having a logic "0" level. Frequency modulator 320 in transmitter circuit 240 can provide a modulated signal S4 having frequency of f c + 3 ⁇ f + f s o-
  • the band pass filter 410 in receiver circuit 260 allows the modulated data signal S 1 to pass through because the frequency of modulated data signal Sl falls within the band pass frequency BPl (however, modulated data signals (S2, S3, and S3) do not pass through because the frequency of modulated data signals (S2, S3, and S3) do not fall within the band pass frequency BPl).
  • modulated data signal S 1 can be passed to the demodulator 420 of receiver circuit 260.
  • Demodulator 420 removes the predetermined carrier frequency f c to provide a signal having a digital data modulating frequency f sl corresponding to a data one (i.e. a logic "1" level) to the data converter 430 of receiver circuit 260.
  • Data converter 430 may detect the data modulating frequency f sl to provide a digital data one to data circuit 440. Also at this time, the band pass filter 410 in receiver circuit 270 allows the modulated data signal S2 to pass through because the frequency of modulated data signal S2 falls within the band pass frequency BP2 (however, modulated data signals (Sl, S3, and S4) do not pass through because the frequency of modulated data signals (Sl, S3, and S4) do not fall within the band pass frequency BP2). In this way, modulated data signal S2 can be passed to the demodulator 420 of receiver circuit 270.
  • Demodulator 420 removes the predetermined carrier frequency f c + ⁇ f to provide a signal having a digital data modulating frequency f s0 corresponding to a data zero (i.e. a logic "0" level) to the data converter 430 of receiver circuit 270.
  • Data converter 430 may detect the data modulating frequency f s o to provide a digital data zero to data circuit 440.
  • the band pass filter 410 in receiver circuit 280 allows the modulated data signal S3 to pass through because the frequency of modulated data signal S3 falls within the band pass frequency BP3 (however, modulated data signals (S 1 , S2, and S4) do not pass through because the frequency of modulated data signals (Sl, S2, and S4) do not fall within the band pass frequency BP3).
  • modulated data signal S3 can be passed to the demodulator 420 of receiver circuit 280.
  • Demodulator 420 removes the predetermined carrier frequency f c + 2 ⁇ f to provide a demodulated data signal having a digital data modulating frequency f sl corresponding to a data one (i.e.
  • the band pass filter 410 in receiver circuit 290 allows the modulated data signal S4 to pass through because the frequency of modulated data signal S4 falls within the band pass frequency BP4 (however, modulated data signals (Sl, S2, and S3) do not pass through because the frequency of modulated data signals (Sl, S2, and S3) do not fall within the band pass frequency BP4). In this way, modulated data signal S4 can be passed to the demodulator 420 of receiver circuit 290.
  • Demodulator 420 removes the predetermined carrier frequency f c + 3 ⁇ f to provide a demodulated data signal having a digital data modulating frequency f s0 corresponding to a data zero (i.e. a logic "0" level) to the data converter 430 of receiver circuit 290.
  • Data converter 430 may detect the data modulating frequency f s0 to provide a digital data zero to data circuit 440.
  • transmitter circuits (210 to 240) are all simultaneously transmitting data through common data line 250 to respective receiver circuits (260 to 290).
  • any number of transmitter circuits may simultaneously transmit data through a common data line 250 to respective receiver circuits (260 to 290). Although only four transmitter circuits (210 to 240) and four receiver circuits (260 to 290) are shown, there may be as many transmitter circuits (210 to 240) and receiver circuits (260 to 290) as can be accommodated by the operable frequency spectrum.
  • any of the respective transmitter circuits (210 to 240) may begin the transmission of their respective data at any time regardless of the simultaneous transmission of data by any other of the respective transmitter circuits (210 to 240) and the transmitted data may be received from common data line 250 at a respective receiver circuit (260 to 290) even when data is being simultaneously transmitted to any of the other receiver circuits (260 to 290).
  • FIG. 8 a block schematic diagram of a common data line sharing circuit according to an embodiment is set forth and given the general reference character 800.
  • Common data line sharing circuit 800 can be integrated on a single semiconductor device.
  • Common data line sharing circuit 800 can include transmitter circuits (810 to 840) and receiver circuits (860 to 890). Transmitter circuits (810 to 840) and receiver circuits (860 to 890) may share a common data line 850.
  • Common data line 850 can be a data line wiring using, for example, a metal wiring layer or the like in a semiconductor device.
  • Each transmitter circuit (810 to 840) may transmit coded data in a predetermined timing window.
  • Transmitter circuit 810 may transmit data that has coded data in a timing window T 1 .
  • Transmitter circuit 820 may transmit data that has coded data in a timing window T 2 .
  • Transmitter circuit 830 may transmit data that has coded data in a timing window T 3 .
  • Transmitter circuit 840 may transmit data that has coded data in a timing window T 4 .
  • Timing windows (Tj, T 2 , T 3; and T 4 ) are different non-overlapping timing windows.
  • Each receiver circuit (860 to 890) include a timing monitoring operation. In this way, each receiver circuit (860 to 890) can receive coded data from a predetermined transmitter circuit (810 to 840). Receiver circuit 860 may receive coded data in timing window Tj. Receiver circuit 870 may receive coded data in timing window T 2 . Receiver circuit 880 may receive coded data in timing window T 3 . Receiver circuit 890 may receive coded data in timing window T 4 . In this way, transmitter circuits (810 to 840) can transmit coded data to a predetermined receiver circuit (860 to 890) along a common data line 850 by transmitting data at a respective predetermined timing window (Ti to T 4 ). Note although the common data line sharing circuit 800 of FIG. 7, shows four transmitter circuits (810 to 740) and four receiver circuits (860 to 890), there may be any number of transmitter and/or receiver circuits having predetermined timing windows.
  • Transmitter circuit 900 may be used as the transmitter circuits (810 to 840) in the common data line sharing circuit 800 of FIG. 8.
  • Transmitter circuit 900 can include a data circuit 910, a coder circuit 920, and a timing circuit 930.
  • Data circuit 910 may provide data 912 to coder circuit 920.
  • Coder circuit may provide coded data signal 932 during a predetermined timing window TN determined by timing circuit 930. Coded data signal 932 can then be transmitted to the common data line (for example, common data line 850 of FIG. 8).
  • a coder may code the data received from data circuit 910 and store it locally until it is transmitted during the allocated timing window.
  • Receiver circuit 1000 may be used as receiver circuits (860 to 890) in the common data line sharing circuit 800 of FIG. 8.
  • Receiver circuit 1000 can include a timing monitor circuit 1010, a decoder 1020, and a data circuit 1030.
  • Timing monitor circuit 1010 can pass coded data 932 to decoder 1020 during a predetermined timing window T N .
  • Decoder circuit 1020 can receive the coded data 932 and provide output data 1022 to data circuit 1030.
  • timing monitor 1010 to provide a predetermined timing window TN as a respective predetermined timing window (Ti to T 4 )
  • a respective receiver circuit (860 to 890) By using timing monitor 1010 to provide a predetermined timing window TN as a respective predetermined timing window (Ti to T 4 ), only the coded data transmitted from a transmitter circuit (810 to 840) can be received by a respective receiver circuit (860 to 890).
  • FIG. 11 a common data line signaling system according to an embodiment is set forth in a block schematic diagram and given the general reference character 1100.
  • Common data line signaling system 1100 may include data transmitter/receiver circuits (TR-11 to TR-mn) and bridge circuits (BCl to BCm).
  • a column of data transmitter/receiver circuits (TR-I l to TR-In) may be connected to a common data line DLL
  • a column of data transmitter/receiver circuits (TR-21 to TR-2n) may be connected to a common data line DL2.
  • a column of data transmitter/receiver circuits (TR-31 to TR-3n) may be connected to a common data line DL3.
  • Bridge circuit BCl may have an input /output terminal connected to common data line DLl and an input/output terminal connected to a bridge line BLl.
  • Bridge circuit BC2 may have an input/output terminal connected to bridge line BLl, an input output terminal connected to common data line DL2, and an input/output terminal connected to bridge line BL2.
  • Bridge circuit BC3 may have an input/output terminal connected to bridge line BL2, an input/output terminal connected to common data line DL3, and an input/output terminal connected to bridge line BL3.
  • Bridge circuit BCm may have an input/output terminal connected to bridge line BL(m-l) and an input output terminal connected to common data line DLm.
  • Data transmitter/receiver circuit 1200 may be used for each of data transmitter/receiver circuits (TR-I l to TR-mn).
  • Data transmitter/receiver circuit 1200 may include a data transmitter circuit 1205 and a data receiver circuit 1235.
  • Data transmitter circuit 1205 may include a data circuit 1210, a frequency modulator 1220, and a phase shifter 1230.
  • Data circuit 1210 may serially provide a stream of digital data 1212 at a predetermined clock frequency to frequency modulator 1220.
  • Frequency modulator 1220 may perform a frequency modulation operation on the stream of data.
  • the frequency modulator may receive a base frequency modulation signal at a frequency of f c + (k-l) ⁇ f and a digital data modulating frequencies (f s o and f sl ) where k is from 1 to n and n is the number of transmitter circuits (TR-I l to TR-mn) connected to a common data line (DLl to DLm), f c may be a base carrier frequency, and ⁇ f may be a frequency spectrum spacing between the modulated digital data signals.
  • Phase shifter 1230 may then perform a phase shifting operation on the modulated data signal 1222 to provide a phase shifted modulated data signal Sxy.
  • a resultant phase shifted modulated data signal Sxy can then be transmitted to a common data line (for example, a respective common data line (DLl to DLm) of FIG. 11).
  • a common data line for example, a respective common data line (DLl to DLm) of FIG. 11).
  • Data receiver circuit 1235 may include a band pass filter 1240, a demodulator circuit 1250, a data converter 1260, and a data circuit 1270.
  • Band pass filter 1240 can receive phase shifted frequency modulated data Sxy from a common data line (for example, a respective common data line (DLl to DLm) and may provide a band pass filtering function around a predetermined carrier frequency f n .
  • a common data line for example, a respective common data line (DLl to DLm)
  • a band pass filtering function around a predetermined carrier frequency f n In other words, frequencies around the predetermined carrier frequency f n are allowed to pass to demodulator circuit 1250 while other frequencies are attenuated and essentially do not pass through.
  • Phase shifted frequency modulated data Sxy can be received by a respective common data line (DLl to DLm).
  • Demodulator circuit 1250 receives the modulated data signal 1242 and removes the predetermined carrier frequency f n to provide the demodulated data (i.e. the original data from data circuit 1210) to data converter 1260.
  • demodulator circuit 1250 may provide a signal to data converter 1260 having only data modulating frequency f sl if the data is a data one and data modulating frequency f s o if the data is a data zero.
  • Data converter 1260 may detect the data modulating frequency (f s o or f s j) of the received signal to provide data (i.e. the stream of digital data 1212 originally provided by a data circuit 1210.
  • Data converter 1260 may be an analog to digital converter.
  • data transmitter/ receiver circuits TR-In, TR-2n, TR-3n, and TR-mn
  • a carrier frequency may be identified with a predetermined row of
  • phase shifter 1230 may provide a predetermined phase shift in accordance as to which column of data transmitter/receiver circuits (TR- 11 to TR-In, TR-21 to TR-2n, TR-31 to TR-3n, and TR-ml to TR-mn) is to receive the phase shifted modulated data Sxy.
  • Each bridge circuit (BCl to BCm) may include a phase filter circuit that only allows signals having the predetermined phase shift for the predetermined common data line (DLl to DLm) pass through.
  • Data transmitter/receiver circuit TR- 14 is transmitting data to be received by data transmitter/receiver circuit TR-m4.
  • Bridge circuit BCl receives phase shifted modulated data S 14 and drives phase shifted modulated data S 14 onto bridge line BLl.
  • Bridge circuit BC2 can receive phase shifted modulated data S 14.
  • bridge circuit BC2 blocks phase shifted modulated data S 14 from being passed to common data line DL2 and passes phases shifted modulated data S 14 onto bridge line BL2.
  • Bridge circuit BC2 can receive phase shifted modulated data S 14.
  • phase shifted modulated data S 14 does not have a predetermined phase shift PS3 (corresponding to a phase shift that bridge circuit BC3 passes to common data line DL3)
  • bridge circuit BC3 blocks phase shifted modulated data S 14 from being passed to common data line DL3 and passes phases shifted modulated data S 14 onto bridge line BL3.
  • Series connected bridge circuits continue to pass the phase shifted modulated data S 14 to an adjacent bridge line while blocking phase shifted modulated data S 14 to the corresponding data line until bridge circuit BCm receives the phase shifted modulated data S 14 from bride line BLm-I.
  • phase shifted modulated data S 14 does not have a predetermined carrier frequency that band pass filters 1240 of data transmitter/receiver circuits (TR-ml to TR-m3 and TR-mn) pass, phase shifted modulated data S 14 may be essentially blocked from data transmitter/receiver circuits (TR-ml to TR-m3 and TR-mn).
  • data transmitter/receiver circuit TR- 14 is transmitting data to data transmitter/receiver circuit TR-m4
  • other data transmitter/receiver circuits may be transmitting data between each other.
  • any number of data transmitter/receiver circuits may simultaneously transmit data to a data transmitter/receiver circuit (TR-I l to TR-mn) along the same row in a simultaneous fashion by utilizing a dedicated frequency spectrum identified with a predetermined row of data transmitter/receiver circuits (TR-11 to TR-mn).
  • Data transmitter/receiver circuit 1300 may be used for data transmitter/receiver circuits (TR-11 to TR-mn) in common data line signaling system 1100 of FIG. 11.
  • Data transmitter/receiver circuit 1300 may differ from data transmitter receiver circuit 1200 in that an amplitude shifter 1330 may be included in data transmitter circuit 1305 instead of phase shifter circuit 1230 of data transmitter circuit 1205. Otherwise, the structure and operation of data transmitter/receiver circuit 1300 may be the same as data transmitter/receiver circuit 1200 of FIG. 12.
  • data transmitter circuit 1305 may provide amplitude shifted modulated data signal Sxy.
  • each data line (DLl to DLm) may only receive data from a bridge circuit BCm if the amplitude has a predetermine shift or modulation corresponding to the amplitude shift or modulation to be passed to the corresponding common data line (DLl to DLm).
  • a data transmitter/receiver circuit (TR-I l to TR- mn) of FIG. 11 may provide an address value to identify the common data line (DLl to DLm) in which the data is to be received by a respective data transmitter/receiver circuit (TR-I l to TR-mn).
  • each data line (DLl to DLm) may only receive data from a bridge circuit BCm if the modulated data (SI l to Smn) includes the predetermined address value that allows the modulated data to be passed(Sl l to Smn) to the corresponding common data line (DLl to DLm).
  • a data transmitter/receiver circuit (TR-I l to TR- mn) of FIG. 11 may provide code value to identify the common data line (DLl to DLm) in which the data is to be received by a respective data transmitter/receiver circuit (TR-I l to TR-mn).
  • each data line (DLl to DLm) may only receive data from a bridge circuit BCm if the modulated data (SI l to Smn) includes the predetermined code value that allows the modulated data to be passed(Sl l to Smn) to the corresponding common data line (DLl to DLm).
  • FIG. 14 a block schematic diagram of a common data line signaling system according to an embodiment is set forth and given the general reference character 1400.
  • each bridge circuit may have a dedicated bridge line (BLl to BLm). This may be accomplished by modifying the common data line signaling system 1100 of FIG. 11 to include m bridge lines (BLl to BLm) in parallel and connected to each bridge circuit (BCl to BCm) as illustrated in common data line signaling system 1400 of FIG. 14.
  • a respective bridge circuit may transmit the modulated data signal Sxy to a predetermined bridge line (BLl to BLm) to be received by a predetermined bridge circuit (BCl to BCm) and transmitted to the predetermined bridge circuits (BCl to BCm) respective shared data line (DLl to DLm).
  • the predetermined phase shift, predetermined amplitude shift or modulation, predetermined address value or predetermined code value may be conceptualized as including a parametric to the frequency modulated data being transmitted.
  • the frequency modulators (320 and 1220) can include high frequency components such as bipolar junction transistors (BJTs), or the like, that have a high cut-off frequency, such as 30-50 GHz.
  • BJTs bipolar junction transistors
  • other components, such as data circuit 310 may include insulated gate field effect transistors (IGFETs) or junction field effect transistors (JFETs), or the like, that may operate at lower frequencies and with less current consumption.
  • IGFETs insulated gate field effect transistors
  • JFETs junction field effect transistors
  • data may be programmed in the phase of the frequency modulated signal (Sl to S4).
  • a frequency fn with a phase of zero may represent a logic zero and a phase of ⁇ /2 may represent a logic one.
  • Data transmitter/receiver circuits may be referred to as data circuits.
  • a data circuit may include a transmitter circuit and/or a receiver circuit like any of the transmitter circuits or receiver circuits described above.

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  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
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Abstract

L'invention concerne un dispositif à semi-conducteurs qui comprend des circuits émetteurs et des circuits récepteurs qui partagent une ligne de données commune et un procédé. Chaque circuit émetteur peut comprendre un modulateur de fréquence qui reçoit un flux de données et fournit une sortie des données modulées de fréquence à une fréquence d'onde porteuse prédéterminée. Chaque récepteur peut comprendre un filtre passe-bande qui permet une sortie des données modulées de fréquence correspondante depuis un circuit émetteur correspondant pour traverser un démodulateur tout en excluant essentiellement les autres données modulées de fréquence. De cette façon, une pluralité de circuits émetteurs peut transmettre simultanément des données avec chacun des circuits de la pluralité des circuits émetteurs transmettant des données à un circuit récepteur prédéterminé.
PCT/US2008/067446 2007-07-02 2008-06-19 Signalisation d'une ligne de données commune et procédé WO2009006032A2 (fr)

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US11/824,737 US7941098B2 (en) 2007-07-02 2007-07-02 Common data line signaling and method

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US7745301B2 (en) 2005-08-22 2010-06-29 Terapede, Llc Methods and apparatus for high-density chip connectivity
US8957511B2 (en) 2005-08-22 2015-02-17 Madhukar B. Vora Apparatus and methods for high-density chip connectivity
DE112012000546B4 (de) * 2012-04-27 2021-08-19 Anywire Corporation Übertragungsleitungs-Adressüberlappungs-Detektionssystem und Unterstation-Endgerät, das in dem System verwendet wird
US9853676B2 (en) * 2014-09-30 2017-12-26 Apple Inc. Alternative routing of wireless data onto power supply

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US7941098B2 (en) 2011-05-10
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TW200908622A (en) 2009-02-16

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