WO2009093375A1 - Laminated ceramic capacitor and process for producing the laminated ceramic capacitor - Google Patents
Laminated ceramic capacitor and process for producing the laminated ceramic capacitor Download PDFInfo
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- WO2009093375A1 WO2009093375A1 PCT/JP2008/071383 JP2008071383W WO2009093375A1 WO 2009093375 A1 WO2009093375 A1 WO 2009093375A1 JP 2008071383 W JP2008071383 W JP 2008071383W WO 2009093375 A1 WO2009093375 A1 WO 2009093375A1
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- 239000003985 ceramic capacitor Substances 0.000 title claims description 49
- 238000000034 method Methods 0.000 title claims description 16
- 239000000919 ceramic Substances 0.000 claims abstract description 116
- 239000006104 solid solution Substances 0.000 claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims abstract description 24
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- 239000000956 alloy Substances 0.000 claims abstract description 21
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 21
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- 239000003990 capacitor Substances 0.000 claims description 78
- 229910010293 ceramic material Inorganic materials 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 230000032798 delamination Effects 0.000 abstract description 15
- 229910002113 barium titanate Inorganic materials 0.000 abstract description 7
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- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 18
- 230000000694 effects Effects 0.000 description 13
- 230000007547 defect Effects 0.000 description 9
- 238000005245 sintering Methods 0.000 description 7
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 6
- 238000011156 evaluation Methods 0.000 description 6
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- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 2
- 229910052693 Europium Inorganic materials 0.000 description 2
- 229910052688 Gadolinium Inorganic materials 0.000 description 2
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- 229910052771 Terbium Inorganic materials 0.000 description 2
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- 229910020203 CeO Inorganic materials 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/018—Dielectrics
- H01G4/06—Solid dielectrics
- H01G4/08—Inorganic dielectrics
- H01G4/12—Ceramic dielectrics
- H01G4/1209—Ceramic dielectrics characterised by the ceramic dielectric material
- H01G4/1218—Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates
- H01G4/1227—Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates based on alkaline earth titanates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/005—Electrodes
- H01G4/008—Selection of materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/30—Stacked capacitors
Definitions
- the present invention relates to a multilayer ceramic capacitor and a method of manufacturing the same, and in particular, includes a plurality of laminated dielectric ceramic layers made of a dielectric ceramic containing a BaTiO 3 system ceramic as a main component and Cu as a subcomponent.
- the present invention relates to a multilayer ceramic capacitor and a method for manufacturing the same.
- Cu contained as a subcomponent in the dielectric ceramic has the property of being completely dissolved with Ni or the like, and this may cause the following problems.
- the capacitor body provided in the multilayer ceramic capacitor includes a plurality of internal electrodes formed therein, that is, a capacitance forming portion in which capacitance forming electrodes are distributed, and an outer layer portion positioned so as to sandwich the capacitance forming portion in the stacking direction. .
- the absolute amount of the Cu component contained in the outer layer portion is: More than the absolute amount of Cu component contained in each dielectric ceramic layer located between the capacitance forming electrodes.
- the capacitor forming electrode includes, for example, a metal that can form a solid solution or an alloy with Cu such as Ni as a conductive component
- the capacitor forming electrode is closest to the outer layer portion, that is, positioned in the outermost layer.
- the Cu component contained in the outer layer portion causes a larger amount of Cu component than other capacitor forming electrodes.
- the capacitor forming electrode located in the outermost layer is liable to cause a fattening phenomenon and a decrease in smoothness. As a result, delamination and short-circuit defects may be caused in the capacitor body.
- Patent Document 1 5 ⁇ m is disclosed as the thickness of each dielectric ceramic layer.
- the thickness is further reduced to 1 ⁇ m or less, delamination and short-circuit defects are more likely to occur. It becomes easy to occur, and the above-mentioned fat phenomenon and the problem of reduced smoothness cannot be ignored.
- JP 2001-142955 A JP 2001-142955 A
- an object of the present invention is to provide a multilayer ceramic capacitor that can solve the above-described problems and a method for manufacturing the same.
- the present invention includes a plurality of laminated dielectric ceramic layers composed of a dielectric ceramic containing BaTiO 3 ceramic as a main component and Cu as a subcomponent, and a metal that can form a solid solution or alloy with Cu.
- a capacitor body composed of a plurality of capacitance forming electrodes formed along a specific interface between the ceramic layers, and the capacitor body and a specific one of the capacitance forming electrodes are electrically connected to the outside of the capacitor body. It is first directed to a multilayer ceramic capacitor comprising first and second external terminal electrodes formed on the surface.
- the capacitance forming electrode further includes Cu derived from Cu contained in the dielectric ceramic, and is located in the outermost layer among the plurality of capacitance forming electrodes.
- the Cu concentration of the capacitance forming electrode is not more than 5 times the Cu concentration of the capacitance forming electrode located in the center.
- the “Cu concentration of the capacitance forming electrode located in the center” means that when the number of capacitance forming electrodes is 2n (n is a natural number), the Cu concentration of the nth capacitance forming electrode and the (n + 1) th It is the average value with the Cu concentration of the capacitance forming electrode. When the number of capacitance forming electrodes is 2n + 1, it is the Cu concentration of the (n + 1) th capacitance forming electrode.
- the “Cu concentration” is defined by the ratio of the peak intensity of Cu to the peak intensity of the conductive metal originally contained in the capacitance forming electrode such as Ni, which is obtained by WDX.
- a multilayer ceramic capacitor comprising a capacitor main body including a capacitor forming portion in which a capacitor forming electrode is distributed and an outer layer portion positioned so as to sandwich the capacitor forming portion in the stacking direction.
- a non-effective electrode including a solid solution or an alloy extending in parallel with the capacitance forming electrode located in the outermost layer and including Cu derived from Cu contained in the dielectric ceramic is formed. It is said.
- the distance between the non-effective electrode and the capacitor forming electrode located on the outermost layer is 0.8 times the thickness dimension of the dielectric ceramic layer between the capacitor forming electrodes or 1 ⁇ m, whichever is shorter It is preferable that the thickness is not less than 4 mm and not more than 4 times the thickness of the dielectric ceramic layer between the capacitance forming electrodes.
- the non-effective electrode is formed so as not to be in contact with any of the first and second external terminal electrodes.
- the Cu content of the dielectric ceramic is preferably 0.1 to 2 mole parts when the BaTiO 3 ceramic as a main component is taken as 100 mole parts.
- the present invention is also directed to a method for manufacturing a multilayer ceramic capacitor.
- a method of manufacturing a multilayer ceramic capacitor according to the present invention includes a plurality of stacked dielectric ceramic green layers including a dielectric ceramic material containing a BaTiO 3 ceramic as a main component and Cu as a subcomponent, and Cu and a solid solution or Consists of a plurality of capacitance forming electrodes including a metal capable of forming an alloy and formed along a specific interface between dielectric ceramic green layers, and the capacitance forming portion and the capacitance forming portion are laminated.
- the outer layer portion is positioned so as to be sandwiched in the direction, and the outer layer portion is formed with an ineffective electrode including a metal that extends in parallel with the capacitance forming electrode positioned in the outermost layer and can form a solid solution or alloy with Cu.
- a process of preparing a raw capacitor body, a process of firing the raw capacitor body, and a specific one of the capacitance forming electrodes Forming the first and second external terminal electrodes on the outer surface of the capacitor body so as to be connected to each other, and forming a solid solution or alloy with the metal in the firing step, It is characterized in that a part of Cu contained in the dielectric ceramic material in the outer layer portion is absorbed by the ineffective electrode.
- Cu contained in the outer layer portion of the capacitor main body tends to diffuse toward the capacitance forming portion in the firing step.
- Cu to be diffused is absorbed by the ineffective electrode. Therefore, a large amount of Cu is not absorbed particularly by the capacitance forming electrode located in the outermost layer.
- the Cu concentration of the capacitance forming electrode located in the outermost layer is suppressed to 5 times or less than the Cu concentration of the capacitance forming electrode located in the center.
- the present invention by preventing the concentration of Cu in the capacitor forming electrode located in the outermost layer in particular, it is possible to prevent a decrease in thickness and a decrease in smoothness in the capacitor forming electrode. The occurrence of delamination and short-circuit defects caused by these fattening phenomena and smoothness degradation can be suppressed.
- the thickness of the dielectric ceramic layer is 5 ⁇ m or less per layer
- the number of dielectric ceramic layers in the capacitance forming portion is 30 or more
- the thickness of the outer layer portion is the dielectric ceramic layer.
- the present invention is particularly advantageously applied to a multilayer ceramic capacitor having a thickness of 4 times or more per layer.
- the distance between the non-effective electrode and the capacitor forming electrode located in the outermost layer is either 0.8 times the thickness dimension of the dielectric ceramic layer between the capacitor forming electrodes or 1 ⁇ m.
- the thickness is selected to be not less than the shorter dimension and not more than 4 times the thickness dimension of the dielectric ceramic layer between the capacitance forming electrodes, the above-described effect can be achieved more reliably.
- the non-effective electrode is formed so as not to be in contact with any of the first and second external electrodes, delamination can be made more difficult to occur.
- the Cu content of the dielectric ceramic is selected in the range of 0.1 to 2 mole parts when the BaTiO 3 based ceramic as a main component is 100 mole parts, the effect of improving the material properties such as the CR product can be obtained with certainty, and the occurrence of delamination can be more reliably suppressed.
- FIG. 1 is a cross-sectional view schematically showing a multilayer ceramic capacitor 1 according to a first embodiment of the present invention. It is a figure which expands and shows the part A of FIG. It is sectional drawing which shows the thing of the raw state of the capacitor
- FIG. 1 is a cross-sectional view schematically showing a multilayer ceramic capacitor 1 according to a first embodiment of the present invention.
- FIG. 2 is an enlarged view of a portion A in FIG.
- the multilayer ceramic capacitor 1 includes a plurality of laminated dielectric ceramic layers 2 and a plurality of capacitance forming electrodes 3 and 4 formed along a specific interface between the dielectric ceramic layers 2.
- a main body 5 is provided.
- the dielectric ceramic layer 2 is made of a dielectric ceramic containing a BaTiO 3 ceramic as a main component and Cu as a subcomponent.
- this dielectric ceramic is disclosed in the above-mentioned Patent Document 1, and the BaTiO 3 -based ceramic as the main component is represented by the general formula ABO 3 .
- A necessarily includes Ba and may further include at least one of Ca and Sr, and B necessarily includes Ti and may include Zr.
- Cu as an accessory component is preferably contained in a range of 0.1 to 2 mole parts, when 100 mole parts of the BaTiO 3 based ceramic as a main component is taken as 100 mole parts.
- the dielectric ceramic is further composed of at least one rare earth element selected from La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Y, Mn, Ni and Mg. At least one of these metals and Si as a sintering aid may be included.
- the capacitance forming electrodes 3 and 4 include a metal that can form a solid solution or an alloy with Cu such as Ni, for example, as a conductive component.
- the multilayer ceramic capacitor 1 includes first and second external terminal electrodes 6 and 7 formed on each end of the capacitor body 5.
- the first external terminal electrode 6 is electrically connected to the first capacitance forming electrode 3, and the second external terminal electrode 7 is electrically connected to the second capacitance forming electrode 4.
- the first capacitor forming electrodes 3 and the second capacitor forming electrodes 4 are alternately arranged in the stacking direction.
- the capacitor body 5 includes a capacitance forming portion 8 in which the capacitance forming electrodes 3 and 4 are distributed, and outer layer portions 9 and 10 positioned so as to sandwich the capacitance forming portion 8 in the stacking direction.
- the thickness of each dielectric ceramic layer 2 is 5 ⁇ m or less
- the number of dielectric ceramic layers 2 in the capacitance forming portion 8 is 30 or more
- each of the outer layer portions 9 and 10 is The thickness of the dielectric ceramic layer 2 is at least four times the thickness of each dielectric ceramic layer 2.
- non-effective electrodes 11 and 12 extending in parallel with the capacitance forming electrodes 3 (B) and 4 (B) located in the outermost layer are formed, respectively.
- the non-effective electrodes 11 and 12 have the same area as the capacitance forming electrodes 3 and 4 and are formed so as not to be in contact with any of the first and second external terminal electrodes 6 and 7.
- the non-effective electrodes 11 and 12 are configured to include Cu derived from Cu included in the dielectric ceramic constituting the dielectric ceramic layer 2 as a result of a firing process performed in the manufacturing process of the multilayer ceramic capacitor 1 described later. Solid solution or alloy.
- the capacitance forming electrodes 3 and 4 also contain Cu derived from Cu contained in the dielectric ceramic as a result of the firing step performed in the manufacturing process of the multilayer ceramic capacitor 1. 4, the Cu concentration of the capacitance forming electrodes 3 (B) and 4 (B) located in the outermost layer is 5 of the Cu concentration of the capacitance forming electrodes 3 (C) and 4 (C) located in the center. No more than twice, preferably no more than 3 times.
- the capacitance forming electrodes located in the outermost layer are indicated by “3 (B)” and “4 (B)”, and the capacitance forming electrodes located in the center are indicated by “3 (C)” and “ 4 (C) ”distinguishes it from other capacitor forming electrodes.
- the capacitor forming electrodes are simply indicated by reference numerals“ 3 ”and“ 4 ”. Show.
- the nth capacitance forming electrode 3 (C) and the (n + 1) th capacitance forming electrode are located at the center.
- the capacitance forming electrode 4 (C) is selected, and the Cu concentration of the capacitance forming electrode located in the center is determined by the Cu concentration of the capacitance forming electrode 3 (C) and the Cu concentration of the capacitance forming electrode 4 (C). It means that it is the average value.
- the total number of the capacitance forming electrodes 3 and 4 is 2n + 1, the (n + 1) th capacitance forming electrode is a capacitance forming electrode located at the center.
- the multilayer ceramic capacitor 1 having the above-described configuration is manufactured as follows.
- FIG. 3 is a cross-sectional view showing the raw capacitor body 5 prepared to obtain the capacitor body 5 shown in FIG.
- the same reference numerals as those used for the elements provided in the sintered capacitor body 5 shown in FIG. 1 are used for the corresponding elements in the raw state of the capacitor body 5 shown in FIG. To do.
- the raw capacitor body 5 includes a plurality of dielectric ceramic green layers 2 and a dielectric ceramic green layer 2 including a dielectric ceramic material mainly composed of BaTiO 3 -based ceramics and Cu as a minor component. It comprises a plurality of capacitance forming electrodes 3 and 4 formed along a specific interface.
- the raw capacitor body 5 includes a capacitance forming portion 8 in which the capacitance forming electrodes 3 and 4 are distributed and outer layer portions 9 and 10 positioned so as to sandwich the capacitance forming portion 8 in the stacking direction.
- Ineffective layers 11 and 12 are formed on the outer layer portions 9 and 10, respectively.
- These non-effective electrodes 11 and 12 include a metal that can form a solid solution or alloy with Cu, for example, a metal such as Ni, Pd, or Pt, when it is formed inside the raw capacitor body 5.
- the first and second external terminal electrodes 6 and 6 are electrically connected to specific ones of the capacitance forming electrodes 3 and 4 in the sintered capacitor body 5, respectively. 7 is formed on each end of the capacitor body 5.
- a method by applying and baking a conductive paste is applied.
- the conductive material for the external terminal electrodes 6 and 7 is used.
- the adhesive paste may be baked at the same time.
- the non-effective electrodes 11 and 12 are formed, and the non-effective electrodes 11 and 12 include a metal that can form a solid solution or alloy with Cu as described above. Some of the Cu contained in the dielectric ceramic material at 10 and 10 is advantageously absorbed by the non-effective electrodes 11 and 12 so as to form a solid solution or alloy with the metal. As a result, it is possible to prevent Cu from being concentrated particularly in the capacitance forming electrodes 3 (B) and 4 (B) located in the outermost layer, so that the fattening phenomenon and the smoothness are less likely to be caused. 5, it is possible to make it difficult for delamination and short-circuit defects to occur.
- the non-effective electrodes 11 and 12 are too far away from the capacitance forming electrodes 3 (B) and 4 (B) located in the outermost layer, the capacitance forming electrodes 3 (B) and B located in the outermost layer 4 (B), the effect of preventing the concentration of Cu is reduced, and on the other hand, if it is too close, the non-effective electrodes 11 and 12 have their capacitance phenomenon due to absorption of Cu by the capacity forming electrode 3 (B ) And 4 (B) are adversely affected, and in either case, a short circuit failure may be caused. In order to avoid such an inconvenience more reliably, as shown in FIG.
- each distance D1 is 0.8 times the thickness dimension D2 of the dielectric ceramic layer 2 between the capacitance forming electrodes 3 and 4 or 1 ⁇ m, whichever is shorter, and the thickness dimension of the dielectric ceramic layer 2 It is preferably 4 times or less of D2.
- the Cu concentration of the capacitance forming electrodes 3 (B) and 4 (B) located in the outermost layer is usually higher than the Cu concentration of the capacitance forming electrodes 3 (C) and 4 (C) located in the center. Get higher.
- the Cu-absorbing action by the non-effective electrodes 11 and 12 in the firing step described above is strong, and the non-effective electrodes 11 and 12 are capacitance forming electrodes 3 (B) and 4 (B), respectively, located in the outermost layer.
- the Cu concentration of the capacitor forming electrodes 3 (C) and 4 located in the center is the same. It may be lower than the Cu concentration of (C).
- FIG. 4 is a diagram corresponding to FIG. 2 for explaining the second embodiment of the present invention. 4, elements corresponding to those shown in FIG. 2 are denoted by the same reference numerals, and redundant description is omitted.
- the second embodiment is characterized in that a plurality of, for example, five non-effective electrodes 11 are formed in the outer layer portion 9 so as to extend in parallel with each other.
- the other non-effective electrodes 12 are similarly formed in the other outer layer portion 10 so as to extend in parallel with each other. According to this embodiment, the effect
- FIG. 5 is a view corresponding to FIG. 1 for explaining the third embodiment of the present invention.
- elements corresponding to those shown in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted.
- the multilayer ceramic capacitor 1a according to the third embodiment is characterized in that each of the non-effective electrodes 11a and 12a is divided into a plurality of parts, for example, four parts. Each of the non-effective electrodes 11a and 12a may be further divided into a number of parts. According to this embodiment, the total area of each of the non-effective electrodes 11a and 12a can be made smaller than the area of each of the non-effective electrodes 11 and 12 shown in FIG. 1, thus reducing the total area. This can be cost effective.
- FIG. 6 is a view corresponding to FIG. 1 for explaining the fourth embodiment of the present invention.
- elements corresponding to those shown in FIG. 1 are given the same reference numerals, and redundant description is omitted.
- the ineffective electrodes 11b and 12b reach one of the end faces of the capacitor body 5 so as to be in contact with the first and second external terminal electrodes 6 and 7, respectively. It is characterized by being formed.
- the possibility of delamination increases due to the fat phenomenon due to Cu absorption of the ineffective electrodes 11b and 12b themselves, which is not preferable.
- Cu, R (La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Y) as subcomponents of the ceramic composition shown in Table 1; mg, is the oxide of Mn and Ni, CuO, La 2 O 3 , CeO 2, Pr 6 O 11, Nd 2 O 3, Sm 2 O 3, Eu 2 O 3, Gd 2 O 3, Tb 4 O 7 , Dy 2 O 3 , Ho 2 O 3 , Er 2 O 3 , Tm 2 O 3 , Yb 2 O 3 , Y 2 O 3 , MgO, MnO and NiO are prepared, and a sintering aid (silicon oxide is added). A colloidal silica solution containing 30% by weight in terms of SiO 2 was prepared.
- the barium titanate solid solution, the subcomponent oxide, and the sintering aid were weighed so that the desired ceramic compositions C1 to C51 shown in Table 1 were obtained.
- the subcomponent oxide is shown in a molar ratio with respect to 100 mole parts of the barium titanate solid solution, and the sintering aid is based on 100 parts by weight of the total of the barium titanate solid solution and the subcomponent oxide. It is shown in weight ratio.
- a barium titanate solid solution, subcomponent oxides and sintering aids weighed so as to obtain ceramic compositions C1 to C51 shown in Table 1 were added to an organic solvent such as a polyvinyl butyral binder and ethanol. And wet mixed by a ball mill to prepare a slurry. This slurry was formed into a sheet by a doctor blade method to obtain a rectangular dielectric ceramic green sheet.
- a conductive paste containing Ni as a conductive component was printed on the green sheet to form a conductive paste layer serving as a capacitance forming electrode. Also, a conductive paste containing Ni as a conductive component was printed on another green sheet to form a conductive paste layer serving as an ineffective electrode having the same area as the capacitance forming electrode.
- the green sheets on which the conductive paste layer to be the capacitance forming electrode is formed are stacked so that the side from which the conductive paste layer is drawn is alternated, and the conductive sheet to be the capacitance forming electrode in the capacitance forming portion.
- a green capacitor body was obtained by laminating 100 sheets of conductive paste layers and laminating one sheet of green sheet on which conductive paste layers serving as ineffective electrodes were formed on both outer layer portions.
- each thickness of the dielectric ceramic layer in the capacitance forming portion is 2 ⁇ m
- the distance D1 (see FIG. 2) from the capacitance forming electrode located in the outermost layer is 1 ⁇ m. It was made to form at a position.
- the raw capacitor body was heated to a temperature of 350 ° C. in an N 2 atmosphere to remove the binder, and then H 2 —N 2 —H 2 with an oxygen partial pressure of 10 ⁇ 9 to 10 ⁇ 12 MPa.
- a reducing atmosphere composed of O gas firing was performed in a temperature range of 1000 to 1400 ° C. for 2 hours to obtain a sintered capacitor body.
- condenser main body after sintering produced using each ceramic composition was cross-sectional-polished, and the porosity of the outer layer was set to the temperature used as 3% or less.
- the multilayer ceramic capacitor according to each sample has a structure as shown in FIG. 1, has a lengthwise dimension of 3.2 mm, a widthwise dimension of 1.6 mm, and a thicknesswise dimension of 1.6 mm.
- the overlapping area of the capacitance forming electrodes per layer was 3.3 mm 2 .
- the multilayer ceramic capacitor according to each sample produced in this way was evaluated for each item of “short defect rate”, “delamination”, and “WDX strength”. These items were evaluated as follows.
- Short-circuit defect rate 100 samples were taken out of the multilayer ceramic capacitors according to each sample, whether or not a short-circuit defect occurred was evaluated, and the ratio of the number of short-circuit defects in 100 was determined.
- Delamination 50 capacitors are extracted from the multilayer ceramic capacitors of each sample, and the surface defined by the length and thickness dimensions is mirror-polished, and then the capacitance is formed on the outermost layer with an optical microscope. The presence / absence of delamination in the entire electrode was confirmed, and the ratio of the number of delamination out of 50 was determined.
- WDX strength the surface defined by the length-direction dimension and the thickness-direction dimension of the multilayer ceramic capacitor according to each sample is mirror-polished, and a capacitance-forming electrode located at the outermost layer and a capacitance-forming electrode located at the center WDX point analysis was performed. If the Cu concentration (specified by the Cu / Ni intensity ratio) of the capacitance forming electrode located in the outermost layer is 5 times or less than the Cu concentration of the capacitance forming electrode located in the center, it is determined that it is good. Then, “G” is displayed.
- the “ceramic composition” in Table 2 corresponds to the “ceramic composition symbol” shown in Table 1, and indicates the composition of the dielectric ceramic applied in each sample shown in Table 2.
- each of the metals contained in the ineffective electrode was changed from Ni to Pd or Pt as shown in the column of “Ineffective electrode metal” in Table 3, by the same method as in Experimental Example 1, A multilayer ceramic capacitor according to the sample was produced and evaluated. The evaluation results are shown in Table 3. As for the dielectric ceramic, only those having the “ceramic composition symbol” shown in the “ceramic composition” column of Table 3 among the ceramic compositions shown in Table 1 were applied.
- Experimental example 3 is a case where the design such as the distance D1 from the capacitance forming electrode to the ineffective electrode located in the outermost layer as shown in FIG. 2 and the thickness D2 of the dielectric ceramic layer between the capacitance forming electrodes is changed. This was carried out in order to investigate the influence on the effect of the present invention.
- (1) to (5) shown in the column “implementation pattern” in Table 4 indicate the following designs.
- the thickness of the dielectric ceramic layer was 5 ⁇ m, and the distance from the capacitance forming electrode located in the outermost layer to the ineffective electrode was 1 ⁇ m.
- the thickness of the dielectric ceramic layer was 0.8 ⁇ m, and the distance from the capacitance forming electrode located in the outermost layer to the ineffective electrode was 1 ⁇ m.
- the thickness of the dielectric ceramic layer was 0.8 ⁇ m, and the distance from the capacitance forming electrode located in the outermost layer to the ineffective electrode was 0.6 ⁇ m.
- a multilayer ceramic capacitor according to each sample was produced by the same method as in Experimental Example 1 except that the design of the multilayer ceramic capacitor was changed as shown in the column “Execution pattern” in Table 4. Evaluation was performed. The evaluation results are shown in Table 4. For the dielectric ceramic, only those having the “ceramic composition symbol” shown in the “ceramic composition” column of Table 4 among the ceramic compositions shown in Table 1 were applied.
- the “effective pattern” is too far from the capacitance forming electrode located in the outermost layer as in the case of (3), or the ineffective electrode is in the outermost layer as in (5). If the electrode is too close to the capacitor forming electrode located in the region, a short circuit failure may occur due to the ineffective electrode and / or the capacitor forming electrode becoming fat.
- Experimental Example 4 was carried out in order to investigate the influence on the effect of the present invention when the number of stacked capacitance forming electrodes was changed. In Experimental Example 4, a sample without an ineffective electrode was also evaluated.
- a multilayer ceramic capacitor according to each sample was manufactured by the same method as in Experimental Example 1 except that the number of stacked capacitance forming electrodes was changed as shown in the column “Number of stacked layers” in Table 5. .
- An increase in the “number of layers” means that the outer layer becomes thinner accordingly.
- Samples 350 to 356 in Table 5 are comparative samples without ineffective electrodes.
- the dielectric ceramic only those having the “ceramic composition symbol” shown in the “ceramic composition” column of Table 5 among the ceramic compositions shown in Table 1 were applied.
- the present invention is more effectively applied as the number of laminated layers of the capacity forming electrode is larger than the number of laminated layers, such as 10 layers, and the outer layer portion is thinner. I can say that.
- a to C shown in the “execution pattern” column of Table 6 indicate the following designs, respectively.
- a multilayer ceramic capacitor according to each sample was prepared by the same method as in Experimental Example 1, except that the design of the multilayer ceramic capacitor was changed as shown in the column “Execution pattern” in Table 6. Evaluation was performed. The evaluation results are shown in Table 6. As for the dielectric ceramic, only those having the “ceramic composition symbol” shown in the “ceramic composition” column of Table 6 among the ceramic compositions shown in Table 1 were applied.
- the Cu content is the same as in the case where the “ceramic composition” is C12 or C34.
- the Cu content is desirably 2 mol parts or less.
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Abstract
When a dielectric ceramic layer is formed of a dielectric ceramic composed mainly of a BaTiO3 ceramic and containing Cu as an accessory component while a capacity-forming electrode contains, for example, Ni as an electroconductive component, due to the nature of Cu which, together with Ni, is likely to form a complete solid solution, during firing, a large amount of Cu contained in the dielectric ceramic is absorbed in the capacity-forming electrode particularly located in the outermost layer resulting in the occurrence of a thickening phenomenon or lowered smoothness in the capacity-forming electrode which sometimes causes delamination or a short circuiting failure. In outer layer parts (9 and 10), non-effective electrodes (11 and 12), which are extended parallel to capacity-forming electrodes (3(B) and 4(B)) located in the outermost layer and contain a metal which, together with Cu, can form a solid solution or an alloy, are formed so that, in the step of firing, Cu is absorbed by the non-effective electrodes (11 and 12) and the probability of causing a thickening phenomenon or a lowering in smoothness is reduced in the capacity-forming electrodes (3(B) and 4(B)) located in the outermost layer.
Description
この発明は、積層セラミックコンデンサおよびその製造方法に関するもので、特に、BaTiO3系セラミックを主成分としかつCuを副成分として含む誘電体セラミックからなる、複数の積層された誘電体セラミック層を備える、積層セラミックコンデンサおよびその製造方法に関するものである。
The present invention relates to a multilayer ceramic capacitor and a method of manufacturing the same, and in particular, includes a plurality of laminated dielectric ceramic layers made of a dielectric ceramic containing a BaTiO 3 system ceramic as a main component and Cu as a subcomponent. The present invention relates to a multilayer ceramic capacitor and a method for manufacturing the same.
積層セラミックコンデンサに対する小型化かつ大容量化の要求は、近年ますます厳しくなっている。このため、積層セラミックコンデンサに備える誘電体セラミック層の薄層化が進められている。しかしながら、薄層化が進むと、誘電体セラミック層の1層あたりに印加され得る電界が大きくなる。したがって、誘電体セラミック層の薄層化が進むほど、誘電体セラミック層を構成する誘電体セラミックに対しては、より高い信頼性が求められる。
Demand for miniaturization and large capacity for multilayer ceramic capacitors has become increasingly severe in recent years. For this reason, the thickness of the dielectric ceramic layer provided in the multilayer ceramic capacitor is being reduced. However, as the layer becomes thinner, the electric field that can be applied per dielectric ceramic layer increases. Accordingly, as the dielectric ceramic layer is further thinned, higher reliability is required for the dielectric ceramic constituting the dielectric ceramic layer.
このように高い信頼性を示す誘電体セラミックとして、BaTiO3系セラミックを主成分としかつCuを副成分として含むものが提案されている(たとえば、特許文献1参照)。この誘電体セラミックによれば、CR積などの材料特性を改善することができる。
As a dielectric ceramic exhibiting such high reliability, a ceramic containing BaTiO 3 system ceramic as a main component and Cu as a subcomponent has been proposed (for example, see Patent Document 1). According to this dielectric ceramic, material characteristics such as CR product can be improved.
しかしながら、上記のように誘電体セラミックにおいて副成分として含まれるCuは、Ni等と全率固溶する性質があり、このことが以下のような問題を引き起こすことがある。
However, as described above, Cu contained as a subcomponent in the dielectric ceramic has the property of being completely dissolved with Ni or the like, and this may cause the following problems.
積層セラミックコンデンサに備えるコンデンサ本体は、そこに形成される複数の内部電極、すなわち容量形成用電極が分布する容量形成部と、この容量形成部を積層方向に挟むように位置する外層部とからなる。そして、通常、容量形成部における容量形成用電極間に位置する誘電体セラミック層の各々の厚みに比べて、外層部の厚みの方が厚いため、外層部に含まれるCu成分の絶対量は、容量形成用電極間に位置する各誘電体セラミック層に含まれるCu成分の絶対量より多い。
The capacitor body provided in the multilayer ceramic capacitor includes a plurality of internal electrodes formed therein, that is, a capacitance forming portion in which capacitance forming electrodes are distributed, and an outer layer portion positioned so as to sandwich the capacitance forming portion in the stacking direction. . And, since the thickness of the outer layer portion is usually larger than the thickness of each dielectric ceramic layer located between the capacitance forming electrodes in the capacitance forming portion, the absolute amount of the Cu component contained in the outer layer portion is: More than the absolute amount of Cu component contained in each dielectric ceramic layer located between the capacitance forming electrodes.
このため、容量形成用電極が、たとえばNiのようなCuと固溶体または合金を作り得る金属を導電成分として含む場合、複数の容量形成用電極のうち、外層部に最も近い、すなわち最外層に位置する容量形成用電極には、外層部に含まれるCu成分が原因となって、他の容量形成用電極に比べて、より多くのCu成分が入ってくることになる。このことから、最外層に位置する容量形成用電極には、太り現象や平滑性低下が生じやすくなり、その結果、コンデンサ本体において、デラミネーションやショート不良がもたらされることがある。
For this reason, when the capacitor forming electrode includes, for example, a metal that can form a solid solution or an alloy with Cu such as Ni as a conductive component, the capacitor forming electrode is closest to the outer layer portion, that is, positioned in the outermost layer. In the capacitor forming electrode, the Cu component contained in the outer layer portion causes a larger amount of Cu component than other capacitor forming electrodes. For this reason, the capacitor forming electrode located in the outermost layer is liable to cause a fattening phenomenon and a decrease in smoothness. As a result, delamination and short-circuit defects may be caused in the capacitor body.
特許文献1では、誘電体セラミック層の1層あたりの厚みとして、5μmが開示されているが、より薄層化が進んで、1μmまたはそれ以下になってくると、デラミネーションやショート不良がより生じやすくなり、上記の太り現象や平滑性低下の問題が無視できないレベルとなってくる。
特開2001-142955号公報
In Patent Document 1, 5 μm is disclosed as the thickness of each dielectric ceramic layer. However, when the thickness is further reduced to 1 μm or less, delamination and short-circuit defects are more likely to occur. It becomes easy to occur, and the above-mentioned fat phenomenon and the problem of reduced smoothness cannot be ignored.
JP 2001-142955 A
そこで、この発明の目的は、上述したような問題を解決し得る積層セラミックコンデンサおよびその製造方法を提供しようとすることである。
Therefore, an object of the present invention is to provide a multilayer ceramic capacitor that can solve the above-described problems and a method for manufacturing the same.
この発明は、BaTiO3系セラミックを主成分としかつCuを副成分として含む誘電体セラミックからなる、複数の積層された誘電体セラミック層と、Cuと固溶体または合金を作り得る金属を含みかつ誘電体セラミック層間の特定の界面に沿って形成された複数の容量形成用電極とをもって構成された、コンデンサ本体と、容量形成用電極の特定のものとそれぞれ電気的に接続されるようにコンデンサ本体の外表面上に形成された、第1および第2の外部端子電極とを備える、積層セラミックコンデンサにまず向けられるものである。
The present invention includes a plurality of laminated dielectric ceramic layers composed of a dielectric ceramic containing BaTiO 3 ceramic as a main component and Cu as a subcomponent, and a metal that can form a solid solution or alloy with Cu. A capacitor body composed of a plurality of capacitance forming electrodes formed along a specific interface between the ceramic layers, and the capacitor body and a specific one of the capacitance forming electrodes are electrically connected to the outside of the capacitor body. It is first directed to a multilayer ceramic capacitor comprising first and second external terminal electrodes formed on the surface.
この発明に係る積層セラミックコンデンサは、第1の局面では、容量形成用電極が、誘電体セラミックに含まれるCuに由来するCuをさらに含み、複数の容量形成用電極のうち、最外層に位置する容量形成用電極のCu濃度が、中央に位置する容量形成用電極のCu濃度の5倍以下であることを特徴としている。
In the multilayer ceramic capacitor according to the present invention, in the first aspect, the capacitance forming electrode further includes Cu derived from Cu contained in the dielectric ceramic, and is located in the outermost layer among the plurality of capacitance forming electrodes. The Cu concentration of the capacitance forming electrode is not more than 5 times the Cu concentration of the capacitance forming electrode located in the center.
なお、上記「中央に位置する容量形成用電極のCu濃度」とは、容量形成用電極の数が2n(nは自然数)であるときには、n番目の容量形成用電極のCu濃度とn+1番目の容量形成用電極のCu濃度との平均値のことであり、容量形成用電極の数が2n+1であるときには、n+1番目の容量形成用電極のCu濃度のことである。また、「Cu濃度」は、WDXにより求めた、Niのような容量形成用電極に本来含まれている導電性金属のピーク強度に対するCuのピーク強度の比によって規定される。
The “Cu concentration of the capacitance forming electrode located in the center” means that when the number of capacitance forming electrodes is 2n (n is a natural number), the Cu concentration of the nth capacitance forming electrode and the (n + 1) th It is the average value with the Cu concentration of the capacitance forming electrode. When the number of capacitance forming electrodes is 2n + 1, it is the Cu concentration of the (n + 1) th capacitance forming electrode. The “Cu concentration” is defined by the ratio of the peak intensity of Cu to the peak intensity of the conductive metal originally contained in the capacitance forming electrode such as Ni, which is obtained by WDX.
この発明に係る積層セラミックコンデンサは、第2の局面では、コンデンサ本体が、容量形成用電極が分布する容量形成部と容量形成部を積層方向に挟むように位置する外層部とからなり、外層部には、最外層に位置する容量形成用電極と平行に延びかつ誘電体セラミックに含まれるCuに由来するCuを含んで構成された固溶体または合金を含む非有効電極が形成されていることを特徴としている。
According to a second aspect of the present invention, there is provided a multilayer ceramic capacitor comprising a capacitor main body including a capacitor forming portion in which a capacitor forming electrode is distributed and an outer layer portion positioned so as to sandwich the capacitor forming portion in the stacking direction. Is characterized in that a non-effective electrode including a solid solution or an alloy extending in parallel with the capacitance forming electrode located in the outermost layer and including Cu derived from Cu contained in the dielectric ceramic is formed. It is said.
上記第2の局面において、非有効電極と最外層に位置する容量形成用電極との距離は、容量形成用電極間の誘電体セラミック層の厚み寸法の0.8倍または1μmのいずれか短い方の寸法以上、かつ容量形成用電極間の誘電体セラミック層の厚み寸法の4倍以下であることが好ましい。
In the second aspect, the distance between the non-effective electrode and the capacitor forming electrode located on the outermost layer is 0.8 times the thickness dimension of the dielectric ceramic layer between the capacitor forming electrodes or 1 μm, whichever is shorter It is preferable that the thickness is not less than 4 mm and not more than 4 times the thickness of the dielectric ceramic layer between the capacitance forming electrodes.
また、第2の局面において、非有効電極は、第1および第2の外部端子電極のいずれとも接しないように形成されていることが好ましい。
In the second aspect, it is preferable that the non-effective electrode is formed so as not to be in contact with any of the first and second external terminal electrodes.
この発明に係る積層セラミックコンデンサにおいて、誘電体セラミックのCu含有量は、主成分としてのBaTiO3系セラミックを100モル部としたとき、0.1~2モル部であることが好ましい。
In the multilayer ceramic capacitor according to the present invention, the Cu content of the dielectric ceramic is preferably 0.1 to 2 mole parts when the BaTiO 3 ceramic as a main component is taken as 100 mole parts.
また、上述のCuと固溶体または合金を作りうる金属としては、たとえばNiがある。
Further, as a metal capable of forming a solid solution or alloy with the above-mentioned Cu, for example, there is Ni.
この発明は、また、積層セラミックコンデンサの製造方法にも向けられる。
The present invention is also directed to a method for manufacturing a multilayer ceramic capacitor.
この発明に係る積層セラミックコンデンサの製造方法は、BaTiO3系セラミックを主成分としかつCuを副成分として含む誘電体セラミック材料を含む、複数の積層された誘電体セラミックグリーン層と、Cuと固溶体または合金を作り得る金属を含みかつ誘電体セラミックグリーン層間の特定の界面に沿って形成された複数の容量形成用電極とをもって構成され、容量形成用電極が分布する容量形成部と容量形成部を積層方向に挟むように位置する外層部とからなり、外層部には、最外層に位置する容量形成用電極と平行に延びかつCuと固溶体または合金を作り得る金属を含む非有効電極が形成されている、生のコンデンサ本体を用意する工程と、生のコンデンサ本体を焼成する工程と、容量形成用電極の特定のものとそれぞれ電気的に接続されるようにコンデンサ本体の外表面上に、第1および第2の外部端子電極を形成する工程とを備え、焼成工程において、金属との間で固溶体または合金を作るようにして、外層部にある誘電体セラミック材料に含まれるCuの一部を非有効電極によって吸収させることを特徴としている。
A method of manufacturing a multilayer ceramic capacitor according to the present invention includes a plurality of stacked dielectric ceramic green layers including a dielectric ceramic material containing a BaTiO 3 ceramic as a main component and Cu as a subcomponent, and Cu and a solid solution or Consists of a plurality of capacitance forming electrodes including a metal capable of forming an alloy and formed along a specific interface between dielectric ceramic green layers, and the capacitance forming portion and the capacitance forming portion are laminated. The outer layer portion is positioned so as to be sandwiched in the direction, and the outer layer portion is formed with an ineffective electrode including a metal that extends in parallel with the capacitance forming electrode positioned in the outermost layer and can form a solid solution or alloy with Cu. A process of preparing a raw capacitor body, a process of firing the raw capacitor body, and a specific one of the capacitance forming electrodes Forming the first and second external terminal electrodes on the outer surface of the capacitor body so as to be connected to each other, and forming a solid solution or alloy with the metal in the firing step, It is characterized in that a part of Cu contained in the dielectric ceramic material in the outer layer portion is absorbed by the ineffective electrode.
コンデンサ本体における外層部に含まれるCuは、焼成工程において、容量形成部に向かって拡散しようとするが、この発明によれば、このように拡散しようとするCuは非有効電極によって吸収される。そのため、特に最外層に位置する容量形成用電極によって多量のCuが吸収されることがない。その結果、最外層に位置する容量形成用電極のCu濃度は、中央に位置する容量形成用電極のCu濃度の5倍以下にまで抑えられる。
Cu contained in the outer layer portion of the capacitor main body tends to diffuse toward the capacitance forming portion in the firing step. According to the present invention, Cu to be diffused is absorbed by the ineffective electrode. Therefore, a large amount of Cu is not absorbed particularly by the capacitance forming electrode located in the outermost layer. As a result, the Cu concentration of the capacitance forming electrode located in the outermost layer is suppressed to 5 times or less than the Cu concentration of the capacitance forming electrode located in the center.
このようにして、この発明によれば、特に最外層に位置する容量形成用電極においてCuが濃化することを防ぐことによって、当該容量形成用電極での太り減少や平滑性低下を防止でき、これら太り現象や平滑性低下が原因となるデラミネーションやショート不良の発生を抑制することができる。
Thus, according to the present invention, by preventing the concentration of Cu in the capacitor forming electrode located in the outermost layer in particular, it is possible to prevent a decrease in thickness and a decrease in smoothness in the capacitor forming electrode. The occurrence of delamination and short-circuit defects caused by these fattening phenomena and smoothness degradation can be suppressed.
このようなことから、この発明は、誘電体セラミック層の厚みが1層あたり5μm以下であり、容量形成部における誘電体セラミック層の数が30以上であり、外層部の厚みが誘電体セラミック層の1層あたりの厚みの4倍以上である、積層セラミックコンデンサに対して特に有利に適用される。
For this reason, according to the present invention, the thickness of the dielectric ceramic layer is 5 μm or less per layer, the number of dielectric ceramic layers in the capacitance forming portion is 30 or more, and the thickness of the outer layer portion is the dielectric ceramic layer. The present invention is particularly advantageously applied to a multilayer ceramic capacitor having a thickness of 4 times or more per layer.
この発明に係る積層セラミックコンデンサにおいて、非有効電極と最外層に位置する容量形成用電極との距離が、容量形成用電極間の誘電体セラミック層の厚み寸法の0.8倍または1μmのいずれか短い方の寸法以上、かつ容量形成用電極間の誘電体セラミック層の厚み寸法の4倍以下に選ばれると、上述した効果がより確実に達成される。
In the multilayer ceramic capacitor according to the present invention, the distance between the non-effective electrode and the capacitor forming electrode located in the outermost layer is either 0.8 times the thickness dimension of the dielectric ceramic layer between the capacitor forming electrodes or 1 μm. When the thickness is selected to be not less than the shorter dimension and not more than 4 times the thickness dimension of the dielectric ceramic layer between the capacitance forming electrodes, the above-described effect can be achieved more reliably.
また、この発明に係る積層セラミックコンデンサにおいて、非有効電極が第1および第2の外部電極のいずれとも接しないように形成されていると、デラミネーションをより生じさせにくくすることができる。
Further, in the multilayer ceramic capacitor according to the present invention, if the non-effective electrode is formed so as not to be in contact with any of the first and second external electrodes, delamination can be made more difficult to occur.
この発明に係る積層セラミックコンデンサにおいて、誘電体セラミックのCu含有量が、主成分としてのBaTiO3系セラミックを100モル部としたとき、0.1~2モル部の範囲に選ばれると、Cu含有によるCR積などの材料特性改善の効果が確実に得られるとともに、デラミネーションの発生をより確実に抑制することができる。
In the multilayer ceramic capacitor according to the present invention, when the Cu content of the dielectric ceramic is selected in the range of 0.1 to 2 mole parts when the BaTiO 3 based ceramic as a main component is 100 mole parts, The effect of improving the material properties such as the CR product can be obtained with certainty, and the occurrence of delamination can be more reliably suppressed.
1,1a,1b 積層セラミックコンデンサ
2 誘電体セラミック層または誘電体セラミックグリーン層
3,4 容量形成用電極
3(B),4(B) 最外層に位置する容量形成用電極
3(C),4(C) 中央に位置する容量形成用電極
5 コンデンサ本体
6,7 外部端子電極
8 容量形成部
9,10 外層部
11,12,11a,12a,11b,12b 非有効電極 1, 1a, 1b Multilayerceramic capacitor 2 Dielectric ceramic layer or dielectric ceramic green layer 3, 4 Capacitance forming electrodes 3 (B), 4 (B) Capacitance forming electrodes 3 (C), 4 located in the outermost layer (C) Capacitor forming electrode located in the center 5 Capacitor body 6, 7 External terminal electrode 8 Capacitor forming part 9, 10 Outer layer part 11, 12, 11a, 12a, 11b, 12b Ineffective electrode
2 誘電体セラミック層または誘電体セラミックグリーン層
3,4 容量形成用電極
3(B),4(B) 最外層に位置する容量形成用電極
3(C),4(C) 中央に位置する容量形成用電極
5 コンデンサ本体
6,7 外部端子電極
8 容量形成部
9,10 外層部
11,12,11a,12a,11b,12b 非有効電極 1, 1a, 1b Multilayer
図1は、この発明の第1の実施形態による積層セラミックコンデンサ1を図解的に示す断面図である。図2は、図1の部分Aを拡大して示す図である。
FIG. 1 is a cross-sectional view schematically showing a multilayer ceramic capacitor 1 according to a first embodiment of the present invention. FIG. 2 is an enlarged view of a portion A in FIG.
積層セラミックコンデンサ1は、複数の積層された誘電体セラミック層2と、誘電体セラミック層2間の特定の界面に沿って形成された複数の容量形成用電極3および4とをもって構成された、コンデンサ本体5を備えている。
The multilayer ceramic capacitor 1 includes a plurality of laminated dielectric ceramic layers 2 and a plurality of capacitance forming electrodes 3 and 4 formed along a specific interface between the dielectric ceramic layers 2. A main body 5 is provided.
誘電体セラミック層2は、BaTiO3系セラミックを主成分としかつCuを副成分として含む誘電体セラミックから構成される。
The dielectric ceramic layer 2 is made of a dielectric ceramic containing a BaTiO 3 ceramic as a main component and Cu as a subcomponent.
この誘電体セラミックは、より具体的には、前述の特許文献1に開示されるものであり、主成分となるBaTiO3系セラミックは、一般式ABO3で表されるものである。ここで、Aは、Baを必ず含み、さらにCaおよびSrの少なくとも一方を含むことがあり、Bは、Tiを必ず含み、Zrを含むことがある。
More specifically, this dielectric ceramic is disclosed in the above-mentioned Patent Document 1, and the BaTiO 3 -based ceramic as the main component is represented by the general formula ABO 3 . Here, A necessarily includes Ba and may further include at least one of Ca and Sr, and B necessarily includes Ti and may include Zr.
また、副成分としてのCuは、主成分としてのBaTiO3系セラミックを100モル部としたとき、0.1~2モル部の範囲で含有することが好ましい。
Further, Cu as an accessory component is preferably contained in a range of 0.1 to 2 mole parts, when 100 mole parts of the BaTiO 3 based ceramic as a main component is taken as 100 mole parts.
誘電体セラミックは、さらに、La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、YbおよびYのうちの少なくとも1種の希土類元素、Mn、NiおよびMgのうちの少なくとも1種の金属、ならびに焼結助剤としてのSiを含んでいてもよい。
The dielectric ceramic is further composed of at least one rare earth element selected from La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Y, Mn, Ni and Mg. At least one of these metals and Si as a sintering aid may be included.
容量形成用電極3および4は、導電成分として、たとえばNiのようなCuと固溶体または合金を作り得る金属を含んでいる。
The capacitance forming electrodes 3 and 4 include a metal that can form a solid solution or an alloy with Cu such as Ni, for example, as a conductive component.
積層セラミックコンデンサ1は、コンデンサ本体5の各端部上にそれぞれ形成された第1および第2の外部端子電極6および7を備えている。第1の外部端子電極6は第1の容量形成用電極3と電気的に接続され、第2の外部端子電極7は第2の容量形成用電極4と電気的に接続される。そして、第1の容量形成用電極3と第2の容量形成用電極4とは、積層方向に関して交互に配置される。
The multilayer ceramic capacitor 1 includes first and second external terminal electrodes 6 and 7 formed on each end of the capacitor body 5. The first external terminal electrode 6 is electrically connected to the first capacitance forming electrode 3, and the second external terminal electrode 7 is electrically connected to the second capacitance forming electrode 4. The first capacitor forming electrodes 3 and the second capacitor forming electrodes 4 are alternately arranged in the stacking direction.
コンデンサ本体5は、容量形成用電極3および4が分布する容量形成部8と容量形成部8を積層方向に挟むように位置する外層部9および10とから構成される。この実施形態では、誘電体セラミック層2の1層あたりの厚みは5μm以下とされ、容量形成部8にある誘電体セラミック層2の層数は30層以上とされ、外層部9および10の各々の厚みは、誘電体セラミック層2の1層あたりの厚みの4倍以上とされている。
The capacitor body 5 includes a capacitance forming portion 8 in which the capacitance forming electrodes 3 and 4 are distributed, and outer layer portions 9 and 10 positioned so as to sandwich the capacitance forming portion 8 in the stacking direction. In this embodiment, the thickness of each dielectric ceramic layer 2 is 5 μm or less, the number of dielectric ceramic layers 2 in the capacitance forming portion 8 is 30 or more, and each of the outer layer portions 9 and 10 is The thickness of the dielectric ceramic layer 2 is at least four times the thickness of each dielectric ceramic layer 2.
外層部9および10には、それぞれ、最外層に位置する容量形成用電極3(B)および4(B)と平行に延びる非有効電極11および12が形成されている。非有効電極11および12は、容量形成用電極3および4と同程度の面積を有し、また、第1および第2の外部端子電極6および7のいずれとも接しないように形成されている。非有効電極11および12は、後述する積層セラミックコンデンサ1の製造過程において実施される焼成工程の結果、誘電体セラミック層2を構成する誘電体セラミックに含まれるCuに由来するCuを含んで構成された固溶体または合金を含んでいる。
In the outer layer portions 9 and 10, non-effective electrodes 11 and 12 extending in parallel with the capacitance forming electrodes 3 (B) and 4 (B) located in the outermost layer are formed, respectively. The non-effective electrodes 11 and 12 have the same area as the capacitance forming electrodes 3 and 4 and are formed so as not to be in contact with any of the first and second external terminal electrodes 6 and 7. The non-effective electrodes 11 and 12 are configured to include Cu derived from Cu included in the dielectric ceramic constituting the dielectric ceramic layer 2 as a result of a firing process performed in the manufacturing process of the multilayer ceramic capacitor 1 described later. Solid solution or alloy.
また、容量形成用電極3および4についても、積層セラミックコンデンサ1の製造過程において実施される焼成工程の結果、誘電体セラミックに含まれるCuに由来するCuを含むが、複数の容量形成用電極3および4のうち、最外層に位置する容量形成用電極3(B)および4(B)のCu濃度は、中央に位置する容量形成用電極3(C)および4(C)のCu濃度の5倍以下、好ましくは3倍以下である。
Further, the capacitance forming electrodes 3 and 4 also contain Cu derived from Cu contained in the dielectric ceramic as a result of the firing step performed in the manufacturing process of the multilayer ceramic capacitor 1. 4, the Cu concentration of the capacitance forming electrodes 3 (B) and 4 (B) located in the outermost layer is 5 of the Cu concentration of the capacitance forming electrodes 3 (C) and 4 (C) located in the center. No more than twice, preferably no more than 3 times.
なお、上記のように、最外層に位置する容量形成用電極を「3(B)」および「4(B)」で示し、中央に位置する容量形成用電極を「3(C)」および「4(C)」で示すことによって、他の容量形成用電極と区別したが、特に、このような区別が必要でないときは、容量形成用電極を単に「3」および「4」の参照符号をもって示す。
As described above, the capacitance forming electrodes located in the outermost layer are indicated by “3 (B)” and “4 (B)”, and the capacitance forming electrodes located in the center are indicated by “3 (C)” and “ 4 (C) ”distinguishes it from other capacitor forming electrodes. In particular, when such distinction is not necessary, the capacitor forming electrodes are simply indicated by reference numerals“ 3 ”and“ 4 ”. Show.
この実施形態では、容量形成用電極3および4の合計数が2n(nは自然数)であるため、中央に位置する容量形成用電極として、n番目の容量形成用電極3(C)とn+1番目の容量形成用電極4(C)とを選び、中央に位置する容量形成用電極のCu濃度は、容量形成用電極3(C)のCu濃度と容量形成用電極4(C)のCu濃度との平均値であるということになる。他方、容量形成用電極3および4の合計数が2n+1である場合には、n+1番目の容量形成用電極が中央に位置する容量形成用電極となる。
In this embodiment, since the total number of the capacitance forming electrodes 3 and 4 is 2n (n is a natural number), the nth capacitance forming electrode 3 (C) and the (n + 1) th capacitance forming electrode are located at the center. The capacitance forming electrode 4 (C) is selected, and the Cu concentration of the capacitance forming electrode located in the center is determined by the Cu concentration of the capacitance forming electrode 3 (C) and the Cu concentration of the capacitance forming electrode 4 (C). It means that it is the average value. On the other hand, when the total number of the capacitance forming electrodes 3 and 4 is 2n + 1, the (n + 1) th capacitance forming electrode is a capacitance forming electrode located at the center.
以上のような構成を有する積層セラミックコンデンサ1は、次のようにして製造される。
The multilayer ceramic capacitor 1 having the above-described configuration is manufactured as follows.
図3は、図1に示したコンデンサ本体5を得るために用意されるコンデンサ本体5の生の状態のものを示す断面図である。図1に示した焼結後のコンデンサ本体5に備える要素について用いた参照符号と同様の参照符号を、図3に示したコンデンサ本体5の生の状態のものにおける対応の要素にも用いることにする。
FIG. 3 is a cross-sectional view showing the raw capacitor body 5 prepared to obtain the capacitor body 5 shown in FIG. The same reference numerals as those used for the elements provided in the sintered capacitor body 5 shown in FIG. 1 are used for the corresponding elements in the raw state of the capacitor body 5 shown in FIG. To do.
積層セラミックコンデンサ1を製造するため、まず、図3に示すような生のコンデンサ本体5が用意される。生のコンデンサ本体5は、BaTiO3系セラミックを主成分としかつCuを副成分として含む誘電体セラミック材料を含む、複数の積層された誘電体セラミックグリーン層2と、誘電体セラミックグリーン層2間の特定の界面に沿って形成された複数の容量形成用電極3および4とをもって構成される。
In order to manufacture the multilayer ceramic capacitor 1, first, a raw capacitor body 5 as shown in FIG. 3 is prepared. The raw capacitor body 5 includes a plurality of dielectric ceramic green layers 2 and a dielectric ceramic green layer 2 including a dielectric ceramic material mainly composed of BaTiO 3 -based ceramics and Cu as a minor component. It comprises a plurality of capacitance forming electrodes 3 and 4 formed along a specific interface.
また、生のコンデンサ本体5は、容量形成用電極3および4が分布する容量形成部8と容量形成部8を積層方向に挟むように位置する外層部9および10とからなる。そして、外層部9および10には、それぞれ、非有効電極11および12が形成されている。これら非有効電極11および12は、生のコンデンサ本体5の内部に形成されている段階では、Cuと固溶体または合金を作り得る金属、たとえばNi、PdまたはPtのような金属を含んでいる。
The raw capacitor body 5 includes a capacitance forming portion 8 in which the capacitance forming electrodes 3 and 4 are distributed and outer layer portions 9 and 10 positioned so as to sandwich the capacitance forming portion 8 in the stacking direction. Ineffective layers 11 and 12 are formed on the outer layer portions 9 and 10, respectively. These non-effective electrodes 11 and 12 include a metal that can form a solid solution or alloy with Cu, for example, a metal such as Ni, Pd, or Pt, when it is formed inside the raw capacitor body 5.
次いで、生のコンデンサ本体5が焼成される。
Next, the raw capacitor body 5 is fired.
次いで、図1に示すように、焼結後のコンデンサ本体5における容量形成用電極3および4の特定のものとそれぞれ電気的に接続されるように、第1および第2の外部端子電極6および7がコンデンサ本体5の各端部上に形成される。外部端子電極6および7の形成には、たとえば、導電性ペーストの塗布および焼付けによる方法が適用される。なお、生のコンデンサ本体5の各端部上に外部端子電極6および7のための導電性ペーストを塗布し、生のコンデンサ本体5を焼成する工程において、外部端子電極6および7のための導電性ペーストを同時に焼き付けるようにしてもよい。
Next, as shown in FIG. 1, the first and second external terminal electrodes 6 and 6 are electrically connected to specific ones of the capacitance forming electrodes 3 and 4 in the sintered capacitor body 5, respectively. 7 is formed on each end of the capacitor body 5. For forming the external terminal electrodes 6 and 7, for example, a method by applying and baking a conductive paste is applied. In the step of applying the conductive paste for the external terminal electrodes 6 and 7 on each end of the raw capacitor body 5 and firing the raw capacitor body 5, the conductive material for the external terminal electrodes 6 and 7 is used. The adhesive paste may be baked at the same time.
上述した焼成工程において、前述の誘電体セラミック材料に含まれるCuが、たとえばNiを導電成分として含む容量形成用電極3および4へと拡散しようとする。特に外層部9および10においては誘電体セラミック材料に含まれるCuの絶対量が多いため、非有効電極11および12が形成されない場合には、最外層に位置する容量形成用電極3(B)および4(B)には多量のCuが吸収されることになる。
In the firing step described above, Cu contained in the dielectric ceramic material tends to diffuse to the capacitance forming electrodes 3 and 4 containing, for example, Ni as a conductive component. In particular, in the outer layer portions 9 and 10, since the absolute amount of Cu contained in the dielectric ceramic material is large, when the non-effective electrodes 11 and 12 are not formed, the capacitance forming electrodes 3 (B) and A large amount of Cu is absorbed in 4 (B).
しかしながら、この実施形態では、非有効電極11および12が形成され、非有効電極11および12には、前述したように、Cuと固溶体または合金を作りうる金属が含まれているので、外層部9および10にある誘電体セラミック材料に含まれるCuの一部は、上記金属との間で固溶体または合金を作るようにして、非有効電極11および12によって有利に吸収される。その結果、特に最外層に位置する容量形成用電極3(B)および4(B)においてCuが濃化することが防止され、そのため、太り現象や平滑性低下がもたらされにくくなり、コンデンサ本体5においてデラミネーションやショート不良を生じさせにくくすることができる。
However, in this embodiment, the non-effective electrodes 11 and 12 are formed, and the non-effective electrodes 11 and 12 include a metal that can form a solid solution or alloy with Cu as described above. Some of the Cu contained in the dielectric ceramic material at 10 and 10 is advantageously absorbed by the non-effective electrodes 11 and 12 so as to form a solid solution or alloy with the metal. As a result, it is possible to prevent Cu from being concentrated particularly in the capacitance forming electrodes 3 (B) and 4 (B) located in the outermost layer, so that the fattening phenomenon and the smoothness are less likely to be caused. 5, it is possible to make it difficult for delamination and short-circuit defects to occur.
非有効電極11および12が、最外層に位置する容量形成用電極3(B)および4(B)に対して、離れすぎていると、最外層に位置する容量形成用電極3(B)および4(B)におけるCuの濃化を防止する効果が低くなり、他方、近すぎると、非有効電極11および12自身のCuの吸収による太り現象が最外層に位置する容量形成用電極3(B)および4(B)に悪影響を及ぼし、いずれの場合においても、ショート不良がもたらされることがある。このような不都合をより確実に回避するためには、図2によく示されているように、非有効電極11および12と最外層に位置する容量形成用電極3(B)および4(B)との各距離D1は、容量形成用電極3および4間の誘電体セラミック層2の厚み寸法D2の0.8倍または1μmのいずれか短い方の寸法以上、かつ誘電体セラミック層2の厚み寸法D2の4倍以下であることが好ましい。
If the non-effective electrodes 11 and 12 are too far away from the capacitance forming electrodes 3 (B) and 4 (B) located in the outermost layer, the capacitance forming electrodes 3 (B) and B located in the outermost layer 4 (B), the effect of preventing the concentration of Cu is reduced, and on the other hand, if it is too close, the non-effective electrodes 11 and 12 have their capacitance phenomenon due to absorption of Cu by the capacity forming electrode 3 (B ) And 4 (B) are adversely affected, and in either case, a short circuit failure may be caused. In order to avoid such an inconvenience more reliably, as shown in FIG. 2, the non-effective electrodes 11 and 12 and the capacitance forming electrodes 3 (B) and 4 (B) located in the outermost layer are used. Each distance D1 is 0.8 times the thickness dimension D2 of the dielectric ceramic layer 2 between the capacitance forming electrodes 3 and 4 or 1 μm, whichever is shorter, and the thickness dimension of the dielectric ceramic layer 2 It is preferably 4 times or less of D2.
なお、最外層に位置する容量形成用電極3(B)および4(B)のCu濃度は、通常の場合、中央に位置する容量形成用電極3(C)および4(C)のCu濃度より高くなる。しかしながら、前述した焼成工程における非有効電極11および12によるCu吸収作用が強く働くとともに、非有効電極11および12が、それぞれ、最外層に位置する容量形成用電極3(B)および4(B)にかなり接近して形成された場合などには、最外層に位置する容量形成用電極3(B)および4(B)のCu濃度は、中央に位置する容量形成用電極3(C)および4(C)のCu濃度より低くなることもあり得る。
Note that the Cu concentration of the capacitance forming electrodes 3 (B) and 4 (B) located in the outermost layer is usually higher than the Cu concentration of the capacitance forming electrodes 3 (C) and 4 (C) located in the center. Get higher. However, the Cu-absorbing action by the non-effective electrodes 11 and 12 in the firing step described above is strong, and the non-effective electrodes 11 and 12 are capacitance forming electrodes 3 (B) and 4 (B), respectively, located in the outermost layer. In the case where the capacitor forming electrodes 3 (B) and 4 (B) located in the outermost layer are formed, the Cu concentration of the capacitor forming electrodes 3 (C) and 4 located in the center is the same. It may be lower than the Cu concentration of (C).
図4は、この発明の第2の実施形態を説明するための図2に対応する図である。図4において、図2に示した要素に相当する要素には同様の参照符号を付し、重複する説明は省略する。
FIG. 4 is a diagram corresponding to FIG. 2 for explaining the second embodiment of the present invention. 4, elements corresponding to those shown in FIG. 2 are denoted by the same reference numerals, and redundant description is omitted.
第2の実施形態では、外層部9において、複数、たとえば5枚の非有効電極11が互いに平行に延びるように形成されていることを特徴としている。図4において図示しないが、他方の外層部10においても、同様に、複数の非有効電極12が互いに平行に延びるように形成されている。この実施形態によれば、非有効電極11および12による作用をより確実に発揮させることができる。
The second embodiment is characterized in that a plurality of, for example, five non-effective electrodes 11 are formed in the outer layer portion 9 so as to extend in parallel with each other. Although not shown in FIG. 4, the other non-effective electrodes 12 are similarly formed in the other outer layer portion 10 so as to extend in parallel with each other. According to this embodiment, the effect | action by the non-effective electrodes 11 and 12 can be exhibited more reliably.
図5は、この発明の第3の実施形態を説明するための図1に対応する図である。図5において、図1に示した要素に相当する要素には同様の参照符号を付し、重複する説明は省略する。
FIG. 5 is a view corresponding to FIG. 1 for explaining the third embodiment of the present invention. In FIG. 5, elements corresponding to those shown in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted.
第3の実施形態による積層セラミックコンデンサ1aでは、非有効電極11aおよび12aの各々が、複数部分、たとえば4つの部分に分割されていることを特徴としている。非有効電極11aおよび12aの各々は、さらに多数の部分に分割されてもよい。この実施形態によれば、非有効電極11aおよび12aの各々の総面積を、図1に示した非有効電極11および12の各々の面積より小さくすることができ、このように総面積を小さくすることができると、コスト面において有利になる場合がある。
The multilayer ceramic capacitor 1a according to the third embodiment is characterized in that each of the non-effective electrodes 11a and 12a is divided into a plurality of parts, for example, four parts. Each of the non-effective electrodes 11a and 12a may be further divided into a number of parts. According to this embodiment, the total area of each of the non-effective electrodes 11a and 12a can be made smaller than the area of each of the non-effective electrodes 11 and 12 shown in FIG. 1, thus reducing the total area. This can be cost effective.
図6は、この発明の第4の実施形態を説明するための図1に対応する図である。図6において、図1に示した要素に相当する要素には同様の参照符号を付し、重複する説明は省略する。
FIG. 6 is a view corresponding to FIG. 1 for explaining the fourth embodiment of the present invention. In FIG. 6, elements corresponding to those shown in FIG. 1 are given the same reference numerals, and redundant description is omitted.
第4の実施形態による積層セラミックコンデンサ1bでは、非有効電極11bおよび12bがコンデンサ本体5のいずれか一方の端面にまで達し、それぞれ、第1および第2の外部端子電極6および7と接するように形成されていることを特徴としている。この実施形態の場合、たとえば第1の実施形態の場合と比べて、非有効電極11bおよび12b自身のCu吸収による太り現象のためにデラミネーションを生じさせる可能性が増し、好ましくないが、このような実施形態も、この発明の範囲内にあることを明示する意義がある。
In the multilayer ceramic capacitor 1b according to the fourth embodiment, the ineffective electrodes 11b and 12b reach one of the end faces of the capacitor body 5 so as to be in contact with the first and second external terminal electrodes 6 and 7, respectively. It is characterized by being formed. In the case of this embodiment, for example, compared to the case of the first embodiment, the possibility of delamination increases due to the fat phenomenon due to Cu absorption of the ineffective electrodes 11b and 12b themselves, which is not preferable. These embodiments are also meaningful to clearly show that they are within the scope of the present invention.
次に、この発明による効果を確認するために実施した実験例について説明する。
Next, experimental examples carried out to confirm the effects of the present invention will be described.
[実験例1]
出発原料として、BaCO3、CaCO3、SrCO3およびTiO2を用意した。これらの原料を、表1に示すセラミック組成物のうちの、ペロブスカイト構造を示す一般式ABO3で表わされるチタン酸バリウム系固溶体の1種である(Ba1-w-xCawSrx)k(Ti1-yZry)O3の組成物が得られるように秤量した。その後、これら秤量済み原料を、ボールミルで湿式混合し、粉砕した後、乾燥し、空気中にて950~1150℃の温度で2時間仮焼して、チタン酸バリウム系固溶体を得た。 [Experimental Example 1]
BaCO 3 , CaCO 3 , SrCO 3 and TiO 2 were prepared as starting materials. These raw materials are one of barium titanate-based solid solutions represented by the general formula ABO 3 having a perovskite structure in the ceramic compositions shown in Table 1 (Ba 1-wx Ca w Sr x ) k. Weighed to obtain a composition of (Ti 1-y Zr y ) O 3 . Thereafter, these weighed raw materials were wet-mixed with a ball mill, pulverized, dried, and calcined in air at a temperature of 950 to 1150 ° C. for 2 hours to obtain a barium titanate solid solution.
出発原料として、BaCO3、CaCO3、SrCO3およびTiO2を用意した。これらの原料を、表1に示すセラミック組成物のうちの、ペロブスカイト構造を示す一般式ABO3で表わされるチタン酸バリウム系固溶体の1種である(Ba1-w-xCawSrx)k(Ti1-yZry)O3の組成物が得られるように秤量した。その後、これら秤量済み原料を、ボールミルで湿式混合し、粉砕した後、乾燥し、空気中にて950~1150℃の温度で2時間仮焼して、チタン酸バリウム系固溶体を得た。 [Experimental Example 1]
BaCO 3 , CaCO 3 , SrCO 3 and TiO 2 were prepared as starting materials. These raw materials are one of barium titanate-based solid solutions represented by the general formula ABO 3 having a perovskite structure in the ceramic compositions shown in Table 1 (Ba 1-wx Ca w Sr x ) k. Weighed to obtain a composition of (Ti 1-y Zr y ) O 3 . Thereafter, these weighed raw materials were wet-mixed with a ball mill, pulverized, dried, and calcined in air at a temperature of 950 to 1150 ° C. for 2 hours to obtain a barium titanate solid solution.
他方、表1に示すセラミック組成物のうちの、副成分としてのCu、R(La、Ce、Pr、Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Tm、YbおよびY)、Mg、MnならびにNiの各酸化物である、CuO、La2O3、CeO2、Pr6O11、Nd2O3、Sm2O3、Eu2O3、Gd2O3、Tb4O7、Dy2O3、Ho2O3、Er2O3、Tm2O3、Yb2O3、Y2O3、MgO、MnOおよびNiOを用意するとともに、焼結助剤(酸化珪素をSiO2換算で30重量%含有したコロイドシリカ溶液)を用意した。
On the other hand, Cu, R (La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Y) as subcomponents of the ceramic composition shown in Table 1; mg, is the oxide of Mn and Ni, CuO, La 2 O 3 , CeO 2, Pr 6 O 11, Nd 2 O 3, Sm 2 O 3, Eu 2 O 3, Gd 2 O 3, Tb 4 O 7 , Dy 2 O 3 , Ho 2 O 3 , Er 2 O 3 , Tm 2 O 3 , Yb 2 O 3 , Y 2 O 3 , MgO, MnO and NiO are prepared, and a sintering aid (silicon oxide is added). A colloidal silica solution containing 30% by weight in terms of SiO 2 was prepared.
次いで、表1に示す所望のセラミック組成物C1~C51が得られるように、チタン酸バリウム系固溶体と副成分の酸化物と焼結助剤とを秤量した。表1において、副成分の酸化物は、チタン酸バリウム系固溶体100モル部に対するモル比で示され、焼結助剤は、チタン酸バリウム系固溶体と副成分の酸化物との合計100重量部に対する重量比で示されている。
Subsequently, the barium titanate solid solution, the subcomponent oxide, and the sintering aid were weighed so that the desired ceramic compositions C1 to C51 shown in Table 1 were obtained. In Table 1, the subcomponent oxide is shown in a molar ratio with respect to 100 mole parts of the barium titanate solid solution, and the sintering aid is based on 100 parts by weight of the total of the barium titanate solid solution and the subcomponent oxide. It is shown in weight ratio.
次に、表1に示したセラミック組成物C1~C51が得られるように秤量したチタン酸バリウム系固溶体と副成分の酸化物と焼結助剤とに、ポリビニルブチラール系バインダおよびエタノールなどの有機溶剤を加えて、ボールミルにより湿式混合し、スラリーを調製した。このスラリーをドクターブレード法によりシート成形し、矩形の誘電体セラミックグリーンシートを得た。
Next, a barium titanate solid solution, subcomponent oxides and sintering aids weighed so as to obtain ceramic compositions C1 to C51 shown in Table 1 were added to an organic solvent such as a polyvinyl butyral binder and ethanol. And wet mixed by a ball mill to prepare a slurry. This slurry was formed into a sheet by a doctor blade method to obtain a rectangular dielectric ceramic green sheet.
次に、グリーンシート上に、Niを導電成分とする導電性ペーストを印刷し、容量形成用電極となる導電性ペースト層を形成した。また、別のグリーンシート上に、Niを導電成分とする導電性ペーストを印刷し、容量形成用電極と同程度の面積を持つ非有効電極となる導電性ペースト層を形成した。
Next, a conductive paste containing Ni as a conductive component was printed on the green sheet to form a conductive paste layer serving as a capacitance forming electrode. Also, a conductive paste containing Ni as a conductive component was printed on another green sheet to form a conductive paste layer serving as an ineffective electrode having the same area as the capacitance forming electrode.
その後、容量形成用電極となる導電性ペースト層が形成されたグリーンシートを、当該導電性ペースト層が引き出されている側が互い違いとなるように積層し、容量形成部において容量形成用電極となる導電性ペースト層を100層積層するとともに、非有効電極となる導電性ペースト層が形成されたグリーンシートを両側の外層部に1枚ずつ積層することによって、生のコンデンサ本体を得た。ここで、焼結後において、容量形成部における誘電体セラミック層の各厚みは2μmとなり、非有効電極については、最外層に位置する容量形成用電極からの距離D1(図2参照)が1μmの位置に形成されるようにした。
Thereafter, the green sheets on which the conductive paste layer to be the capacitance forming electrode is formed are stacked so that the side from which the conductive paste layer is drawn is alternated, and the conductive sheet to be the capacitance forming electrode in the capacitance forming portion. A green capacitor body was obtained by laminating 100 sheets of conductive paste layers and laminating one sheet of green sheet on which conductive paste layers serving as ineffective electrodes were formed on both outer layer portions. Here, after sintering, each thickness of the dielectric ceramic layer in the capacitance forming portion is 2 μm, and for the ineffective electrode, the distance D1 (see FIG. 2) from the capacitance forming electrode located in the outermost layer is 1 μm. It was made to form at a position.
次に、上記生のコンデンサ本体を、N2雰囲気中にて350℃の温度に加熱し、バインダを除去した後、酸素分圧10-9~10-12MPaのH2-N2-H2Oガスからなる還元性雰囲気中において、1000~1400℃の温度範囲内で2時間焼成し、焼結したコンデンサ本体を得た。なお、上記焼成温度については、各セラミック組成物を用いて作製された焼結後のコンデンサ本体を断面研磨し、外層の空隙率が3%以下となる温度に設定した。
Next, the raw capacitor body was heated to a temperature of 350 ° C. in an N 2 atmosphere to remove the binder, and then H 2 —N 2 —H 2 with an oxygen partial pressure of 10 −9 to 10 −12 MPa. In a reducing atmosphere composed of O gas, firing was performed in a temperature range of 1000 to 1400 ° C. for 2 hours to obtain a sintered capacitor body. In addition, about the said baking temperature, the capacitor | condenser main body after sintering produced using each ceramic composition was cross-sectional-polished, and the porosity of the outer layer was set to the temperature used as 3% or less.
その後、得られたコンデンサ本体の両端面に、B2O3-Li2O-SiO2-BaO系のガラスフリットを含有するAgペーストを塗布し、N2雰囲気中において600℃の温度で焼き付け、容量形成用電極と電気的に接続された外部端子電極を形成した。
Thereafter, an Ag paste containing a glass frit of B 2 O 3 —Li 2 O—SiO 2 —BaO system was applied to both end faces of the obtained capacitor body, and baked at a temperature of 600 ° C. in an N 2 atmosphere. An external terminal electrode electrically connected to the capacitance forming electrode was formed.
次に、ニッケルめっき液を用意し、バレルめっき法にてAg外部端子電極上にニッケルめっきを施した。最後に、はんだめっき液を用意し、バレルめっき法にて、このニッケルめっき皮膜上にはんだめっきを施し、試料となる積層セラミックコンデンサを得た。各試料に係る積層セラミックコンデンサは、図1に示すような構造を有し、長さ方向寸法が3.2mm、幅方向寸法が1.6mm、厚み方向寸法が1.6mmであり、誘電体セラミック層の1層あたりの容量形成用電極の重なり面積が3.3mm2であった。
Next, a nickel plating solution was prepared, and nickel plating was performed on the Ag external terminal electrode by a barrel plating method. Finally, a solder plating solution was prepared, and this nickel plating film was solder plated by a barrel plating method to obtain a multilayer ceramic capacitor as a sample. The multilayer ceramic capacitor according to each sample has a structure as shown in FIG. 1, has a lengthwise dimension of 3.2 mm, a widthwise dimension of 1.6 mm, and a thicknesswise dimension of 1.6 mm. The overlapping area of the capacitance forming electrodes per layer was 3.3 mm 2 .
このようにして作製された各試料に係る積層セラミックコンデンサについて、表2に示すように、「ショート不良率」、「デラミネーション」および「WDX強度」の各項目について評価した。なお、これら項目の評価は、次のように行なった。
As shown in Table 2, the multilayer ceramic capacitor according to each sample produced in this way was evaluated for each item of “short defect rate”, “delamination”, and “WDX strength”. These items were evaluated as follows.
「ショート不良率」…各試料に係る積層セラミックコンデンサの中から100個を抜き取り、ショート不良が生じているか否かを評価し、100個中、ショート不良が生じている個数の割合を求めた。
“Short-circuit defect rate”: 100 samples were taken out of the multilayer ceramic capacitors according to each sample, whether or not a short-circuit defect occurred was evaluated, and the ratio of the number of short-circuit defects in 100 was determined.
「デラミネーション」…各試料に係る積層セラミックコンデンサの中から50個を抜き取り、長さ方向寸法および厚み方向寸法によって規定される面を鏡面研磨した後、光学顕微鏡にて最外層に位置する容量形成用電極全域でのデラミネーションの有無を確認し、50個中、デラミネーションが生じている個数の割合を求めた。
"Delamination": 50 capacitors are extracted from the multilayer ceramic capacitors of each sample, and the surface defined by the length and thickness dimensions is mirror-polished, and then the capacitance is formed on the outermost layer with an optical microscope. The presence / absence of delamination in the entire electrode was confirmed, and the ratio of the number of delamination out of 50 was determined.
「WDX強度」…各試料に係る積層セラミックコンデンサの長さ方向寸法および厚み方向寸法によって規定される面を鏡面研磨し、最外層に位置する容量形成用電極と中央に位置する容量形成用電極とでWDX点分析を行なった。最外層に位置する容量形成用電極のCu濃度(Cu/Ni強度比で規定)が中央に位置する容量形成用電極のCu濃度の5倍以下であれば、良好であると判定し、表2では「G」と表示した。なお、後述する表4および表5においては、「NG」と表示されている試料があるが、これらは、最外層に位置する容量形成用電極のCu濃度が中央に位置する容量形成用電極のCu濃度の5倍を超えた場合である。
“WDX strength”: the surface defined by the length-direction dimension and the thickness-direction dimension of the multilayer ceramic capacitor according to each sample is mirror-polished, and a capacitance-forming electrode located at the outermost layer and a capacitance-forming electrode located at the center WDX point analysis was performed. If the Cu concentration (specified by the Cu / Ni intensity ratio) of the capacitance forming electrode located in the outermost layer is 5 times or less than the Cu concentration of the capacitance forming electrode located in the center, it is determined that it is good. Then, “G” is displayed. In Tables 4 and 5 to be described later, there are samples indicated as “NG”, but these are those of the capacitor forming electrode located at the center of the Cu concentration of the capacitor forming electrode located in the outermost layer. This is a case where the Cu concentration exceeds 5 times.
なお、表2における「セラミック組成」は、表1に示した「セラミック組成記号」に対応しており、表2に示した各試料において適用した誘電体セラミックの組成を示している。
The “ceramic composition” in Table 2 corresponds to the “ceramic composition symbol” shown in Table 1, and indicates the composition of the dielectric ceramic applied in each sample shown in Table 2.
表2から、外層部に含まれるCuが非有効電極に固溶することで、容量形成用電極へのCuの固溶が抑えられ、その結果、最外層に位置する容量形成用電極のCu濃度を、中央に位置する容量形成用電極のCu濃度の5倍以下にまで均一化させ得ることがわかった。そして、このように、容量形成用電極においてCuが濃化することを防ぐことによって、容量形成用電極の太りや平滑性低下によるデラミネーションやショート不良を抑えることができた。
From Table 2, Cu contained in the outer layer portion is dissolved in the ineffective electrode, so that the solid solution of Cu in the capacitor forming electrode is suppressed, and as a result, the Cu concentration of the capacitor forming electrode located in the outermost layer is reduced. Can be made uniform to 5 times or less of the Cu concentration of the capacitance forming electrode located in the center. Thus, by preventing the concentration of Cu in the capacitance forming electrode, delamination and short-circuit failure due to the thickness of the capacitance forming electrode and a decrease in smoothness could be suppressed.
[実験例2]
実験例2は、非有効電極に含まれる、Cuと固溶体または合金を作り得る金属を変更しても、この発明の効果が奏されることを確認するために実施したものである。 [Experiment 2]
Experimental Example 2 was carried out in order to confirm that the effect of the present invention was achieved even when the metal that can form a solid solution or alloy with Cu contained in the ineffective electrode was changed.
実験例2は、非有効電極に含まれる、Cuと固溶体または合金を作り得る金属を変更しても、この発明の効果が奏されることを確認するために実施したものである。 [Experiment 2]
Experimental Example 2 was carried out in order to confirm that the effect of the present invention was achieved even when the metal that can form a solid solution or alloy with Cu contained in the ineffective electrode was changed.
非有効電極に含まれる金属を、表3の「非有効電極金属」の欄に示すように、NiからPdまたはPtに変更したことを除いて、実験例1の場合と同様の方法により、各試料に係る積層セラミックコンデンサを作製し、かつ評価を行なった。この評価結果が表3に示されている。なお、誘電体セラミックについては、表1に示したセラミック組成のうち、表3の「セラミック組成」の欄に示した「セラミック組成記号」を有するものについてのみ適用した。
Each of the metals contained in the ineffective electrode was changed from Ni to Pd or Pt as shown in the column of “Ineffective electrode metal” in Table 3, by the same method as in Experimental Example 1, A multilayer ceramic capacitor according to the sample was produced and evaluated. The evaluation results are shown in Table 3. As for the dielectric ceramic, only those having the “ceramic composition symbol” shown in the “ceramic composition” column of Table 3 among the ceramic compositions shown in Table 1 were applied.
表3からわかるように、非有効電極に含まれる金属を変更しても、実験例1の場合と同様の効果が得られた。
As can be seen from Table 3, even if the metal contained in the non-effective electrode was changed, the same effect as in Experimental Example 1 was obtained.
[実験例3]
実験例3は、図2に示すような最外層に位置する容量形成用電極から非有効電極までの距離D1や、容量形成用電極間の誘電体セラミック層の厚みD2といった設計を変更した場合の、この発明の効果への影響を調査するために実施したものである。 [Experiment 3]
Experimental example 3 is a case where the design such as the distance D1 from the capacitance forming electrode to the ineffective electrode located in the outermost layer as shown in FIG. 2 and the thickness D2 of the dielectric ceramic layer between the capacitance forming electrodes is changed. This was carried out in order to investigate the influence on the effect of the present invention.
実験例3は、図2に示すような最外層に位置する容量形成用電極から非有効電極までの距離D1や、容量形成用電極間の誘電体セラミック層の厚みD2といった設計を変更した場合の、この発明の効果への影響を調査するために実施したものである。 [Experiment 3]
Experimental example 3 is a case where the design such as the distance D1 from the capacitance forming electrode to the ineffective electrode located in the outermost layer as shown in FIG. 2 and the thickness D2 of the dielectric ceramic layer between the capacitance forming electrodes is changed. This was carried out in order to investigate the influence on the effect of the present invention.
表4の「実施パターン」の欄に示す(1)~(5)は、それぞれ、次の設計であることを示している。
(1) 誘電体セラミック層の厚みを5μmとし、最外層に位置する容量形成用電極から非有効電極までの距離を1μmとした。
(2) 誘電体セラミック層の厚みを2μmとし、最外層に位置する容量形成用電極から非有効電極までの距離を8μm(=誘電体セラミック層の厚み×4)とした。
(3) 誘電体セラミック層の厚みを2μmとし、最外層に位置する容量形成用電極から非有効電極までの距離を10μm(=誘電体セラミック層の厚み×5)とした。
(4) 誘電体セラミック層の厚みを0.8μmとし、最外層に位置する容量形成用電極から非有効電極までの距離を1μmとした。
(5) 誘電体セラミック層の厚みを0.8μmとし、最外層に位置する容量形成用電極から非有効電極までの距離を0.6μmとした。 (1) to (5) shown in the column “implementation pattern” in Table 4 indicate the following designs.
(1) The thickness of the dielectric ceramic layer was 5 μm, and the distance from the capacitance forming electrode located in the outermost layer to the ineffective electrode was 1 μm.
(2) The thickness of the dielectric ceramic layer was 2 μm, and the distance from the capacitance forming electrode located on the outermost layer to the ineffective electrode was 8 μm (= thickness of the dielectric ceramic layer × 4).
(3) The thickness of the dielectric ceramic layer was 2 μm, and the distance from the capacitance forming electrode located on the outermost layer to the ineffective electrode was 10 μm (= thickness of the dielectric ceramic layer × 5).
(4) The thickness of the dielectric ceramic layer was 0.8 μm, and the distance from the capacitance forming electrode located in the outermost layer to the ineffective electrode was 1 μm.
(5) The thickness of the dielectric ceramic layer was 0.8 μm, and the distance from the capacitance forming electrode located in the outermost layer to the ineffective electrode was 0.6 μm.
(1) 誘電体セラミック層の厚みを5μmとし、最外層に位置する容量形成用電極から非有効電極までの距離を1μmとした。
(2) 誘電体セラミック層の厚みを2μmとし、最外層に位置する容量形成用電極から非有効電極までの距離を8μm(=誘電体セラミック層の厚み×4)とした。
(3) 誘電体セラミック層の厚みを2μmとし、最外層に位置する容量形成用電極から非有効電極までの距離を10μm(=誘電体セラミック層の厚み×5)とした。
(4) 誘電体セラミック層の厚みを0.8μmとし、最外層に位置する容量形成用電極から非有効電極までの距離を1μmとした。
(5) 誘電体セラミック層の厚みを0.8μmとし、最外層に位置する容量形成用電極から非有効電極までの距離を0.6μmとした。 (1) to (5) shown in the column “implementation pattern” in Table 4 indicate the following designs.
(1) The thickness of the dielectric ceramic layer was 5 μm, and the distance from the capacitance forming electrode located in the outermost layer to the ineffective electrode was 1 μm.
(2) The thickness of the dielectric ceramic layer was 2 μm, and the distance from the capacitance forming electrode located on the outermost layer to the ineffective electrode was 8 μm (= thickness of the dielectric ceramic layer × 4).
(3) The thickness of the dielectric ceramic layer was 2 μm, and the distance from the capacitance forming electrode located on the outermost layer to the ineffective electrode was 10 μm (= thickness of the dielectric ceramic layer × 5).
(4) The thickness of the dielectric ceramic layer was 0.8 μm, and the distance from the capacitance forming electrode located in the outermost layer to the ineffective electrode was 1 μm.
(5) The thickness of the dielectric ceramic layer was 0.8 μm, and the distance from the capacitance forming electrode located in the outermost layer to the ineffective electrode was 0.6 μm.
積層セラミックコンデンサの設計を、表4の「実施パターン」の欄に示すように変更したことを除いて、実験例1の場合と同様の方法により、各試料に係る積層セラミックコンデンサを作製し、かつ評価を行なった。この評価結果が表4に示されている。なお、誘電体セラミックについては、表1に示したセラミック組成のうち、表4の「セラミック組成」の欄に示した「セラミック組成記号」を有するものについてのみ適用した。
A multilayer ceramic capacitor according to each sample was produced by the same method as in Experimental Example 1 except that the design of the multilayer ceramic capacitor was changed as shown in the column “Execution pattern” in Table 4. Evaluation was performed. The evaluation results are shown in Table 4. For the dielectric ceramic, only those having the “ceramic composition symbol” shown in the “ceramic composition” column of Table 4 among the ceramic compositions shown in Table 1 were applied.
表4からわかるように、最外層に位置する容量形成用電極から非有効電極までの距離や、容量形成用電極間の誘電体セラミック層の厚みといった設計を変更した場合であっても、実験例1の場合とほぼ同様の効果が得られた。
As can be seen from Table 4, even when the design such as the distance from the capacitance forming electrode located at the outermost layer to the ineffective electrode and the thickness of the dielectric ceramic layer between the capacitance forming electrodes is changed, the experimental example The same effect as in the case of 1 was obtained.
ただし、「実施パターン」が(3)の場合のように、非有効電極が最外層に位置する容量形成用電極から遠くなりすぎたり、(5)の場合のように、非有効電極が最外層に位置する容量形成用電極から近すぎたりすると、非有効電極および/または容量形成用電極が太ることが原因となるショート不良が起こることがあった。
However, the “effective pattern” is too far from the capacitance forming electrode located in the outermost layer as in the case of (3), or the ineffective electrode is in the outermost layer as in (5). If the electrode is too close to the capacitor forming electrode located in the region, a short circuit failure may occur due to the ineffective electrode and / or the capacitor forming electrode becoming fat.
[実験例4]
実験例4は、容量形成用電極の積層数を変更した場合の、この発明の効果への影響を調査するために実施したものである。また、実験例4では、非有効電極のない試料についても評価した。 [Experimental Example 4]
Experimental Example 4 was carried out in order to investigate the influence on the effect of the present invention when the number of stacked capacitance forming electrodes was changed. In Experimental Example 4, a sample without an ineffective electrode was also evaluated.
実験例4は、容量形成用電極の積層数を変更した場合の、この発明の効果への影響を調査するために実施したものである。また、実験例4では、非有効電極のない試料についても評価した。 [Experimental Example 4]
Experimental Example 4 was carried out in order to investigate the influence on the effect of the present invention when the number of stacked capacitance forming electrodes was changed. In Experimental Example 4, a sample without an ineffective electrode was also evaluated.
容量形成用電極の積層数を、表5の「積層数」の欄に示すように変更したことを除いて、実験例1の場合と同様の方法により、各試料に係る積層セラミックコンデンサを作製した。「積層数」が増えるということは、それに従って、外層が薄くなるということを意味している。なお、「積層数」が「100」の試料については、実験例1における対応の試料と同等である。また、表5の試料350~356は、非有効電極のない比較用試料である。また、誘電体セラミックについては、表1に示したセラミック組成のうち、表5の「セラミック組成」の欄に示した「セラミック組成記号」を有するものについてのみ適用した。
A multilayer ceramic capacitor according to each sample was manufactured by the same method as in Experimental Example 1 except that the number of stacked capacitance forming electrodes was changed as shown in the column “Number of stacked layers” in Table 5. . An increase in the “number of layers” means that the outer layer becomes thinner accordingly. Note that the sample with “100” is the same as the corresponding sample in Experimental Example 1. Samples 350 to 356 in Table 5 are comparative samples without ineffective electrodes. As for the dielectric ceramic, only those having the “ceramic composition symbol” shown in the “ceramic composition” column of Table 5 among the ceramic compositions shown in Table 1 were applied.
そして、各試料に係る積層セラミックコンデンサについて、実験例1の場合と同様の方法により、評価を行なった。この評価結果が表5に示されている。
Then, the multilayer ceramic capacitor according to each sample was evaluated by the same method as in Experimental Example 1. The evaluation results are shown in Table 5.
表5からわかるように、容量形成用電極の積層数を変えても、基本的には、実験例1の場合と同様の効果が得られた。
As can be seen from Table 5, basically, the same effect as in Experimental Example 1 was obtained even when the number of stacked layers for forming the capacitance was changed.
なお、外層部が薄くなると、外層部の総Cu量が少なくなるため、最外層に位置する容量形成用電極へのCu固溶は減り、不良が起こりにくくなることが予想される。しかし、非有効電極のない試料350~356間の比較からわかるとおり、積層数が増え、外層部が薄くなると、外層部による束縛が弱くなり、デラミネーションは発生しやすくなる傾向がある。このことから、この発明は、容量形成用電極の積層数がたとえば10層のような積層数が少ないものよりも、積層数が多く、外層部が薄いものほど、より効果的に適用されると言える。
In addition, since the total amount of Cu in the outer layer portion decreases as the outer layer portion becomes thinner, it is expected that the Cu solid solution in the capacitance forming electrode located in the outermost layer is reduced and defects are less likely to occur. However, as can be seen from a comparison between samples 350 to 356 having no ineffective electrode, when the number of stacked layers increases and the outer layer portion becomes thinner, the binding by the outer layer portion becomes weaker and delamination tends to occur. From this, the present invention is more effectively applied as the number of laminated layers of the capacity forming electrode is larger than the number of laminated layers, such as 10 layers, and the outer layer portion is thinner. I can say that.
[実験例5]
実験例5は、非有効電極の形状や配置などを変更した場合の、この発明の効果への影響を調査するために実施したものである。 [Experimental Example 5]
Experimental Example 5 was carried out in order to investigate the influence on the effect of the present invention when the shape or arrangement of the ineffective electrode was changed.
実験例5は、非有効電極の形状や配置などを変更した場合の、この発明の効果への影響を調査するために実施したものである。 [Experimental Example 5]
Experimental Example 5 was carried out in order to investigate the influence on the effect of the present invention when the shape or arrangement of the ineffective electrode was changed.
表6の「実施パターン」の欄に示すA~Cは、それぞれ、次の設計であることを示している。
A. 図4に示すように、各々5枚の非有効電極を双方の外層部に積層した。非有効電極間の間隔を1μmとした。
B. 図5に示すように、非有効電極を、各々の面積が0.8mm2である4つの部分に分割した。
C. 図6に示すように、非有効電極の一方端縁がコンデンサ本体の端面にまで達するように形成した。 A to C shown in the “execution pattern” column of Table 6 indicate the following designs, respectively.
A. As shown in FIG. 4, five non-effective electrodes were laminated on both outer layer portions. The interval between the non-effective electrodes was 1 μm.
B. As shown in FIG. 5, the non-effective electrode was divided into four parts each having an area of 0.8 mm 2 .
C. As shown in FIG. 6, the non-effective electrode was formed so that one end edge reached the end face of the capacitor body.
A. 図4に示すように、各々5枚の非有効電極を双方の外層部に積層した。非有効電極間の間隔を1μmとした。
B. 図5に示すように、非有効電極を、各々の面積が0.8mm2である4つの部分に分割した。
C. 図6に示すように、非有効電極の一方端縁がコンデンサ本体の端面にまで達するように形成した。 A to C shown in the “execution pattern” column of Table 6 indicate the following designs, respectively.
A. As shown in FIG. 4, five non-effective electrodes were laminated on both outer layer portions. The interval between the non-effective electrodes was 1 μm.
B. As shown in FIG. 5, the non-effective electrode was divided into four parts each having an area of 0.8 mm 2 .
C. As shown in FIG. 6, the non-effective electrode was formed so that one end edge reached the end face of the capacitor body.
積層セラミックコンデンサの設計を、表6の「実施パターン」の欄に示すように変更したことを除いて、実験例1の場合と同様の方法により、各試料に係る積層セラミックコンデンサを作製し、かつ評価を行なった。この評価結果が表6に示されている。なお、誘電体セラミックについては、表1に示したセラミック組成のうち、表6の「セラミック組成」の欄に示した「セラミック組成記号」を有するものについてのみ適用した。
A multilayer ceramic capacitor according to each sample was prepared by the same method as in Experimental Example 1, except that the design of the multilayer ceramic capacitor was changed as shown in the column “Execution pattern” in Table 6. Evaluation was performed. The evaluation results are shown in Table 6. As for the dielectric ceramic, only those having the “ceramic composition symbol” shown in the “ceramic composition” column of Table 6 among the ceramic compositions shown in Table 1 were applied.
表6からわかるように、非有効電極の形状や配置などを変更した場合でも、基本的には、実験例1の場合と同様の効果が得られた。
As can be seen from Table 6, even when the shape and arrangement of the non-effective electrodes were changed, basically the same effects as those in Experimental Example 1 were obtained.
ただし、「実施パターン」がCの場合のように、非有効電極の一方端縁がコンデンサ本体の端面にまで達していると、「セラミック組成」がC12やC34の場合のように、Cu含有量が2モル部を超える誘電体セラミックを適用すると、デラミネーションが発生することがあった。このことから、Cu含有量は、2モル部以下であることが望ましいことがわかる。
However, if the one end edge of the ineffective electrode reaches the end face of the capacitor body as in the case where the “implementation pattern” is C, the Cu content is the same as in the case where the “ceramic composition” is C12 or C34. When a dielectric ceramic exceeding 2 mole parts is applied, delamination may occur. From this, it can be seen that the Cu content is desirably 2 mol parts or less.
Claims (7)
- BaTiO3系セラミックを主成分としかつCuを副成分として含む誘電体セラミックからなる、複数の積層された誘電体セラミック層と、Cuと固溶体または合金を作り得る金属を含みかつ前記誘電体セラミック層間の特定の界面に沿って形成された複数の容量形成用電極とをもって構成された、コンデンサ本体と、
前記容量形成用電極の特定のものとそれぞれ電気的に接続されるように前記コンデンサ本体の外表面上に形成された、第1および第2の外部端子電極と
を備え、
前記容量形成用電極は、前記誘電体セラミックに含まれる前記Cuに由来するCuをさらに含み、複数の前記容量形成用電極のうち、最外層に位置する容量形成用電極のCu濃度は、中央に位置する容量形成用電極のCu濃度の5倍以下である、
積層セラミックコンデンサ。 A plurality of laminated dielectric ceramic layers comprising a dielectric ceramic containing a BaTiO 3 ceramic as a main component and Cu as a subcomponent; and a metal capable of forming a solid solution or an alloy with Cu, and between the dielectric ceramic layers A capacitor body composed of a plurality of capacitance forming electrodes formed along a specific interface;
First and second external terminal electrodes formed on the outer surface of the capacitor body so as to be electrically connected to specific ones of the capacitance forming electrodes,
The capacitor forming electrode further includes Cu derived from the Cu contained in the dielectric ceramic, and the Cu concentration of the capacitor forming electrode located in the outermost layer among the plurality of capacitor forming electrodes is at the center. It is 5 times or less of the Cu concentration of the capacitance forming electrode located.
Multilayer ceramic capacitor. - BaTiO3系セラミックを主成分としかつCuを副成分として含む誘電体セラミックからなる、複数の積層された誘電体セラミック層と、Cuと固溶体または合金を作り得る金属を含みかつ前記誘電体セラミック層間の特定の界面に沿って形成された複数の容量形成用電極とをもって構成された、コンデンサ本体と、
前記容量形成用電極の特定のものとそれぞれ電気的に接続されるように前記コンデンサ本体の外表面上に形成された、第1および第2の外部端子電極と
を備え、
前記コンデンサ本体は、前記容量形成用電極が分布する容量形成部と前記容量形成部を積層方向に挟むように位置する外層部とからなり、
前記外層部には、最外層に位置する前記容量形成用電極と平行に延びかつ前記誘電体セラミックに含まれる前記Cuに由来するCuを含んで構成された固溶体または合金を含む非有効電極が形成されている、
積層セラミックコンデンサ。 A plurality of laminated dielectric ceramic layers comprising a dielectric ceramic containing a BaTiO 3 ceramic as a main component and Cu as a subcomponent; and a metal capable of forming a solid solution or an alloy with Cu, and between the dielectric ceramic layers A capacitor body composed of a plurality of capacitance forming electrodes formed along a specific interface;
First and second external terminal electrodes formed on the outer surface of the capacitor body so as to be electrically connected to specific ones of the capacitance forming electrodes,
The capacitor body includes a capacitance forming portion in which the capacitance forming electrodes are distributed and an outer layer portion positioned so as to sandwich the capacitance forming portion in the stacking direction.
In the outer layer portion, an ineffective electrode including a solid solution or an alloy extending in parallel with the capacitance forming electrode located in the outermost layer and including Cu derived from Cu contained in the dielectric ceramic is formed. Being
Multilayer ceramic capacitor. - 前記非有効電極と前記最外層に位置する容量形成用電極との距離は、前記容量形成用電極間の前記誘電体セラミック層の厚み寸法の0.8倍または1μmのいずれか短い方の寸法以上、かつ前記容量形成用電極間の前記誘電体セラミック層の厚み寸法の4倍以下である、請求項2に記載の積層セラミックコンデンサ。 The distance between the non-effective electrode and the capacitor forming electrode located on the outermost layer is not less than 0.8 times the thickness of the dielectric ceramic layer between the capacitor forming electrodes or 1 μm, whichever is shorter The multilayer ceramic capacitor according to claim 2, wherein the thickness is 4 times or less the thickness dimension of the dielectric ceramic layer between the capacitance forming electrodes.
- 前記非有効電極は、前記第1および第2の外部端子電極のいずれとも接しないように形成されている、請求項2に記載の積層セラミックコンデンサ。 The multilayer ceramic capacitor according to claim 2, wherein the non-effective electrode is formed so as not to be in contact with any of the first and second external terminal electrodes.
- 前記誘電体セラミックのCu含有量は、主成分としてのBaTiO3系セラミックを100モル部としたとき、0.1~2モル部である、請求項1または2に記載の積層セラミックコンデンサ。 The multilayer ceramic capacitor according to claim 1 or 2, wherein the Cu content of the dielectric ceramic is 0.1 to 2 mole parts, based on 100 mole parts of BaTiO 3 ceramic as a main component.
- 前記Cuと固溶体または合金を作り得る金属はNiを含む、請求項1または2に記載の積層セラミックコンデンサ。 The multilayer ceramic capacitor according to claim 1 or 2, wherein the metal capable of forming a solid solution or alloy with Cu includes Ni.
- BaTiO3系セラミックを主成分としかつCuを副成分として含む誘電体セラミック材料を含む、複数の積層された誘電体セラミックグリーン層と、Cuと固溶体または合金を作り得る金属を含みかつ前記誘電体セラミックグリーン層間の特定の界面に沿って形成された複数の容量形成用電極とをもって構成され、前記容量形成用電極が分布する容量形成部と前記容量形成部を積層方向に挟むように位置する外層部とからなり、前記外層部には、最外層に位置する前記容量形成用電極と平行に延びかつCuと固溶体または合金を作り得る金属を含む非有効電極が形成されている、生のコンデンサ本体を用意する工程と、
前記生のコンデンサ本体を焼成する工程と、
前記容量形成用電極の特定のものとそれぞれ電気的に接続されるように前記コンデンサ本体の外表面上に、第1および第2の外部端子電極を形成する工程と
を備え、
前記焼成工程は、前記金属との間で前記固溶体または合金を作るようにして、前記外層部にある前記誘電体セラミック材料に含まれる前記Cuの一部を前記非有効電極によって吸収させる工程を備える、
積層セラミックコンデンサの製造方法。 A dielectric ceramic material comprising a plurality of laminated dielectric ceramic green layers including a dielectric ceramic material mainly composed of BaTiO 3 -based ceramics and Cu as a minor component, and a metal capable of forming a solid solution or alloy with Cu A plurality of capacitance forming electrodes formed along a specific interface between the green layers, and a capacitance forming portion in which the capacitance forming electrodes are distributed and an outer layer portion positioned so as to sandwich the capacitance forming portion in the stacking direction A raw capacitor body having a non-effective electrode formed on the outer layer portion, which is formed in parallel with the capacitance forming electrode located in the outermost layer and includes a metal capable of forming a solid solution or alloy with Cu. A process to prepare;
Firing the raw capacitor body;
Forming first and second external terminal electrodes on the outer surface of the capacitor body so as to be electrically connected to specific ones of the capacitance forming electrodes, respectively.
The firing step includes a step of absorbing a part of the Cu contained in the dielectric ceramic material in the outer layer portion by the ineffective electrode so as to make the solid solution or alloy with the metal. ,
Manufacturing method of multilayer ceramic capacitor.
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