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WO2009054268A1 - METHOD FOR FORMING Cu WIRING - Google Patents

METHOD FOR FORMING Cu WIRING Download PDF

Info

Publication number
WO2009054268A1
WO2009054268A1 PCT/JP2008/068290 JP2008068290W WO2009054268A1 WO 2009054268 A1 WO2009054268 A1 WO 2009054268A1 JP 2008068290 W JP2008068290 W JP 2008068290W WO 2009054268 A1 WO2009054268 A1 WO 2009054268A1
Authority
WO
WIPO (PCT)
Prior art keywords
forming
layer
wiring
wetted
trench
Prior art date
Application number
PCT/JP2008/068290
Other languages
French (fr)
Japanese (ja)
Inventor
Tatsuo Hatano
Atsushi Gomi
Yasushi Mizusawa
Masamichi Hara
Takashi Sakuma
Original Assignee
Tokyo Electron Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Limited filed Critical Tokyo Electron Limited
Publication of WO2009054268A1 publication Critical patent/WO2009054268A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physical Vapour Deposition (AREA)

Abstract

A method for forming a Cu wiring is provided with a step of preparing a structure having a silicon substrate, a Low-k film, which is on the substrate with a trench, and a barrier layer on the film; a step of forming a layer to be wetted, on the barrier layer by CVD by using a metal material to be wetted with Cu; a step of forming a Cu layer by PVD on the layer to be wetted; and a step of heating the silicon substrate to have the Cu layer flow after forming the Cu layer and making Cu flow into a trench.
PCT/JP2008/068290 2007-10-24 2008-10-08 METHOD FOR FORMING Cu WIRING WO2009054268A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007276891A JP2009105289A (en) 2007-10-24 2007-10-24 METHOD OF FORMING Cu WIRING
JP2007-276891 2007-10-24

Publications (1)

Publication Number Publication Date
WO2009054268A1 true WO2009054268A1 (en) 2009-04-30

Family

ID=40579374

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/068290 WO2009054268A1 (en) 2007-10-24 2008-10-08 METHOD FOR FORMING Cu WIRING

Country Status (3)

Country Link
JP (1) JP2009105289A (en)
TW (1) TW200931531A (en)
WO (1) WO2009054268A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013535820A (en) * 2010-07-19 2013-09-12 インターナショナル・ビジネス・マシーンズ・コーポレーション Method and structure for improving the conductivity of narrow copper filled vias
US10121697B2 (en) 2010-08-20 2018-11-06 Micron Technology, Inc. Semiconductor constructions; and methods for providing electrically conductive material within openings

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5616605B2 (en) * 2009-10-16 2014-10-29 株式会社アルバック Method for forming copper thin film
US8399353B2 (en) 2011-01-27 2013-03-19 Tokyo Electron Limited Methods of forming copper wiring and copper film, and film forming system
JP5788785B2 (en) * 2011-01-27 2015-10-07 東京エレクトロン株式会社 Cu wiring forming method and film forming system
JP5767570B2 (en) * 2011-01-27 2015-08-19 東京エレクトロン株式会社 Cu wiring forming method, Cu film forming method, and film forming system
US8859422B2 (en) 2011-01-27 2014-10-14 Tokyo Electron Limited Method of forming copper wiring and method and system for forming copper film
JP2013074173A (en) * 2011-09-28 2013-04-22 Ulvac Japan Ltd Manufacturing method of semiconductor device and semiconductor device
JP5794905B2 (en) * 2011-12-07 2015-10-14 株式会社アルバック Reflow method and semiconductor device manufacturing method
JP2013143442A (en) * 2012-01-10 2013-07-22 Ulvac Japan Ltd Device manufacturing method and manufacturing device
JP2013171940A (en) * 2012-02-20 2013-09-02 Ulvac Japan Ltd Semiconductor device manufacturing method
JP2014033139A (en) * 2012-08-06 2014-02-20 Ulvac Japan Ltd Device manufacturing method
JP5969306B2 (en) * 2012-08-08 2016-08-17 東京エレクトロン株式会社 Method for forming Cu wiring
JP2014086537A (en) * 2012-10-23 2014-05-12 Ulvac Japan Ltd METHOD OF FORMING Cu LAYER AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
JP6310653B2 (en) * 2013-07-08 2018-04-11 株式会社アルバック Method for forming Cu wiring structure
JP2016111047A (en) * 2014-12-02 2016-06-20 東京エレクトロン株式会社 METHOD FOR FORMING Cu WIRING AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
JP6385856B2 (en) 2015-02-26 2018-09-05 東京エレクトロン株式会社 Cu wiring formation method and semiconductor device manufacturing method
US9418934B1 (en) * 2015-06-30 2016-08-16 International Business Machines Corporation Structure and fabrication method for electromigration immortal nanoscale interconnects
US10681778B2 (en) * 2017-11-21 2020-06-09 Watlow Electric Manufacturing Company Integrated heater and method of manufacture

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11340227A (en) * 1998-05-25 1999-12-10 Fujitsu Ltd Semiconductor device and manufacturing method thereof
JP2002075994A (en) * 2000-08-24 2002-03-15 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method
WO2006104853A1 (en) * 2005-03-31 2006-10-05 Tokyo Electron Limited Low-temperature chemical vapor deposition of low-resistivity ruthenium layers
JP2007214387A (en) * 2006-02-09 2007-08-23 Tokyo Electron Ltd Film depositing method, plasma film forming device, and storage medium

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11340227A (en) * 1998-05-25 1999-12-10 Fujitsu Ltd Semiconductor device and manufacturing method thereof
JP2002075994A (en) * 2000-08-24 2002-03-15 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method
WO2006104853A1 (en) * 2005-03-31 2006-10-05 Tokyo Electron Limited Low-temperature chemical vapor deposition of low-resistivity ruthenium layers
JP2007214387A (en) * 2006-02-09 2007-08-23 Tokyo Electron Ltd Film depositing method, plasma film forming device, and storage medium

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013535820A (en) * 2010-07-19 2013-09-12 インターナショナル・ビジネス・マシーンズ・コーポレーション Method and structure for improving the conductivity of narrow copper filled vias
US9392690B2 (en) 2010-07-19 2016-07-12 Globalfoundries Inc. Method and structure to improve the conductivity of narrow copper filled vias
US10121697B2 (en) 2010-08-20 2018-11-06 Micron Technology, Inc. Semiconductor constructions; and methods for providing electrically conductive material within openings
US10879113B2 (en) 2010-08-20 2020-12-29 Micron Technology, Inc. Semiconductor constructions; and methods for providing electrically conductive material within openings

Also Published As

Publication number Publication date
JP2009105289A (en) 2009-05-14
TW200931531A (en) 2009-07-16

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