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WO2009053949A1 - Convertisseur analogique/numérique à modes multiples, système de traitement de signaux et appareil électronique - Google Patents

Convertisseur analogique/numérique à modes multiples, système de traitement de signaux et appareil électronique Download PDF

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Publication number
WO2009053949A1
WO2009053949A1 PCT/IB2008/055336 IB2008055336W WO2009053949A1 WO 2009053949 A1 WO2009053949 A1 WO 2009053949A1 IB 2008055336 W IB2008055336 W IB 2008055336W WO 2009053949 A1 WO2009053949 A1 WO 2009053949A1
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WIPO (PCT)
Prior art keywords
loop
converter
analog
stage
digital
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Application number
PCT/IB2008/055336
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English (en)
Inventor
Berengere Le Men
Hassan Ihs
Original Assignee
Freescale Semiconductor, Inc.
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Publication date
Application filed by Freescale Semiconductor, Inc. filed Critical Freescale Semiconductor, Inc.
Publication of WO2009053949A1 publication Critical patent/WO2009053949A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/392—Arrangements for selecting among plural operation modes, e.g. for multi-standard operation
    • H03M3/394—Arrangements for selecting among plural operation modes, e.g. for multi-standard operation among different orders of the loop filter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/414—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type

Definitions

  • This invention relates to an analog to digital converter, to a signal processing system and to an electronic apparatus.
  • the ADC includes a sigma-delta modulator which is connected with an output to a digital decimator.
  • the digital decimator is connected with an output to a digital high pass filter.
  • the ADC can operate at oversampling rates of 64 times the input frequency for low power application or 128 times the input frequency for high performance applications.
  • a disadvantage of this ADC is that although some power can be saved by switching to a lower oversampling rate, the ADC consumes a large amount of power in the low power application.
  • the present invention provides an analog to digital converter, a signal processing system and an electronic apparatus as described in the accompanying claims. Specific embodiments of the invention are set forth in the dependent claims.
  • Figure 1 schematically shows a block diagram of an first example of an embodiment of an analog to digital converter in a high performance operational mode.
  • Figure 2 schematically shows a block diagram of the example of FIG. 1 in a low power operational mode.
  • Figure 3 schematically shows a block diagram of a second example of an embodiment of an analog to digital converter.
  • Figure 4 schematically shows a block diagram of a first example of an embodiment of a first converter stage that may be used in the examples of figs 1-3.
  • Figure 5 schematically shows a block diagram of a second example of an embodiment of a first converter stage that may be used in the examples of figs 1-3.
  • Figure 6 schematically shows a block diagram of a first example of an embodiment of a second converter stage that may be used in the examples of figs 1-3.
  • Figure 7 schematically shows a block diagram of a second example of an embodiment of a second converter stage that may be used in the examples of figs 1-3.
  • Figure 8 schematically shows a first example of an embodiment of a signal processing system in which an analog to digital converter may be used.
  • Figure 9 schematically shows an example of an embodiment of an electronic apparatus in which an analog to digital converter may be used.
  • Figure 10 schematically shows a second example of an embodiment of a signal processing system in which an analog to digital converter may be used.
  • the ADC 1 may, as shown, include an analog input I, a digital output O, a first loop, a second loop and a loop control input 6.
  • the first loop may include a first converter stage 2 and connect the analog input I and the digital output O.
  • the second loop may connect an intermediate input ⁇ and the digital output O.
  • the second loop may include a second converter stage 3. As shown, the intermediate input ⁇ may be connected to the first loop.
  • the ADC 1 may perform a method as follows. At the analog input I an analog signal X(z) may be presented, which may be converted by the ADC 1 into a digital signal Y t (z). The digital signal Y t (z) may be presented at the digital output O. Via the loop control input 6, in a first mode of the ADC 1 the second loop may be disabled, as is illustrated in FIG. 2. In a second mode of the ADC 1 , the second loop may be enabled, as is illustrated in FIG. 1. When the second loop is disabled (in the first mode), the analog signal X(z) passes through the first loop, but not through the second loop. Hence, in the first mode the analog signal X(z) is processed by the first converter stage 2 but not by the second converter stage 3. . When the second loop is enabled (in the second mode), the analog signal X(z) passes through the first loop and through the second loop. Hence, in the second mode the analog signal X(z) is processed by the first converter stage 2 and by the second converter stage 3.
  • the power consumption of the ADC 1 may be reduced relative to the power consumption in the second mode because less stages are active, while, for example, in the second mode the performance of the ADC 1 can be improved relative to the first mode, since (an) additional stage(s) can process the analog signal X(z). Therefore the digital output signal may, for example, have a smaller step between the digital output values or have less noise.
  • the ADC 1 may include any suitable number of second loops and/or second stages. As shown in the example of FIG. 3, for instance, the ADC 1 may include two or more second loops in a cascade arrangement and may include two or more second stages.
  • the outputs of the stages in the cascade arrangement are connected to the ADC output O, in the examples via a combining unit 5 which combines the signals outputted by each stage.
  • the ADC 1 may have three or more different modes. For example, in a high performance mode, all the second loops may be used, for instance to (at least partially) cancel the quantization noise from the signals of the previous stages, whereas in a normal mode some of the second loops may be switched off, in order to reduce power consumption while still (at least partially) removing quantization noise and in a low-power mode all the second loops may be switched off, in order to minimize the power consumption.
  • the mode of the ADC 1 may be selected based on any suitable criterion.
  • the mode of the ADC 1 may be selected based on the type of analog signal. For instance, in case the analog signal X(z) is an audio signal for which high-quality is less important, such as speech in a phone system, the ADC 1 may be set to the first mode in order to save power consumption from the battery and increase the "talk time", whereas in case the analog signal X(z) is an audio signal for which high-quality is more important, such as music, the ADC 1 may be set to the second mode.
  • a low power mode may be selected automatically when a user of an apparatus selects a voice input of the apparatus to be used and a high power mode may be selected automatically when the user selects a music recording input.
  • the ADC 1 may be part of a signal processing system which includes an ADC controller 10 connected to the loop control input 6 of the ADC 1.
  • the ADC controller 10 may for example control the mode of the ADC 1 based on the type of audio signal or other suitable criterion.
  • the mode of the ADC 1 may for example be controlled based on the frequency characteristics required for the ADC 1 to accurately convert a type of audio signal.
  • the first mode may be a relatively narrow band mode and the second mode may be a relatively wide band mode, the wide band being wider than the narrow band.
  • the audio signal to be converted is a speech signal
  • the narrow band mode may then be selected, whereas in case the audio signal is a non-speech signal, such as music
  • the wide band mode may be selected.
  • a narrow band with a frequency range from 0 to 8kHz is sufficient to characterize speech signals whereas a wide band with an upper limit above 2OkHz, is sufficient to provide good results for non-speech signals, such as music.
  • the ADC controller 10 may control the mode in any manner suitable for the specific implementation.
  • the ADC may e.g. receive a clock signal CLK, which may also referred to as sample rate or frame sync or word sync, from a processor to which the digital output O is provided.
  • the clock signal CLK may for example be used to control the timing of the operations of components of the ADC.
  • the processor may provide different clock signals depending on the type of audio signal to be processed and the ADC controller 10 may include a detector 11 for detecting the type of clock signal.
  • the processor 100 - A - may for instance have two or more clocks 101 ,102 with different frequencies of which a selected clock signal can be selected by a switch 103 which connects the clocks 101 ,102 to a clock output of the processor 100
  • the processor may provide a clock signal with a first frequency in case the audio signal is a speech signal and a clock signal with a second frequency, different from the first frequency in case the audio signal is a music signal.
  • the first frequency may be 20 kHz or less, such as typically 16kHz or 8 kHz and the second frequency may be above 20 kHz, for example 24kHz, 32kHz, 48kHz or 96kHz.
  • the ADC controller 10 may, as shown in FIG. 10, include a frequency detector 1 1 which can detect the frequency of the clock signal and control the ADC 1 to be in the first mode in case the audio signal is a speech signal and be in the second mode in case the audio signal is music.
  • the first loop and the second loop may have any suitable architecture suitable to switch off the second loop without switching off the first loop.
  • the first loop and the second loop may be different branches of the same loop.
  • the first loop forms a first branch while the second loop forms a second branch.
  • the second branch may for example be branched off from the first branch upstream of the output of the first converter stage.
  • the second branch may join the first branch at a node of the first branch downstream of this output of the first converter stage, e.g. downstream of the second converter stage 3.
  • the signal presented at a (in a signal processing direction) downstream end of the second loop may be subtracted from the signal outputted by the first converter stage 2 in the first loop, in order to obtain a signal in which the quantization noise of the first converter stage is reduced or completely removed, as is explained below in more detail with reference to equations 1-4.
  • the second loop may for example have an architecture which includes the first converter stage 2 and the second converter stage 3 in a cascade arrangement, for example a pure cascade arrangement in which the second converter stage 3 is connected with the second stage input only to the first stage output or a semi-cascade arrangement, in which the second converter stage 3 in the converter is not only connected with its input to the output of the first converter stage 2, but also to a node upstream of the first converter output.
  • a cascade arrangement for example a pure cascade arrangement in which the second converter stage 3 is connected with the second stage input only to the first stage output or a semi-cascade arrangement, in which the second converter stage 3 in the converter is not only connected with its input to the output of the first converter stage 2, but also to a node upstream of the first converter output.
  • the second converter stage 3 may be connected to the output of the first converter 2 via a combining unit 4 which is connected with a first input to the first converter output and with a second input to another contact of the first converter 2, in this example to an internal node of the first converter 2 upstream of a quantizer 23, which forms the input of the quantizer 23.
  • the second loop may for example be used to process the analog signal such that a digital signal with a lower amount of noise, e.g. a smaller quantization noise, than in the first loop can be obtained.
  • the second mode may then be referred to as the high performance mode, whereas power may be saved in the first mode, which may therefore be referred to as the low power mode (because the second converter stage 3 is not used in the first mode).
  • the signal presented at a (in a signal processing direction) downstream end of the second loop may be subtracted from the signal outputted by the first converter stage 2 in the first loop.
  • the downstream end of the second loop may for example be connected to the first loop at a node downstream of the first converter stage 2.
  • the downstream end may be connected to the node via a combining unit 5 which can combine the signals from the first loop and the second loop.
  • the second stage 3 may for instance be connected to the first converter stage 2 to receive as an input signal the quantization noise component in the output of the first converter stage 2, for example in a manner as explained below with reference to FIGs. 4 and 6.
  • the first converter stage 2 may have a transfer function Y 1 (Z) as described by the mathematical formula:
  • Y 1 (Z) Z 1 (Z) - U 1 - X(z) + B 1 - E 1 (Z)] (1 ). while the second stage may have a transfer function Y 2 (z) as described by the mathematical formula:
  • Y 2 (z) f 2 (z) ⁇ [A 2 ⁇ E 1 (Z) + B 2 - ⁇ 2 (z)] (2) in which equations fj(z),f 2 (z) represent functions in the z-domain and ⁇ t (z), ⁇ 2 (z) represent the quantization noise.
  • the first converter stage 2 may have a transfer function Y 1 (Z) as described by the mathematical formula:
  • the first converter stage 2 and the second converter stage 3 may be implemented in any manner suitable for the specific implementation.
  • the first converter stage 2 and the second converter stage 3 may include one or more of: a quantizer 23,33, an integrator (indicated with z "1 in the numerator and 1-z "1 in the denominator of the sections 22,32 in figs. 5 and 7), a combining unit
  • the first converter stage 2 and the second converter stage 3 may for instance be delta modulators, for example pure delta modulators or sigma-delta modulators.
  • the first converter stage and the second converter stage may for example be first or higher order sigma delta modulators.
  • the converter stages may be a CIFB (Cascade of lntegrators in FeedBack form) 2 nd order sigma-delta modulators, including two integrator sections 25,35 (in this example each section being of order 1).
  • the ADC 1 may be a i-j MASH (Multi-stAge noise SHaping) with i and j indicating the number of integrators in the first converter stage and the second converter stage respectively.
  • the converter stages 2,3 may include a quantizer 23,33 which quantizes an inputted signal and outputs a quantized signal.
  • the sigma delta modulators include a quantizer, such as a single bit quantizer or a multibit quantizer (for example 5 bits or less), in a forward loop between a modulator input and a modulator output.
  • the quantizer 23.33 may be a single or multi bit quantizer which outputs a discrete signal Q out with levels li ...l max , based on a comparison of the amplitude of the input signal Qin with one or more threshold values T 1 ... T ma ⁇ .
  • the quantizer 23,33 may for example have a single threshold level and output a binary signal based on the comparison with a single threshold.
  • the quantizer 23,33 may then output a stream of binary ones and zeros at a rate determined by the operating rate of the quantizer 23,33.
  • the operating rate may for example be much higher than the Nyquist rate.
  • the quantizer 23,33 may be connected to the output of the converter stage 2 and output the discrete signal Q out as the converter stage output Y ⁇ Y ⁇ -
  • the converter stages 2,3 may include one or more feedback loops.
  • the output by the quantizer 23,33 may be feedback to the input of the respective converter stage 2,3 and be subtracted from the input.
  • the output of quantizer 23,33 may be connected to an input of a combiner unit 21 ,31.
  • the combiner unit 21 ,31 may be connected with another input to the input of the respective converter stage 2,3 and an output of the combiner unit 21 ,31 may be connected to the quantizer 23,33 or to an intermediate section 22,32 positioned between the combiner unit 21 ,31 and the quantizer 23,33.
  • the quantizer 23 quantizes this difference and hence indirectly compares the change in the input signal with the threshold.
  • the first converter stage 2 and the second converter stage 3 may each include one or more integrators.
  • the integrator is implemented in the intermediate section 22,32, which is connected with an input to the combining unit 21 ,31 and with an output to the quantizer 23,33.
  • the integrator may average the difference between the converter stage output Yi(z) and the stage input X(z) and input the result to the input of the quantizer 23.
  • the converter stages may include multiple sections 25,35 which can integrate.
  • the sections 25,35 may be successive sections which can perform each a first order integration, thus obtaining a higher order integration, for example a second order.
  • the integrator may for example be implemented as an analog filter.
  • the analog filter often called the feedforward loop filter, may be a discrete time integrator with a transfer function H 22,32 (z) as described by the mathematical formula:
  • further sections may be present such as digital filters 51 ,52.
  • the digital filters 51 ,52 cancel the quantization noise of the first stage fed to the second stage.
  • the digital filter 52 may be a delay section and the digital filter 51 may be a differential section as indicated in the figures 5,7.
  • other components may be provided such as amplifier devices 24,26,34,36,38,40,41 which can amplify a signal imputed with an amplification factor a1-a4, b1-b4, c,d1-d2.
  • the amplification factor may for example be smaller, equal or greater than 1.
  • the amplification of the signals inputted into the combining unit 4 may for example be set such that an amplification in the quantizer 23,33 is counteracted and such that the result equals the quantization noise.
  • the values c and d may be set such that the ratio of c/d equals x.
  • the second loop may include a combining unit 4. As shown in figs.
  • the combining unit 4 may be connected with a first input to a node upstream, in a signal processing direction, of the quantizer 23 of the first converter stage for receiving an upstream signal and connected with a second input to a node downstream of the quantizer for receiving an downstream signal, the combining unit being arranged to subtract the upstream signal and the downstream signal from each other, the combining unit being connected with an output to the second converter stage.
  • the quantized output signal Y-T(z) of the first converter stage may be received while at the second input a non-quantized signal may be received (e.g. the signal inputted to the quantizer 23).
  • the signals presented at the first input and the second input may be subtracted from each other, in order to obtain a signal which mainly consists of the quantization noise ⁇ /z) generated in the first converter stage 2.
  • the output of the subtracting unit 4 may be connected to an input of the second converter stage 3, in order to input the obtained signal into the second converter stage 3.
  • the signal processing may include an ADC 1 , for example as shown in FIG. 1 or 3.
  • the signal processing system may include one or more decimator stages, such as a digital filter 8 and/or a down-sampler 9.
  • the decimator stage may be connected to the first loop and the second loop of the ADC 1.
  • the decimator stages 8,9 are connected to the output O of the ADC 1.
  • the decimator stages 8,9 may receive a data stream from the ADC 1.
  • the data stream is derived from digital signals generated in the first loop in the first mode and generated in the first loop and the second loop in the second mode.
  • the digital filter 8 may for example receive from the ADC 1 a series of samples, e.g. a binary data stream.
  • the digital filter 8 may for example perform an operation as described by the mathematical formula:
  • Y F (k) represents the k-th sample outputted by the filter 8 and j represents the number of samples over which the running filtering is determined.
  • the digital filter 8 may output the sample Y F (k) to the down-sampler 9.
  • the digital filter 8 may for example output the samples Y F (k) as n-bit signals, n being for instance between 13 and 24 for audio signals.
  • the number of bits may for example be set depending on the mode of the ADC 1 , for example a lower number of bits when the ADC 1 is in a low power mode and a higher number of bits when the ADC is in a high performance mode.
  • the down-sampler 9 may reduce the rate at which the samples are outputted.
  • the down- sampler 9 may for example output at the downsampler output Y D every n-th sample received from the digital filter 8.
  • the shown apparatus is a mobile communication device 400, in this example a mobile telephone.
  • the mobile communication device 400 may include an ADC 1 which is connected to a microphone 401 of the mobile communication device 400.
  • audio may be inputted.
  • the audio may be voice and the ADC 1 may be in the first mode.
  • the audio may be music and the ADC 1 may be in the second mode.
  • the ADC is connected to a processing unit 11 which may receive the digital signal from the ADC and perform further processing thereof, such as compressing the digital signal into an compressed signal or outputting the signals at an antenna of the device 400.
  • connections may be any type of connection suitable to transfer signals from or to the respective nodes, units or devices, for example via intermediate devices. Accordingly, unless implied or stated otherwise the connections may for example be direct connections or indirect connections.
  • the sections of the stages 2,3 are shown in a certain order, it will be apparent that this order may be changed, since the integrator, the combining unit, the weighing elements and the quantizer are commutative.
  • the integrator 25,35 may be positioned downstream of the quantizer 23,33, for example between the quantizer and the feedback loop.
  • the invention is not limited to physical devices or units implemented in nonprogrammable hardware but can also be applied in programmable devices or units able to perform the desired device functions by operating in accordance with suitable program code.
  • the devices may be physically distributed over a number of apparatuses, while functionally operating as a single device.
  • the converter stages may be implemented using discrete analog components connected to each other to form a converter stage
  • stages or sections functionally being separate may be integrated in a single physical device.
  • the ADC may be implemented on a single die of a semiconductor integrated circuit.
  • other modifications, variations and alternatives are also possible.
  • the specifications and drawings are, accordingly, to be regarded in an illustrative rather than in a restrictive sense.
  • any reference signs placed between parentheses shall not be construed as limiting the claim.
  • the word 'comprising' does not exclude the presence of other elements or steps then those listed in a claim.
  • the words 'a' and 'an' shall not be construed as limited to 'only one', but instead are used to mean 'at least one', and do not exclude a plurality.
  • the mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage.
  • An analog to digital converter (1 ) for converting a selected type of audio signal including: a first loop between an analog input (I), at which at least two types of audio signals can be received, and a digital output (O), said first loop including a first converter stage (2); and a second loop between said analog input and said digital output, including a second converter stage (3), which second converter stage is not included in the first loop; said analog to digital converter having at least two modes including: a narrow band mode in which the second loop is disabled and a wide band mode in which said second loop is enabled; and said analog to digital converter including an ADC controller (10), for controlling said analog to digital converter to be in a selected mode which is selected based on the frequency characteristics required for the analog to digital converter (1 ) to accurately convert said type of audio signal,
  • An analog to digital converter as claimed in claim 1 or 2 wherein the analog to digital converter has an input to receive a clock signal from a processor (100) and a detector (11 ) for detecting a type of clock signal and selecting said selected mode based on said type of clock signal.
  • analog to digital converter as claimed in claim 3, wherein said analog to digital converter includes a frequency detector for determining a frequency of said clock signal and said
  • ADC controller (10) is arranged to select said selected mode based on the determined frequency.
  • each of said first converter stage (2) and said second converter stage (3) includes one or more of: a

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  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

La présente invention concerne un convertisseur analogique/numérique (CAN) qui comprend une première boucle entre une entrée analogique et une entrée numérique. La première boucle comprend un premier étage de conversion. Le CAN comprend une seconde boucle entre l'entrée analogique et la sortie numérique. La seconde boucle comprend un second étage de conversion, lequel second étage de conversion n'est pas inclus dans la première boucle. Le convertisseur analogique/numérique comprend une entrée de commande de boucle pour désactiver, dans un premier mode du convertisseur analogique/numérique, la seconde boucle et activer, dans un second mode du convertisseur analogique/numérique, la seconde boucle.
PCT/IB2008/055336 2007-10-22 2008-10-13 Convertisseur analogique/numérique à modes multiples, système de traitement de signaux et appareil électronique WO2009053949A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017059927A1 (fr) * 2015-10-09 2017-04-13 Tdk Corporation Circuit électronique pour un microphone, et microphone

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0454406A1 (fr) * 1990-04-26 1991-10-30 Hughes Aircraft Company Convertisseur à étages multiples sigma-delta analogique-numérique
EP0954107A2 (fr) * 1998-04-27 1999-11-03 Motorola, Inc. Méthode de modulation et modulteur sigma-delta
WO2001093430A1 (fr) * 2000-05-31 2001-12-06 Spirea Ab Modulateur sigma-delta pourvu d'un recepteur frontal
WO2002037686A2 (fr) * 2000-11-01 2002-05-10 Qualcomm Incorporated Procede et appareil permettant de commander les etages d'un circuit a plusieurs etages
US6538592B1 (en) * 2001-09-24 2003-03-25 Lsi Logic Corporation Variable dynamic range analog-to-digital converter
US20040036640A1 (en) * 2002-08-12 2004-02-26 Rohm Co., Ltd. Variable-order delta sigma modulator and DA converter
WO2006053152A1 (fr) * 2004-11-12 2006-05-18 Analog Devices, Inc. Procede et systeme convertisseur analogique-numerique delta-sigma a double mode
US20060164274A1 (en) * 2005-01-25 2006-07-27 Masato Nakakita Cascade-type variable-order delta-sigma modulator

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0454406A1 (fr) * 1990-04-26 1991-10-30 Hughes Aircraft Company Convertisseur à étages multiples sigma-delta analogique-numérique
EP0954107A2 (fr) * 1998-04-27 1999-11-03 Motorola, Inc. Méthode de modulation et modulteur sigma-delta
WO2001093430A1 (fr) * 2000-05-31 2001-12-06 Spirea Ab Modulateur sigma-delta pourvu d'un recepteur frontal
WO2002037686A2 (fr) * 2000-11-01 2002-05-10 Qualcomm Incorporated Procede et appareil permettant de commander les etages d'un circuit a plusieurs etages
US6538592B1 (en) * 2001-09-24 2003-03-25 Lsi Logic Corporation Variable dynamic range analog-to-digital converter
US20040036640A1 (en) * 2002-08-12 2004-02-26 Rohm Co., Ltd. Variable-order delta sigma modulator and DA converter
WO2006053152A1 (fr) * 2004-11-12 2006-05-18 Analog Devices, Inc. Procede et systeme convertisseur analogique-numerique delta-sigma a double mode
US20060164274A1 (en) * 2005-01-25 2006-07-27 Masato Nakakita Cascade-type variable-order delta-sigma modulator

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ANONYMOUS: "WM8737L: Stereo ADC with Microphone Preamplifier", WOLFSON MICROELECTRONICS DATASHEET., May 2004 (2004-05-01), XP002475365, Retrieved from the Internet <URL:http://www.wolfsonmicro.com/uploads/documents/en/WM8737.pdf> [retrieved on 20080407] *

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017059927A1 (fr) * 2015-10-09 2017-04-13 Tdk Corporation Circuit électronique pour un microphone, et microphone
CN108141222A (zh) * 2015-10-09 2018-06-08 Tdk株式会社 用于麦克风的电子电路和麦克风
EP3360256A1 (fr) * 2015-10-09 2018-08-15 TDK Corporation Circuit électronique pour un microphone, et microphone
JP2018535575A (ja) * 2015-10-09 2018-11-29 Tdk株式会社 マイクロフォン用の電子回路およびマイクロフォン
US20190082258A1 (en) * 2015-10-09 2019-03-14 Tdk Corporation Electronic Circuit for a Microphone and Microphone
US10516942B2 (en) 2015-10-09 2019-12-24 Tdk Corporation Electronic circuit for a microphone and microphone
CN108141222B (zh) * 2015-10-09 2021-08-06 Tdk株式会社 用于麦克风的电子电路和麦克风

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