WO2008128160A1 - Hemts based on si/nitride structures - Google Patents

Abstract

A transistor device includes a substrate. A buffer region is positioned on the substrate. A GaN/ AlGaN layer is positioned on the buffer region.

Description

NEW DEVICES BASED ON SI/NITRIDE STRUCTURES

PRIORITY INFORMATION This application claims priority from provisional application Ser. No. 60/923,094 filed April 12, 2007, which is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

The invention relates to the field of transistor structures, and in particular to a transi stor formed using S i/nitride structures .

State-of-the-art commercial GaN transistors are normally grown on SiC substrates. In spite of the excellent performance of these devices, their commercialization is severely hindered by the high cost of SiC wafers. To reduce cost, GaN transistors have also been grown on Si substrates (normally >10 times cheaper than SiC). However, the performance of these devices is limited by the high electrical conductivity and poor thermal conductivity of the Si substrate.

SUMMARY OF THE INVENTION

According to one aspect of the invention, there is provided a transistor device. The transistor device includes a substrate. A buffer region is positioned on the substrate. A GaN/ AlGaN layer is positioned on the buffer region.

According to another aspect of the invention, there is provided a method of forming a transistor device. The method includes providing a substrate and forming a buffer region on the substrate. Moreover, the method includes forming a GaN/ AlGaN structure on the buffer region. BRIEF DESCRIPTION OF THE DRAWINGS

FIGs. IA- 1C are process flow graphs for the selective removal of a Si substrate below AlGaN/GaN HEMTs;

FIG. 2 is a scanning electron micrograph (SEM) of the selective etch if Si substrate in accordance with the invention;

FIGs. 3A-3F are process flow graphs of the selective removal of the Si wafer and Si-doped GaN material in the buffer of an AlGaN/GaN HEMT;

FIG. 4 is a schematic diagram illustrating a thin-body AlGaN/GaN HEMT formed in accordance with invention; FIG. 5 is a schematic diagram illustrating a double gate GaN HEMT formed in accordance with the invention;

FIGs. 6A-6D are examples of a process flow graph for the implantation of Si from the back side of the wafer to improve the activation yield of Si implanted species; and

FIGs. 7A-7E are examples of a process flow graph for the integration of Si CMOS electronics in GaN-on-Si wafers.

DETAILED DESCRIPTION OF THE INVENTION

The invention involves several new technologies to improve the performance of GaN HEMTs grown on Si substrates. This invention also allows the fabrication of completely new devices as well as the development of hybrid circuits with GaN HEMTs and Si MOSFETs in close proximity. The first technology, which is called GaN-on- nothing technology, will allow the fabrication of GaN transistors grown on Si without the frequency performance limitations traditionally shown on GaN-on-Si devices. This technology is based on the reduction of parasitic substrate capacitances through the full etching of the Si wafer below the GaN transistors. This technology will also help to reduce buffer leakage currents and to improve the transistor reliability. The technology also has important beneficial effects in the implantation yield in nitrides, ohmic contact resistance as well as in the carrier confinement and gate electrostatic control in these devices. All these new characteristics will allow GaN-on-Si devices to reach a performance level at least similar to the one on GaN-on-SiC devices, at a fraction of the total cost and in a much more scalable technology.

The second key technology will allow the fabrication of Si devices in close proximity to GaN HEMTs in a GaN-on-Si wafer. This technology is based on the selective removal of the AlGaN/GaN epilayer and subsequent processing of the exposed Si (111) wafer.

The low cost of Si wafers and its scalability makes the growth of GaN devices on Si very attractive. This interest is even higher when considering the tremendous possibilities of the integration of GaN devices with Si electronics. The use of AlGaN- GaN wafers is grown on Si with great success. However, the performance of HEMTs fabricated on these wafers has been lower than in other substrates due to the high parasitic capacitance introduced by the Si substrate and the high conductivity of the Si- diffused buffer layer. In this invention, the well established Si micromachining technology is used to improve the performance of GaN transistors grown on Si beyond the performance achieved in other substrates. To reduce parasitic capacitances and previously mentioned benefits, one can selectively remove the Si carrier wafer in the region underneath an AlGaN/GaN transistor following the process flow shown in FIG. 1.

The process flow of FIG. IA shows an as grown AlGaN/GaN structure on GaN- on-Si wafer 2, as shown in step 12 of FIG. IB. Photoresists 6 or other masking materials are deposited and defined on the Si substrate δ of wafer 2 as shown in step 14 and a dry etch is used to remove a portion of the Si substrate 8 so as to expose a portion of the bottom layer of the GaN buffer layer 10 of wafer 4, as shown in step 16 of FIG. 1C.

There are different methods to selectively remove the Si substrate 8. One of them was, for example, developed at the Microsystems Technology Laboratories (MTL) of MIT during the fabrication of substrate via holes. In this technology the Si wafer is selectively etched with a Surface Technology Systems time-multiplexed, inductively- coupled plasma reactive ion etching system available in MTL. This system uses a Bosch etch to fabricate via holes in Si wafers with an aspect ratio of 49: 1.

FIG. 2 shows an electron micrograph 18 of some via holes fabricated in Si wafers in MTL. Due to the extremely high chemical stability of nitride semiconductors, the GaN buffer layer will act as a etch stop layer to the Bosch etch (SFβ-based etch). There are many other technologies that can be used to etch Si and they should not reduce the generality of the invention.

The selective removal of the Si material below the AlGaN/GaN transistor is the first step to improve the performance of these devices.

FIGs. 3A-3F shows a process flow graph illustrating the formation of an AlGaN/GaN transistor. An AlGaN/GaN wafer 22 is shown in step 20 of FIG. 3A includes a Si-doped GaN buffer layer 24 grown on a Si substrate 26. Photoresist layers 28, 30 are deposited on the bottom side of the Si substrate 26, as shown in step 32 of FIG. 3B. A portion of the Si substrate 26 is removed using a dry etch exposing the Si-doped GaN buffer layer 24, as shown in step 34 of FIG. 3C. AlGaN/GaN transistors grown on Si have important parasitic capacitances due to both the relative high conductivity of the Si substrate 26 and the diffusion of Si atoms into the GaN buffer layer 24 during the high temperature growth of the GaN epilayer 35. By removing the portions of the Si substrate 26 as described herein, the first component of the parasitic capacitances is eliminated.

To reduce the contribution of the Si-doped GaN buffer layer 24, after removing the portions of the Si substrate 26, a portion of the GaN buffer layer 24 is etched with a Cl₂-based plasma to remove the Si-doped conductive region, as shown in step 36 of FOG. 3D. This approach will significantly reduce the buffer conductivity and improve the high frequency performance of AlGaN/GaN devices grown on Si. It is expected that the removal of the Si substrate 26 and Si-doped buffer 24 will reduce the parasitic buffer capacitance at least by 50 % and the buffer leakage current. The photoresist layers 28, 30 are also removed in step 38 of FIG. 3E. To remove the damage introduced by the Cl₂- based plasma etch, a high temperature annealing may be performed in the structure. In step 40 of FIG. 3F, gate 42, source 44, and drain 46 contacts are formed using lithography and deposition while being aligned with wafer backside 46.

FIG. 4 shows an ultra thing body AlGaN/GaN HEMT structure 51 formed in accordance with the invention as shown in FIG. 3. If the etch of the GaN buffer layer 24 is carefully controlled, it is possible to etch most of the GaN buffer 50 and fabricate ultra thin body AlGaN/GaN HEMT 50 where only 5-100 nm of the GaN buffer layer 50 is left after the etch, as shown in FIG. 4. This device geometry will improve the carrier confinement and the modulation efficiency of the gate, which will significantly increase the high frequency performance of these devices. The proposed device geometry will also be useful to increase the reliability and lifetime of the GaN transistor as it alleviates the internal stress due to the high piezoelectric coefficients and electric fields of these transistors. Thin etch stop layers made of AlGaN, InGaN or InAlGaN layers 52 can be used in the buffer to assure a reproducible etch.

The inventive ultrathin body devices could also benefit from the possibility of depositing metallic contacts in the back side of the wafer, for example on the GaN buffer layer 60. Due to this new technology, devices with a top 62 and bottom gate 64 could be fabricated for the first time in the GaN system, as show in FIG. 5. These devices will significantly improve the electrostatic control of the channel by the gate, enhancing the pinch-off of the devices and increasing the frequency performance.

Another beneficial side-effect of the proposed technology is the increase of the implantation yield. Si implantation is being investigated by several groups to reduce the access resistances in AlGaN/GaN HEMTs, however it has only achieved a limited success due to the poor activation yield of implanted Si in the AlGaN

The etch of the Si carrier wafer underneath the transistor and the etch of some of the GaN buffer layer described herein would significantly reduced the distance between the back of the sample and the channel. This reduced distance would allow the use of implantation from the back side of the wafer. With this configuration, most of the implanted atoms will be in GaN and the activation yield will be much higher than in standard devices. Also, as the implantation occurs from the GaN face, it is expected that very limited Al atoms will mix with the GaN buffer due to implantation scattering. FIGs. 6A-6D shows the process steps of this improved implantation technology. With this new back implantation technology, it would even be possible to fabricate the ohmic contacts on the back side of the wafer, which would allow ultra low ohmic resistances due to the reduction of potential barriers to the electron flow. In particular, FIG. 6 A shows a AlGaN/GaN wafer 72 having portions of the wafer's Si substrate 74, Si- doped GaN buffer layer 76, a GaN layer 78 being etched, as shown step 70. Step 80 of FIG. 6B shows Si implantation being performed in the etched regions. Step 82 of FIG. 6C shows high temperature activation of the regions 86 of Si planted atoms. Step 84 of FIG. 6D shows the formation of a source 88, gate 90, and drain 92 on the regions 86 of Si planted atoms using metal deposition. Note the source and drain can be formed on the backside of the wafer 72 as well.

The invention also protects the use of the Si substrate of the GaN-on-Si wafer to process the Si electronics required by the hybrid GaN-Si circuits. Although the standard orientation of Si wafers used in the microelectronics industry is (100), Si (111) has also been used by industry in the fabrication of high performance Si electronics.

Due to the high growth temperatures required during the growth of GaN HEMTs, the processing of the Si devices has to be done after the growth of the AlGaN/GaN epilayers.

The inventive processing is based on the selective removal of the AlGaN/GaN epilayer in the region where the Si devices are going to be processed. The main steps of this process are depicted in a process illustrate in FIGs. 7A-7E. In particular, FIG. 7A show a AlGaN/GaN wafer 112 having a AlGaN layer 116, a GaN epilayer 118, and a Si substrate 114, as shown in step 110. Photoresist layers 122 are formed on the wafer 112, as show in step 120 of FIG. 7B. Portions of the AlGaN layer 116 and GaN epilayer 118 are etched to expose the top surface of the Si substrate 114 as shown in FIG. 7C. The etching of the AlGaN/GaN epilayer can be done with a dry etching system with a combination of Cl₂ and BCI₃ chemistries. This etching has been proven successful in the etching of thick GaN layers during the process of GaN HEMTs and lasers, as shown in step 126 of FIG. 1C. The photoresist layers 122 are removed as shown in step 128 of FIG. 7D. Step 130 of FIG. 7E shows a Si-based MOSFET structure 132 being formed on the exposed top surface of the Si substrate 1 14.

The invention allows a substantial reduction in the cost of GaN-based transistors which will revolutionize the high frequency electronic market. The tremendous performance, at an affordable price, of these new devices will allow the introduction of a great variety of new applications, from cell phone base stations, to anti-collision radar systems, digital electronics, or the like.

Also, the new devices enabled by the proposed technology, such as double gate and ultra-low access resistance transistors, will allow the use of these devices at much higher frequencies and it may even allow the use of these devices in a future beyond-Si digital electronics.

Although the present invention has been shown and described with respect to several preferred embodiments thereof, various changes, omissions and additions to the form and detail thereof, may be made therein, without departing from the spirit and scope of the invention.

What is claimed is:

Claims

CLAIMS L A transistor device comprising a substrate; a buffer region positioned on said substrate; and a GaN/ AlGaN structure positioned on said buffer region.

2. The transistor device of claim 1 , wherein said GaN/ AlGaN layer comprises a thin AlN layer positioned between the GaN and AlGaN layers.

3. The transistor device of claim 1 , wherein said substrate region is totally or partially etched to reduce the parasitic capacitance of the transistor device.

4. The transistor device of claim 2, wherein said buffer region is partially or totally etched to reduce the conductivity of the buffer region, to reduce parasitic capacitance between the buffer/substrate and the GaN/ AlGaN layer and to increase the reliability and lifetime of the AlGaN/GaN transistor.

5. The transistor device of claim 1 , wherein said buffer region comprises one or multiple AlInGaN layers, which can be doped or undoped, crystalline or amorphous.

6. The transistor device of claim 4, wherein said substrate is locally or uniformly etched using wet chemistry or an inductively-coupled plasma reactive etching system or a reactive ion etching system or chemical-mechanical polishing.

7. The transistor device of claim 5, wherein said buffer region is totally or partially etched using wet chemistry or an inductively-coupled plasma reactive etching system or a reactive ion etching system or chemical-mechanical polishing.

8. The transistor device of claim 7, wherein said buffer region is etched using CVbased plasma.

9. The transistor device of claim 1 , wherein said substrate region is etched to exposed the surface of the GaN/ AlGaN layer.

10. The transistor device of claim 1 , wherein said GaN/AlGaN layer comprises AlGaN or InGaN or InAlGaN etch stop layer.

1 1. The transistor device of claim 8, wherein said GaN/AlGaN exposed layer allows for the use of source, gate, and drain contacts.

12. The transistor device of claim 10, wherein said contacts comprise metal and/or implanted species such as Si.

13. The transistor device of claim 1 , wherein the AlGaN/GaN layers and the buffer regions are etched to expose the surface of said substrate.

14. The transistor device of claim 12, wherein said substrate is planarized to allow a MOSFET structure to be formed.

15. A method of forming a transistor device comprising providing a substrate; forming a buffer region on said substrate; and forming a GaN/AlGaN structure on said buffer region.

16. The method of claim 14, wherein said substrate is locally or uniformly etched to reduce parasitic capacitance associated with said GaN/ AlGaN layer.

17. The method of claim 16, wherein said buffer region is locally or uniformly etched to reduce buffer leakage current and further reduce parasitic capacitance associated with said GaN/AlGaN layer and to increase the reliability and lifetime of the AlGaN/GaN transistor.

18. The method of claim 17, wherein said buffer region comprises Si-doped nitride.

19. The method of claim 16, wherein said substrate is totally or partially etched using wet chemistry or an inductively-coupled plasma reactive etching system or a reactive ion etching system or chemical-mechanical polishing.

20. The method of claim 16, wherein said buffer region is totally or partially etched using wet chemistry or an inductively-coupled plasma reactive etching system or a reactive ion etching system or chemical-mechanical polishing.

21. The method of claim 20, wherein said buffer region is etched using C^-based plasma.

22. The method of claim 15, wherein said GaN/AlGaN layer comprises AlGaN or InGaN or InAlGaN etch stop.

23. The method of claim 15, wherein said GaN/AlGaN layer is etched to expose the surface of said Si substrate.

24. The method of claim 15, wherein said GaN/AlGaN layer allows for the use of source, gate, and drain contacts.

25. The method of claim 24, wherein said contacts comprise metal and/or implanted species such as Si.

26. The transistor device of claim 15, wherein said Si substrate is planarized to allow a MOSFET structure to be formed.