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WO2008126609A1 - 誤り検出制御システム - Google Patents

誤り検出制御システム Download PDF

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Publication number
WO2008126609A1
WO2008126609A1 PCT/JP2008/054570 JP2008054570W WO2008126609A1 WO 2008126609 A1 WO2008126609 A1 WO 2008126609A1 JP 2008054570 W JP2008054570 W JP 2008054570W WO 2008126609 A1 WO2008126609 A1 WO 2008126609A1
Authority
WO
WIPO (PCT)
Prior art keywords
error detection
data
data region
overwrite
nonvolatile memory
Prior art date
Application number
PCT/JP2008/054570
Other languages
English (en)
French (fr)
Inventor
Shigeo Ohyama
Original Assignee
Sharp Kabushiki Kaisha
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Kabushiki Kaisha filed Critical Sharp Kabushiki Kaisha
Priority to CN200880015658.2A priority Critical patent/CN101681310B/zh
Priority to US12/594,311 priority patent/US8176387B2/en
Publication of WO2008126609A1 publication Critical patent/WO2008126609A1/ja

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Storage Device Security (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

　データの信頼性及び耐タンパー性をある程度確保しつつ、誤り検出処理の処理手順及び回路構成を複雑化することなく上書き処理の実行が可能な不揮発性メモリの誤り検出制御システムを提供する。 １アドレス毎に主データ領域と冗長データ領域で構成されたデータ領域を複数アドレス分備える不揮発性メモリ１０と、不揮発性メモリ１０に対し、データ領域群単位での一括消去処理、データ領域単位での読み出し処理、データ領域単位での書き込み処理及びビット単位での上書き処理の制御を行うメモリ制御手段２０と、読み出しデータに対し、対応する冗長データに基づいて誤り検出処理を実行する誤り検出手段３０と、上書き処理の実行対象であるか否かで分類されるデータ種別、または、上書き処理を実行したか否かを示す記憶状態に基づいて、誤り検出処理の実行の可否を制御する誤り検出制御手段５０を備える。
PCT/JP2008/054570 2007-04-04 2008-03-13 誤り検出制御システム WO2008126609A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN200880015658.2A CN101681310B (zh) 2007-04-04 2008-03-13 错误检测控制系统
US12/594,311 US8176387B2 (en) 2007-04-04 2008-03-13 Error detection control system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-098800 2007-04-04
JP2007098800A JP4160625B1 (ja) 2007-04-04 2007-04-04 誤り検出制御システム

Publications (1)

Publication Number Publication Date
WO2008126609A1 true WO2008126609A1 (ja) 2008-10-23

Family

ID=39863739

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/054570 WO2008126609A1 (ja) 2007-04-04 2008-03-13 誤り検出制御システム

Country Status (5)

Country Link
US (1) US8176387B2 (ja)
JP (1) JP4160625B1 (ja)
CN (1) CN101681310B (ja)
TW (1) TW200903247A (ja)
WO (1) WO2008126609A1 (ja)

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JP5668279B2 (ja) 2009-08-06 2015-02-12 ソニー株式会社 不揮発性ランダムアクセスメモリおよび不揮発性メモリシステム
US8683270B2 (en) * 2010-04-29 2014-03-25 Micron Technology, Inc. Signal line to indicate program-fail in memory
US8918683B2 (en) * 2012-09-14 2014-12-23 SK Hynix Inc. One-time program cell array circuit and memory device including the same
JP5954872B2 (ja) * 2012-09-20 2016-07-20 ルネサスエレクトロニクス株式会社 半導体集積回路
US9652376B2 (en) 2013-01-28 2017-05-16 Radian Memory Systems, Inc. Cooperative flash memory control
US10445229B1 (en) 2013-01-28 2019-10-15 Radian Memory Systems, Inc. Memory controller with at least one address segment defined for which data is striped across flash memory dies, with a common address offset being used to obtain physical addresses for the data in each of the dies
US11249652B1 (en) 2013-01-28 2022-02-15 Radian Memory Systems, Inc. Maintenance of nonvolatile memory on host selected namespaces by a common memory controller
JP5794240B2 (ja) * 2013-02-05 2015-10-14 ソニー株式会社 誤り検出訂正装置、誤り検出訂正方法、情報処理装置、および、プログラム
JP2015011609A (ja) * 2013-07-01 2015-01-19 ラピスセミコンダクタ株式会社 情報処理装置、半導体装置及び情報データのベリファイ方法
KR102148389B1 (ko) * 2014-06-11 2020-08-27 삼성전자주식회사 오버 라이트 동작을 갖는 메모리 시스템 및 그에 따른 동작 제어방법
US9542118B1 (en) 2014-09-09 2017-01-10 Radian Memory Systems, Inc. Expositive flash memory control
US10552058B1 (en) 2015-07-17 2020-02-04 Radian Memory Systems, Inc. Techniques for delegating data processing to a cooperative memory controller
JP6757127B2 (ja) * 2015-09-25 2020-09-16 富士通デバイス株式会社 遊技機用記憶装置
JP6717059B2 (ja) * 2016-06-06 2020-07-01 オムロン株式会社 制御システム
CN106528311A (zh) * 2016-09-29 2017-03-22 杭州芯讯科技有限公司 嵌入式系统及其控制方法
US10585610B1 (en) * 2016-09-30 2020-03-10 EMC IP Holding Company LLC Locking data structures with locking structures in flash memory by setting bits in the locking structures
KR20190029316A (ko) * 2017-09-12 2019-03-20 에스케이하이닉스 주식회사 마이크로 컨트롤러, 이를 포함하는 메모리 시스템 및 이의 동작방법
US11175984B1 (en) 2019-12-09 2021-11-16 Radian Memory Systems, Inc. Erasure coding techniques for flash memory
US11556618B2 (en) * 2020-02-18 2023-01-17 At&T Intellectual Property I, L.P. Split ledger software license platform
JP7500365B2 (ja) * 2020-09-14 2024-06-17 キオクシア株式会社 メモリシステム
US11604740B2 (en) * 2020-12-01 2023-03-14 Capital One Services, Llc Obfuscating cryptographic material in memory
JP2023037738A (ja) * 2021-09-06 2023-03-16 セイコーエプソン株式会社 制御システム及び電子機器

Citations (2)

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Publication number Priority date Publication date Assignee Title
JPH01209552A (ja) * 1988-02-17 1989-08-23 Hitachi Maxell Ltd 半導体ファイルメモリ装置
JP2002091831A (ja) * 2000-09-12 2002-03-29 Hitachi Ltd データ処理システム及びデータ処理方法

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US4019033A (en) * 1975-12-29 1977-04-19 Honeywell Information Systems, Inc. Control store checking system and method
JP3542002B2 (ja) * 1996-09-24 2004-07-14 株式会社ルネサステクノロジ システム
JPH10334695A (ja) * 1997-05-27 1998-12-18 Toshiba Corp キャッシュメモリ及び情報処理システム
TW333648B (en) * 1997-10-30 1998-06-11 Key Technology Corp The connection structure and algorithm for flash memory
US6941505B2 (en) 2000-09-12 2005-09-06 Hitachi, Ltd. Data processing system and data processing method
CN1311354C (zh) 2001-04-24 2007-04-18 皇家菲利浦电子有限公司 用于闪速存储器允许可更改位的系统和存储数据的方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01209552A (ja) * 1988-02-17 1989-08-23 Hitachi Maxell Ltd 半導体ファイルメモリ装置
JP2002091831A (ja) * 2000-09-12 2002-03-29 Hitachi Ltd データ処理システム及びデータ処理方法

Also Published As

Publication number Publication date
TW200903247A (en) 2009-01-16
CN101681310B (zh) 2012-07-18
CN101681310A (zh) 2010-03-24
JP4160625B1 (ja) 2008-10-01
US8176387B2 (en) 2012-05-08
JP2008257476A (ja) 2008-10-23
US20100083050A1 (en) 2010-04-01
TWI368134B (ja) 2012-07-11

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