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WO2008126429A1 - クロック・データ再生回路およびその制御方法 - Google Patents

クロック・データ再生回路およびその制御方法 Download PDF

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Publication number
WO2008126429A1
WO2008126429A1 PCT/JP2008/050387 JP2008050387W WO2008126429A1 WO 2008126429 A1 WO2008126429 A1 WO 2008126429A1 JP 2008050387 W JP2008050387 W JP 2008050387W WO 2008126429 A1 WO2008126429 A1 WO 2008126429A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
discrimination
clock
discrimination circuit
main signal
Prior art date
Application number
PCT/JP2008/050387
Other languages
English (en)
French (fr)
Inventor
Hidemi Noguchi
Original Assignee
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Priority to JP2009508929A priority Critical patent/JP4706885B2/ja
Priority to US12/529,439 priority patent/US8238503B2/en
Publication of WO2008126429A1 publication Critical patent/WO2008126429A1/ja

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

　安定したクロック信号を抽出することができないという問題を解決するクロック・データ再生回路を影響する。 　位相比較器は、主信号識別器を有する。主信号識別器は、受信信号をクロック信号で識別し、その識別結果を示す再生データを生成する。位相比較器２は、主信号識別器の識別結果を用いて受信信号および再生クロックの位相を比較し、その比較結果を示す位相比較信号を出力する。生成部は、位相比較器２から出力された位相比較信号が示す比較結果に応じた周波数の再生クロックを生成する。アイ開口モニタ部は、受信信号から分岐されたモニタ信号と、主信号識別器が生成した再生データとに基づいて、主信号識別器１の最適な識別点を検出する。また、アイ開口モニタ部は、その検出結果に基づいて主信号識別器の識別点を調整する。
PCT/JP2008/050387 2007-03-30 2008-01-16 クロック・データ再生回路およびその制御方法 WO2008126429A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009508929A JP4706885B2 (ja) 2007-03-30 2008-01-16 クロック・データ再生回路およびその制御方法
US12/529,439 US8238503B2 (en) 2007-03-30 2008-01-16 Clock data recovering circuit and control method of the clock data recovering circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-090445 2007-03-30
JP2007090445 2007-03-30

Publications (1)

Publication Number Publication Date
WO2008126429A1 true WO2008126429A1 (ja) 2008-10-23

Family

ID=39863588

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/050387 WO2008126429A1 (ja) 2007-03-30 2008-01-16 クロック・データ再生回路およびその制御方法

Country Status (3)

Country Link
US (1) US8238503B2 (ja)
JP (1) JP4706885B2 (ja)
WO (1) WO2008126429A1 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014116880A (ja) * 2012-12-12 2014-06-26 Fujitsu Ltd 受信回路
US9184904B2 (en) 2013-11-21 2015-11-10 Fujitsu Limited Communication system, receiver, and eye-opening measuring method
TWI804187B (zh) * 2021-09-29 2023-06-01 智原科技股份有限公司 眼開監測裝置與其操作方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8761325B2 (en) * 2010-06-28 2014-06-24 Ben WILLCOCKS Digital receivers
US9591374B2 (en) * 2010-06-30 2017-03-07 Warner Bros. Entertainment Inc. Method and apparatus for generating encoded content using dynamically optimized conversion for 3D movies
US8134393B1 (en) 2010-09-29 2012-03-13 Motorola Solutions, Inc. Method and apparatus for correcting phase offset errors in a communication device
US8917803B1 (en) 2011-05-03 2014-12-23 Xilinx, Inc. Circuits and methods for characterizing a receiver of a communication signal
US8995514B1 (en) * 2012-09-28 2015-03-31 Xilinx, Inc. Methods of and circuits for analyzing a phase of a clock signal for receiving data
JP6032080B2 (ja) * 2013-03-22 2016-11-24 富士通株式会社 受信回路及び受信回路の制御方法
KR102707221B1 (ko) * 2024-04-30 2024-09-20 주식회사 램쉽 피드백 루프를 갖는 아이 오프닝 모니터 회로 및 아이 오프닝 모니터링 방법

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02137550A (ja) * 1988-11-18 1990-05-25 Fujitsu Ltd 受信系最適化方式
JPH1168674A (ja) * 1997-08-12 1999-03-09 Toshiba Corp 光受信器
JP2003018140A (ja) * 2001-07-05 2003-01-17 Fujitsu Ltd 伝送装置
JP2003318872A (ja) * 2002-04-19 2003-11-07 Nef:Kk リタイミング回路

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Publication number Priority date Publication date Assignee Title
US4218771A (en) * 1978-12-04 1980-08-19 Rockwell International Corporation Automatic clock positioning circuit for a digital data transmission system
US4535459A (en) * 1983-05-26 1985-08-13 Rockwell International Corporation Signal detection apparatus
US4538283A (en) * 1983-07-26 1985-08-27 Rockwell International Corporation Adaptive equalizer suitable for use with fiber optics
US4821297A (en) * 1987-11-19 1989-04-11 American Telephone And Telegraph Company, At&T Bell Laboratories Digital phase locked loop clock recovery scheme
JP2817785B2 (ja) 1996-06-20 1998-10-30 日本電気株式会社 自動識別点制御識別器およびその制御方法
US5896391A (en) * 1996-12-19 1999-04-20 Northern Telecom Limited Forward error correction assisted receiver optimization
JP3039526B2 (ja) 1998-07-22 2000-05-08 日本電気株式会社 Ｐｌｌ回路
JP3856101B2 (ja) 2001-09-03 2006-12-13 日本電気株式会社 受信波形整形機能を有する光受信装置
JP3839830B2 (ja) 2002-12-05 2006-11-01 富士通株式会社 ディジタル信号受信装置、該ディジタル信号受信装置を有する光伝送装置及び識別点制御方法
JP3995094B2 (ja) 2003-10-08 2007-10-24 日本電信電話株式会社 アイ開口モニタ

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02137550A (ja) * 1988-11-18 1990-05-25 Fujitsu Ltd 受信系最適化方式
JPH1168674A (ja) * 1997-08-12 1999-03-09 Toshiba Corp 光受信器
JP2003018140A (ja) * 2001-07-05 2003-01-17 Fujitsu Ltd 伝送装置
JP2003318872A (ja) * 2002-04-19 2003-11-07 Nef:Kk リタイミング回路

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014116880A (ja) * 2012-12-12 2014-06-26 Fujitsu Ltd 受信回路
US9184904B2 (en) 2013-11-21 2015-11-10 Fujitsu Limited Communication system, receiver, and eye-opening measuring method
TWI804187B (zh) * 2021-09-29 2023-06-01 智原科技股份有限公司 眼開監測裝置與其操作方法

Also Published As

Publication number Publication date
US20100023826A1 (en) 2010-01-28
JP4706885B2 (ja) 2011-06-22
US8238503B2 (en) 2012-08-07
JPWO2008126429A1 (ja) 2010-07-22

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