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WO2008123399A1 - 三次元構造半導体装置 - Google Patents

三次元構造半導体装置 Download PDF

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Publication number
WO2008123399A1
WO2008123399A1 PCT/JP2008/056018 JP2008056018W WO2008123399A1 WO 2008123399 A1 WO2008123399 A1 WO 2008123399A1 JP 2008056018 W JP2008056018 W JP 2008056018W WO 2008123399 A1 WO2008123399 A1 WO 2008123399A1
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
semiconductor device
dimensional structure
conductor layer
layer
Prior art date
Application number
PCT/JP2008/056018
Other languages
English (en)
French (fr)
Inventor
Tadahiro Ohmi
Masahiro Konda
Original Assignee
National University Corporation Tohoku University
Foundation For Advancement Of International Science
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National University Corporation Tohoku University, Foundation For Advancement Of International Science filed Critical National University Corporation Tohoku University
Priority to US12/450,441 priority Critical patent/US20100044846A1/en
Publication of WO2008123399A1 publication Critical patent/WO2008123399A1/ja

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H10D88/01—Manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

　チップ面積の増大を防ぎ、チップの動作周波数を高くすることが可能な三次元構造の半導体装置を提供する。三次元構造半導体装置は、第１の半導体層に形成された複数の領域と該第１の半導体層の上に形成された第１の配線層とを含んで構成された第１の集積回路と、前記第１の配線層に積層された第１の絶縁層と、前記第１の絶縁層に積層された第２の半導体層に形成された複数の領域と該第２の半導体層の上に形成された第２の配線層とを含んで構成された第２の集積回路とを含む。前記第１の集積回路及び前記第２の集積回路は積層方向に貫通した配線により電気的に接続され、前記第１の集積回路及び前記第２の集積回路間のデータ双方向通信、制御信号供給、およびクロック信号供給の少なくとも一つが前記貫通した配線を介して行われる。
PCT/JP2008/056018 2007-03-29 2008-03-28 三次元構造半導体装置 WO2008123399A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/450,441 US20100044846A1 (en) 2007-03-29 2008-03-28 Three-dimensional structural semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-088444 2007-03-29
JP2007088444A JP2008251666A (ja) 2007-03-29 2007-03-29 三次元構造半導体装置

Publications (1)

Publication Number Publication Date
WO2008123399A1 true WO2008123399A1 (ja) 2008-10-16

Family

ID=39830884

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/056018 WO2008123399A1 (ja) 2007-03-29 2008-03-28 三次元構造半導体装置

Country Status (3)

Country Link
US (1) US20100044846A1 (ja)
JP (1) JP2008251666A (ja)
WO (1) WO2008123399A1 (ja)

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KR100907896B1 (ko) * 2007-06-22 2009-07-14 주식회사 동부하이텍 시스템 인 패키지의 금속 전극 형성방법
JP2009295740A (ja) * 2008-06-04 2009-12-17 Elpida Memory Inc メモリチップ及び半導体装置
US8330489B2 (en) * 2009-04-28 2012-12-11 International Business Machines Corporation Universal inter-layer interconnect for multi-layer semiconductor stacks
US8796863B2 (en) 2010-02-09 2014-08-05 Samsung Electronics Co., Ltd. Semiconductor memory devices and semiconductor packages
US8677613B2 (en) * 2010-05-20 2014-03-25 International Business Machines Corporation Enhanced modularity in heterogeneous 3D stacks
US9048112B2 (en) * 2010-06-29 2015-06-02 Qualcomm Incorporated Integrated voltage regulator with embedded passive device(s) for a stacked IC
TW201203496A (en) * 2010-07-01 2012-01-16 Nat Univ Tsing Hua 3D-IC device and decreasing type layer-ID detector for 3D-IC device
US8519735B2 (en) 2011-08-25 2013-08-27 International Business Machines Corporation Programming the behavior of individual chips or strata in a 3D stack of integrated circuits
US8476771B2 (en) 2011-08-25 2013-07-02 International Business Machines Corporation Configuration of connections in a 3D stack of integrated circuits
US8516426B2 (en) 2011-08-25 2013-08-20 International Business Machines Corporation Vertical power budgeting and shifting for three-dimensional integration
US8525569B2 (en) 2011-08-25 2013-09-03 International Business Machines Corporation Synchronizing global clocks in 3D stacks of integrated circuits by shorting the clock network
US8587357B2 (en) 2011-08-25 2013-11-19 International Business Machines Corporation AC supply noise reduction in a 3D stack with voltage sensing and clock shifting
US8576000B2 (en) 2011-08-25 2013-11-05 International Business Machines Corporation 3D chip stack skew reduction with resonant clock and inductive coupling
US8476953B2 (en) 2011-08-25 2013-07-02 International Business Machines Corporation 3D integrated circuit stack-wide synchronization circuit
US8381156B1 (en) 2011-08-25 2013-02-19 International Business Machines Corporation 3D inter-stratum connectivity robustness
US9330433B2 (en) * 2014-06-30 2016-05-03 Intel Corporation Data distribution fabric in scalable GPUs
JP6871512B2 (ja) 2017-04-11 2021-05-12 富士通株式会社 半導体装置及びその製造方法
JP2018182213A (ja) 2017-04-19 2018-11-15 富士通株式会社 半導体装置及び半導体装置の製造方法
KR102587973B1 (ko) * 2017-11-07 2023-10-12 삼성전자주식회사 3차원 반도체 메모리 장치
CN112466350B (zh) 2019-06-28 2023-05-12 长江存储科技有限责任公司 一种三维3d存储器件以及用于操作三维3d存储器件上的数据处理单元的系统及方法
WO2020258209A1 (en) * 2019-06-28 2020-12-30 Yangtze Memory Technologies Co., Ltd. Computation-in-memory in three-dimensional memory device
US20230176818A1 (en) * 2020-05-22 2023-06-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

Citations (4)

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Publication number Priority date Publication date Assignee Title
JP2006013337A (ja) * 2004-06-29 2006-01-12 Nec Corp ３次元半導体装置
JP2006012358A (ja) * 2004-06-29 2006-01-12 Nec Corp 積層型半導体メモリ装置
JP2006019328A (ja) * 2004-06-30 2006-01-19 Nec Corp 積層型半導体装置
JP2006253699A (ja) * 1998-06-02 2006-09-21 Thin Film Electronics Asa データ記憶・演算装置、及びその製造方法

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JPS58139449A (ja) * 1982-02-15 1983-08-18 Fujitsu Ltd 垂直信号線を有する多層集積回路
US5202754A (en) * 1991-09-13 1993-04-13 International Business Machines Corporation Three-dimensional multichip packages and methods of fabrication
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JPH0992781A (ja) * 1995-09-22 1997-04-04 Internatl Business Mach Corp <Ibm> 統合した回路を有するマルチチップ半導体構造およびその製造方法
US6831370B2 (en) * 2001-07-19 2004-12-14 Micron Technology, Inc. Method of using foamed insulators in three dimensional multichip structures
JP4419049B2 (ja) * 2003-04-21 2010-02-24 エルピーダメモリ株式会社 メモリモジュール及びメモリシステム
JP2006319058A (ja) * 2005-05-11 2006-11-24 Elpida Memory Inc 半導体装置の製造方法
KR100796642B1 (ko) * 2006-01-27 2008-01-22 삼성전자주식회사 고집적 반도체 장치 및 그 제조 방법
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Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006253699A (ja) * 1998-06-02 2006-09-21 Thin Film Electronics Asa データ記憶・演算装置、及びその製造方法
JP2006013337A (ja) * 2004-06-29 2006-01-12 Nec Corp ３次元半導体装置
JP2006012358A (ja) * 2004-06-29 2006-01-12 Nec Corp 積層型半導体メモリ装置
JP2006019328A (ja) * 2004-06-30 2006-01-19 Nec Corp 積層型半導体装置

Also Published As

Publication number Publication date
JP2008251666A (ja) 2008-10-16
US20100044846A1 (en) 2010-02-25

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