+

WO2008146441A1 - Ｓｏｉウエーハの製造方法 - Google Patents

Ｓｏｉウエーハの製造方法 Download PDF

Info

Publication number
WO2008146441A1
WO2008146441A1 PCT/JP2008/000995 JP2008000995W WO2008146441A1 WO 2008146441 A1 WO2008146441 A1 WO 2008146441A1 JP 2008000995 W JP2008000995 W JP 2008000995W WO 2008146441 A1 WO2008146441 A1 WO 2008146441A1
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
base wafer
base
forming
soi
Prior art date
Application number
PCT/JP2008/000995
Other languages
English (en)
French (fr)
Inventor
Isao Yokokawa
Hiroshi Takeno
Nobuhiko Noto
Original Assignee
Shin-Etsu Handotai Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin-Etsu Handotai Co., Ltd. filed Critical Shin-Etsu Handotai Co., Ltd.
Priority to KR1020097023929A priority Critical patent/KR101500956B1/ko
Priority to CN2008800169169A priority patent/CN101681805B/zh
Priority to EP08738597A priority patent/EP2149898B1/en
Priority to US12/450,960 priority patent/US7985660B2/en
Publication of WO2008146441A1 publication Critical patent/WO2008146441A1/ja

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

　本発明は、ｐ＋シリコン単結晶ウエーハからなるベースウエーハと、これよりも低濃度のドーパントを含有するシリコン単結晶ウエーハからなるボンドウエーハとを準備する工程と、ベースウエーハの全面にシリコン酸化膜を熱酸化によって形成する工程と、ボンドウエーハとベースウエーハとをシリコン酸化膜を介して貼り合わせる工程と、ボンドウエーハを薄膜化してＳＯＩ層を形成する工程とを含み、ベースウエーハの熱酸化工程より前に、ベースウエーハの貼り合わせ面とは反対側の面にＣＶＤ絶縁膜を形成する工程を有することを特徴とするＳＯＩウエーハの製造方法である。これにより、高温熱処理によって、ベースウエーハに含まれていたｐ型ドーパントが、ベースウエーハの貼り合わせ面とは反対側の面から外方拡散することを簡便に防止でき、ＳＯＩ層中への混入を抑制し、かつ、反りを低減することができるＳＯＩウエーハの製造方法が提供される。
PCT/JP2008/000995 2007-05-22 2008-04-16 Ｓｏｉウエーハの製造方法 WO2008146441A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020097023929A KR101500956B1 (ko) 2007-05-22 2008-04-16 Ｓｏｉ웨이퍼의 제조 방법
CN2008800169169A CN101681805B (zh) 2007-05-22 2008-04-16 Soi芯片的制造方法
EP08738597A EP2149898B1 (en) 2007-05-22 2008-04-16 Method for manufacturing soi wafer
US12/450,960 US7985660B2 (en) 2007-05-22 2008-04-16 Method for manufacturing soi wafer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-135298 2007-05-22
JP2007135298A JP5272329B2 (ja) 2007-05-22 2007-05-22 Ｓｏｉウエーハの製造方法

Publications (1)

Publication Number Publication Date
WO2008146441A1 true WO2008146441A1 (ja) 2008-12-04

Family

ID=40074719

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/000995 WO2008146441A1 (ja) 2007-05-22 2008-04-16 Ｓｏｉウエーハの製造方法

Country Status (6)

Country Link
US (1) US7985660B2 (ja)
EP (1) EP2149898B1 (ja)
JP (1) JP5272329B2 (ja)
KR (1) KR101500956B1 (ja)
CN (1) CN101681805B (ja)
WO (1) WO2008146441A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022054429A1 (ja) * 2020-09-11 2022-03-17 信越半導体株式会社 Ｓｏｉウェーハの製造方法及びｓｏｉウェーハ
JP2022067962A (ja) * 2020-10-21 2022-05-09 信越半導体株式会社 Ｓｏｉウェーハの製造方法及びｓｏｉウェーハ

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010027959A (ja) * 2008-07-23 2010-02-04 Sumco Corp 高抵抗ｓｉｍｏｘウェーハの製造方法
JP5532680B2 (ja) * 2009-05-27 2014-06-25 信越半導体株式会社 Ｓｏｉウェーハの製造方法およびｓｏｉウェーハ
EP2282332B1 (en) * 2009-08-04 2012-06-27 S.O.I. TEC Silicon Method for fabricating a semiconductor substrate
JP2011253906A (ja) * 2010-06-01 2011-12-15 Shin Etsu Handotai Co Ltd 貼り合わせウェーハの製造方法
KR20120020526A (ko) * 2010-08-30 2012-03-08 삼성전자주식회사 도전막 매립형 기판, 그 형성 방법, 및 이를 이용하는 반도체 소자의 제조 방법
JP5644670B2 (ja) * 2011-05-19 2014-12-24 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
JP5927894B2 (ja) * 2011-12-15 2016-06-01 信越半導体株式会社 Ｓｏｉウェーハの製造方法
JP5862521B2 (ja) * 2012-09-03 2016-02-16 信越半導体株式会社 Ｓｏｉウェーハの製造方法
JP6186984B2 (ja) * 2013-07-25 2017-08-30 三菱電機株式会社 半導体装置の製造方法
KR101602279B1 (ko) 2014-12-12 2016-03-10 연세대학교 산학협력단 롤러베어링을 포함하는 웨이퍼 및 그 제조방법
JP6743963B2 (ja) * 2017-03-02 2020-08-19 信越化学工業株式会社 炭化珪素基板の製造方法及び炭化珪素基板
US11585010B2 (en) 2019-06-28 2023-02-21 Globalwafers Co., Ltd. Methods for producing a single crystal silicon ingot using boric acid as a dopant and ingot puller apparatus that use a solid-phase dopant
CN110729195A (zh) * 2019-10-28 2020-01-24 沈阳硅基科技有限公司 平面晶体管的制造方法
US11866844B2 (en) 2020-12-31 2024-01-09 Globalwafers Co., Ltd. Methods for producing a single crystal silicon ingot using a vaporized dopant
US11795569B2 (en) 2020-12-31 2023-10-24 Globalwafers Co., Ltd. Systems for producing a single crystal silicon ingot using a vaporized dopant

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5244169A (en) * 1975-10-06 1977-04-06 Hitachi Ltd Process for production of semiconductor device
JPH05226620A (ja) 1992-02-18 1993-09-03 Fujitsu Ltd 半導体基板及びその製造方法
JPH0837286A (ja) 1994-07-21 1996-02-06 Toshiba Microelectron Corp 半導体基板および半導体基板の製造方法
JPH09266214A (ja) * 1996-03-28 1997-10-07 Shin Etsu Handotai Co Ltd シリコンウェーハの製造方法及びシリコンウェーハ
JPH09266175A (ja) * 1996-03-28 1997-10-07 Shin Etsu Handotai Co Ltd 半導体ウェーハの製造方法及び半導体ウェーハ
JP2001044085A (ja) * 1999-07-30 2001-02-16 Mitsubishi Materials Silicon Corp 張り合わせ基板およびその製造方法
WO2005027217A1 (ja) * 2003-09-08 2005-03-24 Sumco Corporation Ｓｏｉウェーハおよびその製造方法
JP2006270039A (ja) * 2005-02-28 2006-10-05 Shin Etsu Handotai Co Ltd 貼り合わせウエーハの製造方法及び貼り合わせウエーハ

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6008110A (en) * 1994-07-21 1999-12-28 Kabushiki Kaisha Toshiba Semiconductor substrate and method of manufacturing same
EP0798765A3 (en) * 1996-03-28 1998-08-05 Shin-Etsu Handotai Company Limited Method of manufacturing a semiconductor wafer comprising a dopant evaporation preventive film on one main surface and an epitaxial layer on the other main surface
JP3358550B2 (ja) * 1998-07-07 2002-12-24 信越半導体株式会社 Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ
JP2001144275A (ja) * 1999-08-27 2001-05-25 Shin Etsu Handotai Co Ltd 貼り合わせｓｏｉウエーハの製造方法および貼り合わせｓｏｉウエーハ
JP4682508B2 (ja) * 2003-11-14 2011-05-11 信越半導体株式会社 シリコンエピタキシャルウェーハの製造方法
EP1855309A4 (en) * 2005-02-28 2010-11-17 Shinetsu Handotai Kk METHOD FOR MANUFACTURING STICKED GALETTE AND STICKED GALETTE

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5244169A (en) * 1975-10-06 1977-04-06 Hitachi Ltd Process for production of semiconductor device
JPH05226620A (ja) 1992-02-18 1993-09-03 Fujitsu Ltd 半導体基板及びその製造方法
JPH0837286A (ja) 1994-07-21 1996-02-06 Toshiba Microelectron Corp 半導体基板および半導体基板の製造方法
JPH09266214A (ja) * 1996-03-28 1997-10-07 Shin Etsu Handotai Co Ltd シリコンウェーハの製造方法及びシリコンウェーハ
JPH09266175A (ja) * 1996-03-28 1997-10-07 Shin Etsu Handotai Co Ltd 半導体ウェーハの製造方法及び半導体ウェーハ
JP2001044085A (ja) * 1999-07-30 2001-02-16 Mitsubishi Materials Silicon Corp 張り合わせ基板およびその製造方法
WO2005027217A1 (ja) * 2003-09-08 2005-03-24 Sumco Corporation Ｓｏｉウェーハおよびその製造方法
JP2006270039A (ja) * 2005-02-28 2006-10-05 Shin Etsu Handotai Co Ltd 貼り合わせウエーハの製造方法及び貼り合わせウエーハ

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2149898A4

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022054429A1 (ja) * 2020-09-11 2022-03-17 信越半導体株式会社 Ｓｏｉウェーハの製造方法及びｓｏｉウェーハ
JP2022046971A (ja) * 2020-09-11 2022-03-24 信越半導体株式会社 Ｓｏｉウェーハの製造方法及びｓｏｉウェーハ
JP7334698B2 (ja) 2020-09-11 2023-08-29 信越半導体株式会社 Ｓｏｉウェーハの製造方法及びｓｏｉウェーハ
JP2022067962A (ja) * 2020-10-21 2022-05-09 信越半導体株式会社 Ｓｏｉウェーハの製造方法及びｓｏｉウェーハ
JP7380517B2 (ja) 2020-10-21 2023-11-15 信越半導体株式会社 Ｓｏｉウェーハの製造方法及びｓｏｉウェーハ

Also Published As

Publication number Publication date
US20100112781A1 (en) 2010-05-06
JP5272329B2 (ja) 2013-08-28
EP2149898A4 (en) 2011-01-19
JP2008294045A (ja) 2008-12-04
EP2149898A1 (en) 2010-02-03
KR20100017106A (ko) 2010-02-16
CN101681805A (zh) 2010-03-24
CN101681805B (zh) 2011-05-25
US7985660B2 (en) 2011-07-26
KR101500956B1 (ko) 2015-03-11
EP2149898B1 (en) 2012-12-26

Similar Documents

Publication Publication Date Title
WO2008146441A1 (ja) Ｓｏｉウエーハの製造方法
WO2009006183A3 (en) Diffusion control in heavily doped substrates
WO2008105136A1 (ja) シリコン単結晶ウエーハの製造方法
WO2009037955A1 (ja) 太陽電池の製造方法
WO2008117509A1 (ja) Ｓｏｉウエーハの製造方法
JP2009135465A5 (ja)
EP2105957A3 (en) Method for manufacturing soi substrate and method for manufacturing semiconductor device
DE602005001401D1 (de) Struktur und verfahren für die herstellung eines cmos-kompatiblen hochgeschwindigkeits-ge-on-isolator-photodetektors
GB2497259B (en) Butted SOI junction isolation structures and devices and method of fabrication
WO2009075244A1 (ja) 太陽電池の製造方法
TW200701460A (en) Semiconductor device and production method thereof
EP2626914A3 (en) Solar Cell and Method of Manufacturing the Same
TW200633022A (en) Method of manufacturing an epitaxial semiconductor substrate and method of manufacturing a semiconductor device
TW201130018A (en) Semiconductor device and method of manufacturing the same
TW200943477A (en) Method for manufacturing SOI substrate
SG166738A1 (en) Method for manufacturing soi substrate and soi substrate
WO2008081724A1 (ja) 絶縁膜の形成方法および半導体装置の製造方法
EP2579296A4 (en) MANUFACTURING PROCESS FOR JOINT WAFERS
JP2009260312A5 (ja)
WO2008155876A1 (ja) Ｓｏｉウェーハの製造方法
JP2009044142A5 (ja)
TW200616141A (en) Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer
EP2053645A3 (en) Method for manufacturing semiconductor substrate
EP2096673A3 (en) Display device and manufacturing method thereof
JP2009272453A5 (ja)

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200880016916.9

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08738597

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 12450960

Country of ref document: US

WWE Wipo information: entry into national phase

Ref document number: 2008738597

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 20097023929

Country of ref document: KR

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载