+

WO2008038235A3 - Method to manage the load of peripheral elements within a multicore system - Google Patents

Method to manage the load of peripheral elements within a multicore system Download PDF

Info

Publication number
WO2008038235A3
WO2008038235A3 PCT/IB2007/053909 IB2007053909W WO2008038235A3 WO 2008038235 A3 WO2008038235 A3 WO 2008038235A3 IB 2007053909 W IB2007053909 W IB 2007053909W WO 2008038235 A3 WO2008038235 A3 WO 2008038235A3
Authority
WO
WIPO (PCT)
Prior art keywords
multicore
network
chip
peripheral
peripheral elements
Prior art date
Application number
PCT/IB2007/053909
Other languages
French (fr)
Other versions
WO2008038235A2 (en
Inventor
Federico Angiolini
Alonso David Attenza
Micheli Giovanni De
Original Assignee
Ecole Polytech
Federico Angiolini
Alonso David Attenza
Micheli Giovanni De
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ecole Polytech, Federico Angiolini, Alonso David Attenza, Micheli Giovanni De filed Critical Ecole Polytech
Publication of WO2008038235A2 publication Critical patent/WO2008038235A2/en
Publication of WO2008038235A3 publication Critical patent/WO2008038235A3/en
Priority to US12/412,742 priority Critical patent/US7995599B2/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5083—Techniques for rebalancing the load in a distributed system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7825—Globally asynchronous, locally synchronous, e.g. network on chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Small-Scale Networks (AREA)

Abstract

The aim of the present invention is to propose a method to provide reliability, power management and load balancing support for multicore systems based on Networks- on-Chip (NoCs) as well as a way to efficiently implement architectural support for this method by introducing complex packet handling mechanisms achieved by modifying the basic network interfaces attached to the cores of multicore computation systems. The present invention provides also a solution in interrupt-based support in NoCs for multicore computation systems against transient failures or other system-level issues while the system is executing a certain application. It also proposes policies to leverage the proposed hardware extensions. This aim is achieved thanks to a method to manage the load of peripheral elements within a multicore system, said multicore system comprising several processing cores accessing peripheral elements through a Network on Chip (NoC), each processing unit and peripheral element attached to a Network Interface in charge of formatting and driving the packets sent to or received from the Network on Chip, wherein, while considering at least two peripheral elements having a similar function, the Network Interface dedicated to a first peripheral element reroutes the incoming packets to a second Network Interface dedicated to a second peripheral element.
PCT/IB2007/053909 2006-09-27 2007-09-26 Method to manage the load of peripheral elements within a multicore system WO2008038235A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/412,742 US7995599B2 (en) 2006-09-27 2009-03-27 Method to manage the load of peripheral elements within a multicore system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US84736806P 2006-09-27 2006-09-27
US60/847,368 2006-09-27

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/412,742 Continuation-In-Part US7995599B2 (en) 2006-09-27 2009-03-27 Method to manage the load of peripheral elements within a multicore system

Publications (2)

Publication Number Publication Date
WO2008038235A2 WO2008038235A2 (en) 2008-04-03
WO2008038235A3 true WO2008038235A3 (en) 2008-06-12

Family

ID=39027126

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2007/053909 WO2008038235A2 (en) 2006-09-27 2007-09-26 Method to manage the load of peripheral elements within a multicore system

Country Status (2)

Country Link
US (1) US7995599B2 (en)
WO (1) WO2008038235A2 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008038235A2 (en) 2006-09-27 2008-04-03 Ecole Polytechnique Federale De Lausanne (Epfl) Method to manage the load of peripheral elements within a multicore system
EP2080128A1 (en) * 2006-10-10 2009-07-22 Ecole Polytechnique Federale De Lausanne (Epfl) Method to design network-on-chip (noc)-based communication systems
US8601310B2 (en) * 2010-08-26 2013-12-03 Cisco Technology, Inc. Partial memory mirroring and error containment
JP2012146201A (en) * 2011-01-13 2012-08-02 Toshiba Corp On-chip router and multi-core system using the same
BR112014006948A2 (en) 2011-07-25 2017-06-13 Servergy Inc low power general purpose computer server system
GB2493194A (en) * 2011-07-28 2013-01-30 St Microelectronics Res & Dev Alerting transaction initiators in an electronic circuit in the event of a power failure or circuit error
US9756009B2 (en) * 2011-11-07 2017-09-05 Telefonaktiebolaget Lm Ericsson (Publ) Message forwarding among disparate communication networks
CN102638311B (en) * 2012-04-23 2015-04-08 西安电子科技大学 Optical network-on-chip system based on wavelength allocation and communication method of system
CN102831037B (en) * 2012-07-17 2015-01-07 高旭东 Data path fragmentation redundancy protection structure
US9424228B2 (en) * 2012-11-01 2016-08-23 Ezchip Technologies Ltd. High performance, scalable multi chip interconnect
US10469337B2 (en) 2017-02-01 2019-11-05 Netspeed Systems, Inc. Cost management against requirements for the generation of a NoC
CN107395524B (en) * 2017-06-09 2020-12-22 北京中科睿芯科技有限公司 Network failure task discrimination and resource redistribution method and system on many-core chip

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7036042B1 (en) * 2002-08-16 2006-04-25 3Pardata Discovery and isolation of misbehaving devices in a data storage system

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7013354B1 (en) * 1998-10-05 2006-03-14 Canon Kabushiki Kaisha Channel protocol for IEEE 1394 data transmission
WO2005099187A1 (en) * 2004-04-05 2005-10-20 Koninklijke Philips Electronics N.V. Integrated circuit and method for time slot allocation
CN101133597A (en) * 2005-03-04 2008-02-27 皇家飞利浦电子股份有限公司 Electronic device and a method for arbitrating shared resources
WO2006106475A1 (en) * 2005-04-06 2006-10-12 Koninklijke Philips Electronics N. V. Network-on-chip environment and method for reduction of latency
US20080205432A1 (en) * 2005-04-07 2008-08-28 Koninklijke Philips Electronics, N.V. Network-On-Chip Environment and Method For Reduction of Latency
US20090122703A1 (en) * 2005-04-13 2009-05-14 Koninklijke Philips Electronics, N.V. Electronic Device and Method for Flow Control
KR100675850B1 (en) * 2005-10-12 2007-02-02 삼성전자주식회사 NC system with ABI protocol
KR100687659B1 (en) * 2005-12-22 2007-02-27 삼성전자주식회사 A network interface for controlling lock operation according to the AI protocol, a packet data communication on-chip interconnect system including the network interface, and a method of operating the network interface.
KR100737943B1 (en) * 2006-09-13 2007-07-13 삼성전자주식회사 Network-on-chip response signal control device and method
WO2008038235A2 (en) 2006-09-27 2008-04-03 Ecole Polytechnique Federale De Lausanne (Epfl) Method to manage the load of peripheral elements within a multicore system
EP1995660B1 (en) * 2007-05-24 2013-07-10 STMicroelectronics Srl Method and system for full-duplex mesochronous communications and corresponding computer program product
EP2009554A1 (en) * 2007-06-25 2008-12-31 Stmicroelectronics SA Method for transferring data from a source target to a destination target, and corresponding network interface
EP2061191A1 (en) * 2007-11-13 2009-05-20 STMicroelectronics (Grenoble) SAS Buffering architecture for packet injection and extraction in on-chip networks.
US8131944B2 (en) * 2008-05-30 2012-03-06 Intel Corporation Using criticality information to route cache coherency communications

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7036042B1 (en) * 2002-08-16 2006-04-25 3Pardata Discovery and isolation of misbehaving devices in a data storage system

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
ANGIOLINI, FREDERICO ET AL: "Netwoks on chips: A synthesis perspective", 22 July 2006 (2006-07-22), XP002473818, Retrieved from the Internet <URL:http://web.archive.org/web/20060722183309/http://www-micrel.deis.unibo.it/~angiolini/parco05.pdf> [retrieved on 20080325] *
ANGIOLINI, FREDERICO ET AL: "Reliability support for on-chip memories using networks-on-chip", ICCD PROCEEDINGS 2006, 1 October 2006 (2006-10-01) - 4 October 2006 (2006-10-04), pages 296 - 306, XP002473819, Retrieved from the Internet <URL:http://infoscience.epfl.ch/record/89529> [retrieved on 20080325] *
PANDE P P ET AL: "High-Throughput Switch-Based Interconnect for Future SoCs", PROCEEDINGS OF THE IEEE INTERNATIONAL WORKSHOP ON SYSTEM-ON-CHIP FOR REAL-TIME APPLICATIONS, IEEE, PISCATAWAY, NJ, US, July 2003 (2003-07-01), XP002320368 *

Also Published As

Publication number Publication date
US20100080124A1 (en) 2010-04-01
WO2008038235A2 (en) 2008-04-03
US7995599B2 (en) 2011-08-09

Similar Documents

Publication Publication Date Title
WO2008038235A3 (en) Method to manage the load of peripheral elements within a multicore system
WO2006128147A3 (en) Systems and methods for a fault tolerant voice-over-internet protocol (voip) architecture
WO2007069245A3 (en) System and method for providing network security to mobile devices
WO2010027659A3 (en) Dynamically instantiating services by installing software in nodes of a service insertion architecture
WO2007064637A3 (en) System and method for failover of iscsi target portal groups in a cluster environment
WO2006096657A3 (en) System and method for a fast, programmable packet processing system
WO2008045370A3 (en) Method, system and apparatus for a dual mode mobile device
WO2007016518A3 (en) Communication protocol testing system
WO2008027964A3 (en) Binding methods and devices in a building automation system
WO2009008007A3 (en) Data packet processing method for a multi core processor
WO2006078562A3 (en) System, node, and method optimizing data connections for packet services
WO2007064477A3 (en) Network access control for many-core systems
EP1596303A3 (en) Fault recovery method in a system having a plurality of storage systems
WO2010054235A3 (en) Safe browser plugins using native code modules
WO2008042116A3 (en) Apparatus, system, and method for sharing output contacts across multiple relays
WO2007002443A3 (en) Control of service workload management
WO2007084973A3 (en) Network security system and method
WO2007142866A3 (en) Context-aware migration of communication session
WO2011106588A3 (en) An add-on module and methods thereof
WO2011067062A3 (en) Provisioning services using a cloud services catalog
WO2010132456A3 (en) System and method for priority delivery of load management messages on ip-based networks
WO2007089283A3 (en) System and method for providing computer services
WO2010036656A3 (en) Directing data units to a core supporting tasks
FR2901442B1 (en) SECURE FILE TRANSFER METHOD
WO2011100921A3 (en) Multi-service node management system, device and method

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07826548

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 07826548

Country of ref document: EP

Kind code of ref document: A2

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载