WO2008001461A1

WO2008001461A1 - Semiconductor integrated circuit

Info

Publication number: WO2008001461A1
Application number: PCT/JP2006/313099
Authority: WO
Inventors: Seiichi Nishijima; Iwao Sugiyama
Original assignee: Fujitsu Limited
Priority date: 2006-06-30
Filing date: 2006-06-30
Publication date: 2008-01-03
Also published as: JPWO2008001461A1; JP4551474B2

Abstract

Provided is a power supply control circuit capable of reducing a leak current and a power consumption by building a power supply control system on a circuit so as to supply power only to an operation block. The power supply control circuit is arranged on a semiconductor integrated circuit including: a buffer unit of an operation block which inputs input data and a Valid signal indicating whether the input data is valid data and holds the input data if it is valid; a logic unit of the operation block which executes an operation process by using accumulated data when the number of accumulated data held in the buffer has reached a predetermined number and outputs the Valid signal indicating whether the output data after the operation process and the output data are valid; and a power supply switch control unit which controls a switch unit of the operation block to turn ON/OFF the power supply so that power is supplied before the logic unit executes an operation process.

Description

Specification

Semiconductor integrated circuit

Technical field

The present invention relates to a technique for suppressing leakage current of a semiconductor integrated circuit.

Background art

[0002] In recent years, there has been a problem that leakage current (leak current) increases with the miniaturization of transistors formed in LSI (Large Scale Integration) such as IC chips.

[0003] The cause of current leakage (leakage) is the leakage current due to the quantum tunnel effect. Since the phenomenon of electrons passing between the insulating layers can occur probabilistically, the leakage current cannot be ignored as the circuit becomes highly integrated. In addition, if the leakage current increases, the power consumption of the LSI increases, the amount of heat generation increases, and the circuit board is easily damaged.

[0004] Generally, power consumption due to leakage current accounts for about half of the total power consumption of LSI. Here, the total power consumption is the sum of logic charge / discharge power and leakage power. For this reason, it is important to suppress the leakage current in order to increase the degree of integration, improve performance, and save LSI power.

[0005] For example, let us consider leakage current by a transistor formed on a semiconductor substrate shown in FIG. The transistor is formed on the semiconductor substrate 141 from a gate part 142 (Gate), a source part 143 (Source), a drain part 144 (Drain), and a mixed oxide 145 (Oxide). In such a structure, the gate leak 146 (Gate leakage), the sub-threshold leak 1 47 (Sub-threshold leakage), etc. occur. All of these leakage currents flow steadily regardless of pure computation (logic). In addition to CMOS (Metal Oxide Semiconductor) LSIs, there are also leakage powers in bipolar transistors.

[0006] Conventionally, leakage current has been suppressed by improving device process technology and materials.

However, this alone is not enough to prevent an increase in leakage current due to high integration. [0007] According to Patent Document 1, it is not necessary to provide a power supply stop line that stops supply of power supply voltage during standby and a power supply voltage supply line that is also supplied during standby to maintain the state during standby. A circuit block has been proposed that is connected to a power supply stop line to reduce leakage current.

[0008] Further, according to Patent Document 2, a logic circuit block synchronized with a supplied clock signal, a power supply switch for supplying power to the circuit block, and a control circuit for controlling the switch are necessary for circuit operation. There are proposals to reduce the leakage current by shutting off the power supply outside the period.

[0009] According to Patent Document 3, the system LSI is divided into functional block circuits, each block is connected to an independent power supply line, and power is supplied by the standby control circuit and the power supply control circuit to reduce power consumption. Proposals have been made.

[0010] According to Patent Document 4, the inside of a chip is divided into a plurality of circuit blocks, the supply of power supply voltage to the block can be cut off, and the path of a signal output from the blockable block to another block Proposals have been made to reduce power consumption by providing an inter-block interface circuit that can store signals.

[0011] However, in order to suppress the leakage current that increases due to further miniaturization in the future, it is not possible to obtain a sufficient effect only by controlling the power supply of each arithmetic block in the LSI as described above. In other words, the leakage current cannot be suppressed unless the power supply is controlled for each circuit constituting each calculation block in the LSI. To that end, it is necessary to control the power supply by grasping the flow and timing of input and output data of each circuit (computation block) in the LSI.

[0012] In Patent Documents 1 to 4, each operation block in the LSI is divided into a buffer unit and a logic unit, and after the data is transferred from the buffer unit, a power supply voltage is supplied to the logic unit, and the logic unit is stopped until then. It is not a configuration to do. In other words, a power supply control program is created according to the configuration and operation of each computation block, and power control is not performed by that control program.

[0013] In addition, when creating a power control program, if there are multiple data paths in the LSI, complicated control is required, so hardware suitable for power control is required.

Patent Document 1: JP 2004-015670 A

Patent Document 2: W〇99Z66640 Publication Patent Document 3: Japanese Patent Application Laid-Open No. 2004-140503

Patent Document 4: Japanese Unexamined Patent Publication No. 2003-092359

Non-Patent Document 1: Note 1) Nikkei Business Publications, Nikkei Electronics 2004 4-26 no.872, ρ99-127

[0014] The present invention has been made in view of the above circumstances, and reduces a leakage current by constructing on a circuit a power supply control system that supplies power only to necessary operation blocks when necessary. An object of the present invention is to provide a power supply control circuit that realizes low power consumption. A semiconductor integrated circuit provided with a calculation block for executing a calculation process according to one aspect of the present invention receives input data and a Valid signal indicating whether the input data is valid data. A buffer portion of the arithmetic block for holding input data in

When the number of stored data held in the buffer unit reaches a preset number of data, the stored data is used to execute a calculation process, and the output data after execution of the calculation process and the output data are valid A mouth portion of the arithmetic block that outputs a Valid signal indicating

A power switch control unit that performs power on / off in order to supply power before the arithmetic processing is performed by the logic unit; and that controls a switch unit of the arithmetic block.

[0015] Preferably, the calculation block includes a selector unit configured to set a connection between the input data and the data network provided to input the Valid signal to the calculation block, and the input data via the selector unit. And a data buffer unit that holds the input data for which the Valid signal is valid,

When the Valid signal is valid, the control unit writes the input data and the Valid signal to the data buffer unit, outputs a control signal, and the input data reaches the preset number of data, and the logic unit from the power switch controller In response to a power supply instruction to the data buffer unit, a read control signal for starting data transfer from the data buffer unit is output to the data buffer unit, and the time from the start of power supply to the logic unit to the end of the arithmetic processing of the logic unit And a W / R control unit for counting. [0016] Preferably, the power switch control unit may periodically notify the switching timing of the switch unit that controls power supply to the logic unit.

Preferably, a desired power consumption is reduced by determining an operating frequency of the logic unit based on a ratio between a leakage current of the logic unit and a charge / discharge current applied to the calculation.

[0017] With the above configuration, the circuit of each operation block constituting the LSI is subdivided, and the optimal power supply to the circuit that controls the power supply (the logic part of the operation block) can suppress the consumption of leakage current. The power consumption of the entire LSI can be reduced. In addition, leakage current consumption can be further reduced by increasing the operating frequency ratio of the circuit that can control power supply.

[0018] A semiconductor integrated circuit provided with a calculation block that executes a calculation process according to another aspect of the present invention receives input data and a Valid signal indicating whether the input data is valid data. A buffer unit of the arithmetic block for holding input data when the data is valid and issuing a full signal when the number of stored data held reaches a preset number of data;

When the number of stored data held in the buffer unit reaches a preset number of data, the stored data is used to execute a calculation process, and after the calculation process is executed, the output data and the output data are valid. Logic block of the operation block that outputs a Valid signal indicating whether or not there is,

The logic unit receives power supply permission and the full signal in order to supply power before execution of arithmetic processing, and controls the switch unit of the arithmetic block that performs power on / off. A control unit;

Issuing a token for controlling power on / off to the power control unit, allowing the power supply to the logic unit, and canceling the power supply permission from the power control unit when the logic unit completes the arithmetic processing A token issuing unit for receiving a return token;

[0019] Preferably, the arithmetic block includes a selector unit configured to set a connection between the input data and the data signal provided to input the valid signal to the arithmetic block, and the input via the selector unit. A data buffer unit for inputting the data and the Valid signal, and holding the input data for which the Valid signal is valid; When the Valid signal is valid, write the input data and the Valid signal to the data buffer unit, and output a control signal. The input data reaches the preset number of data and starts data transfer from the data buffer unit. A WZR control unit that outputs a read control signal and a full signal to the power control unit to the data buffer unit;

Upon receipt of the power supply permission token and the full signal issued from the token issuing unit to the logic unit, the switch unit is switched to supply power to the logic unit, and supply power to the logic unit. A power control unit that counts the time from the start to the end of the arithmetic processing of the logic unit.

[0020] Preferably, the operating frequency of the logic unit is determined based on a ratio between a leakage current of the logic unit and a charge / discharge current applied to the calculation, thereby reducing desired power consumption. The program of the power switch control unit can easily create a program, focusing only on token control without being aware of the internal operation when A to Z calculation starts and ends.

[0021] A semiconductor integrated circuit provided with a calculation block for executing a calculation process, which is another aspect of the present invention,

When input data and a Valid signal indicating whether the input data is valid are input, the input data is retained when the data is valid, and the number of stored data that has been retained reaches a preset number of data When the number of accumulated data held in the buffer unit reaches a preset number of data, an arithmetic process is executed using the accumulated data, A mouth portion of the computation block that outputs output data after computation processing and a Valid signal indicating whether the output data is valid;

The logic unit receives the toggle signal from the buffer unit to supply power before executing the arithmetic processing, and controls the switch unit of the arithmetic block that performs power on / off to the logic unit. A power control unit for the block.

Preferably, a desired power consumption is reduced by determining an operating frequency of the logic unit based on a ratio between a leakage current of the logic unit and a charge / discharge current applied to the calculation. The above configuration simplifies power supply control. The order of data exchange between computation blocks (data network topology) is switched, and when there are inputs from multiple computation blocks, the connection between the network and computation blocks becomes complicated. Even in this case, it is sufficient to define only the relationship between the transfer source (source) calculation block and the transfer destination (target) calculation block in the power switch control unit in the calculation block. Also, fine control can be easily performed by subdividing the blocks.

According to the present invention, the leakage current consumption is suppressed by subdividing the circuit of each operation block constituting the LSI and supplying the optimum power to the circuit that controls the power supply (the logic part of the operation block). It is possible to reduce the power consumption of the entire LSI. In addition, the leakage current consumption can be further reduced by increasing the operating frequency ratio of the circuit that can control the power supply.

FIG. 1 is a block diagram showing a configuration of Example 1.

FIG. 2 is a block diagram illustrating a configuration of each calculation unit according to the first embodiment.

FIG. 3 is a term chart showing the operation of the logic unit.

[Fig. 4] Comparison of leakage current reduction.

FIG. 5 is a flowchart showing the operation of the first embodiment.

FIG. 6 is a flowchart showing the operation.

FIG. 7 is a time chart showing power supply control.

FIG. 8 is a block diagram showing a configuration of Example 2.

FIG. 9 is a block diagram showing a configuration of each calculation unit in the second embodiment.

FIG. 10 is a flowchart showing the operation of the second embodiment.

FIG. 11 is a block diagram showing a configuration of Example 3.

FIG. 12 is a block diagram illustrating a configuration of each calculation unit according to the third embodiment.

FIG. 13 is a flowchart showing the operation of the third embodiment.

FIG. 14 shows a structure of a transistor.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. (Example 1)

FIG. 1 is a schematic diagram showing the internal configuration of LSI 1 using the present invention. Fig. 1 shows an example of the LSI 1 configuration consisting of a power supply unit 2, a data network 3, a power supply switch control unit 4, and operation blocks 5a to 5z.

[0025] For example, if the function of LSI1 is considered as a baseband processing unit of a demodulating unit such as a wireless LAN, each arithmetic block 5a to 5z can be thought of as a circuit that realizes functions such as a filter unit and an FFT unit. S can. When executing each function serially as in the above baseband processing, the operation blocks 5a to 5z perform operation processing and transfer data to the next operation block via the data network 3. If the output of the previous-stage calculation block is used as the input of the next-stage calculation block after the previous-stage calculation block has completed processing, the leakage current can be reduced by supplying power only to the currently used calculation block. However, the present invention is not limited to serial processing, but is effective in a system in which only the operation block being processed is operating and the other operation blocks are stopped.

A power supply unit 2 shown in FIG. 1 supplies power to each circuit of the LSI 1. The data network 3 is configured by a crossbar network or a bus network, and is a data path that interconnects the operation blocks 5a to 5z. Data network 3 sends input data and valid data to each computation block, and outputs the output data of each computation block to the computation block and other peripheral circuits via the output network. The valid data is data for determining whether or not the input data used in each calculation block is valid. For example, it is synchronized with the clock and sent with the data. Data can be transferred serially or in parallel.

[0027] The power switch controller 4 controls the power supply timing of each of the operation blocks 5a to 5z. Each arithmetic block 5a-5z is provided with buffer units 6a-6z and logic units 7a-7z. The power supply unit 2 supplies both to the buffer units 6a to 6z and the logic units 7a to 7z. The buffers 6a to 6z always supply power so that input data can be held at any time. The logic units 7a to 7z execute the arithmetic processing described above, and when the arithmetic processing is performed, the switch units 8a to 8z are controlled to supply power. The configuration of the power switch control unit 4 may be a CPU, reconfigurable hardware, or dedicated hardware. When executed by a CPU, etc. When configuring with configurable hardware, etc., the program is read when LSI1 is started and then executed.

Next, FIG. 2 shows the configuration of the operation blocks 5a to 5z. The buffer unit 6 includes a selector unit 21, a W / R control unit 22, a data buffer unit 23, and the like. Input data and Valid signal are input to computation blocks 5a to 5z, and output data and output Valid signal are output after computation processing.

The selector unit 21 sets the connection between the data network 3 and the buffer unit 6 by the circuit setting signal, and takes in the input data and the Valid signal to the calculation block. Set the transfer source information of the transfer source calculation block that sends input data and Valid signal for each calculation block, and the transfer destination information of the transfer destination calculation block that outputs input data and Valid signal as the output of the calculation block. Yes.

The W / R control unit 22 performs control for writing the input data input via the selector unit 21 into the data buffer unit 23. The input data has data used by the logic unit 7 and is synchronized with the data input clock. Further, only valid input data is written into the data buffer unit 23 based on the Valid signal input via the selector unit 21. A power control signal (external operation start trigger) is periodically acquired from the power switch control unit 4 and data and valid signal transfer to the logic unit 7 is started. For example, when a predetermined number of data is accumulated in the data buffer unit 23 and an external operation start trigger is received, the W / R control unit 22 outputs a read control signal to the data buffer unit 23 and starts transfer.

The data buffer unit 23 performs data transfer to the logic unit 7. The data buffer unit 23 stores the input data in the memory and transfers the data to the logic unit 7. Data can be written to memory using a method that saves data to a general address, or it can be saved in the order of input, such as FI F〇.

The switch unit 8 can control power supply by a transistor. For example, control is performed using an inverter 24 and transistors 25 and 26. In this example, transistors 25 and 26 are connected using different junctions, so the power control signal (external operation start trigger) from power switch control unit 4 is inverted by inverter 24 and input to transistor 25. . One transistor 26 is input without being inverted. Here, power on / off of the logic unit 7 is performed on the VDD side and the GND side of the logic unit 7, but only the VDD side may be used. If only the VDD side is used, the area is not wasted compared to the case where both are turned on compared to turning on / off the power on both sides. When inserted on the GND side, potential differences may occur between the gate and the Si substrate of the transistor in the circuit block, or between the gate and drain (source), and the cause of the gate leakage current cannot be completely removed. There is.

(Description of operation)

The input data is transferred from the input port via the data network 3 to the operation blocks 5a to 5z based on the data network setting previously set by the register. Then, the processed output data and the output valid signal are output to other calculation blocks or output ports.

Here, consider a case where the calculation block 5a has a 64-point FFT, an operating frequency f = 40 MHz, and an operating frequency ratio m = 2. Figure 3 shows the timing chart for (1) input data signal waveform, (2) data buffer unit 23 output signal waveform, and (3) change in Vdd '(power control signal).

[0035] The waveform of (1) is sent to the calculation block 5a via the data network 3 on the operating frequency of f = 40 MHz. Since computation block 5a operates at an operating frequency of fXm = 80MHz, it receives valid data once every two cycles. In the case of a 64-point FFT, 64 data are required for one FFT operation, so 64 data are acquired from 128 cynoles * (l / 80MHz). Next, 64 pieces of data are transferred from the buffer unit 6 to the logic unit 7. At that time, power is supplied to the logic unit 7 (Vdd 'is supplied), and Vdd' is shut off after the calculation is completed. The leakage current can be reduced only during the period when the supply of Vdd ′ is stopped.

Here, the memory size of the data buffer unit 23 differs depending on the operation assigned to the block unit 7. A 64-point FFT requires a minimum of 64 cycles. Assuming that the ratio of the leakage current of the logic unit 7 and the charge / discharge current for calculation is 1: 1, the current consumption is Current consumption = 1 ""-

2

[0037] When m = 2, the power consumption can be reduced to 3/4 of the conventional one as shown in FIG. Conventionally, at frequency f = l, the calculation processing that requires power consumption 2 (the sum of leakage power 1 and logic charge / discharge power 1) over the calculation time 0 to 2 in Fig. 1 (a) By doubling m = 2, the power can be turned on for half the time compared to the conventional method, and the leakage power can be reduced by half. As a result of (b) in the figure, the effect of reducing the total power to 3Z4 is obtained. The generalization of the power reduction effect for parameter m is shown in (Equation 1). The higher the operating frequency ratio m, the lower the current consumption. In addition, as the circuit block is subdivided, the power supply can be controlled more carefully and the current can be minimized by optimal control.

(Operation flow)

Next, the operation flow of the first embodiment will be described with reference to FIG.

In step S51, a control program for the power switch control unit 4 is set. In step S52, as described above, the power control signal is transferred to each computation block to notify the power on / off timing.

[0039] In step S53, each calculation block is set. In the W / R control unit 22, the number of stored data (Ndata) and logic processing time (Toutoff) are set as constants by the circuit setting signal, and the data read count (Counter) and logic processing time are set as variables. Initialize the count number (timer). In the same figure, initialization is set to 0 and the up-counting is performed, but even if the down-counting is performed, the power is confusing. In addition, a meter for realizing the function is set for the logic unit 7. The circuit setting signal shown in Fig. 2 sets parameters corresponding to the real and imaginary parts of the complex data, for example, in FFT calculations. For digital filter operations, the corresponding filter coefficient is set as a parameter.

In step S54, the selector unit 21 of each calculation block shown in FIG. 2 is set (SEL) by the circuit setting signal shown in FIG. Here, steps S5:! To 54 in the setting process surrounded by a broken line The order does not limit the invention. The setting process is a setting by the CPU or dedicated hardware responsible for overall control.

[0041] In step S55, the input data and valid signal of each calculation unit are taken into the data buffer unit 23 and the WZR control unit 22 based on the connection (SEL) of the selector unit 21.

In step S56, the W / R control unit 22 writes only data for which the Valid signal is valid to the data buffer unit 23. The write control signal is output to the data buffer unit 23 for writing. The WZR control unit 22 increments the data read count (Counter) each time one valid data is written. The count here counts the number of valid data, and counts the valid signal.

In step S 57, it is determined whether a predetermined number of valid input data has been written in the data buffer unit 23. That is, it is determined whether the data reading count number (Counter) = the accumulated data number (N data) is satisfied. If established (YES), the process proceeds to step S58, and if not established, loops in S57 until established.

[0043] In step S58, the power supply control signal (external operation start trigger) from the power supply switch control unit 4 controls the switch unit 8 that supplies power to the logic unit 7 of the corresponding operation block to conduct the logic unit process. Start counting up the time count (timer).

[0044] In step S59, the data buffer unit 23 transfers the accumulated data of Ndata to the logic unit. In step S510, the logic unit 7 receives data and starts calculation. After that, the data that has been calculated is output from the logic unit 7 in step S511.

Step S512 After the processing of the logic unit 7 is completed, the power is turned off when the logic unit processing time (Toutoff) = logic unit processing time count (timer). Also initialize variables.

Next, as shown in FIG. 5, in order to perform arithmetic processing in the next arithmetic block, the process proceeds to step S55. For example, consider the case where the calculation block A shown in FIG. 6 is the first stage, the calculation block to be processed next is the calculation block B, and the processing up to the calculation block Z is sequentially processed. The calculation block B obtains input data from the calculation block A or the data network 3. Computation block B completes the processing of the buffer part and the logic part in the same way as computation block A, and moves to computation block C in the next stage. Repeat this process until operation block Z Do the arithmetic.

[0047] Here, there is no problem even if computation block A and computation block B perform computations simultaneously. When such parallel processing is required, the control program of power switch control unit 4 is different from that shown in FIG. You can make a simple program.

(Power control)

Figure 7 explains the power supply operation. The waveform of period (c) shown in (i) of FIG. 7 indicates switching of the switch unit 8 (transistors 25 and 26 shown in FIG. 2). When power supply to the logic unit 7 starts, the power supply voltage of the logic unit 7 shown in (Port) rises, and after the period of (b) in the figure (after the power supply voltage has stabilized), the logic unit 7 starts arithmetic processing ( The period calculation process shown in (a) of Fig. 6 is executed. After the calculation is completed, the switch unit 8 is switched to shut off the power supply. Thus, when creating the control program of the power switch control unit 4, it is necessary to provide a period (b) in which the logic unit 7 is in a stable operation state.

[0048] As described above, only when the logic unit 7 operates, the power switch control unit 4 supplies power to the corresponding calculation block, thereby stopping the power supply path every time the calculation process is completed. Stop power supply. However, power is always supplied to the no-uffer section 6. This is because data input is always possible regardless of the power supply state. The same applies to the buffer section 6 of all the computation blocks. For this reason, it is possible to transfer data without being aware of each other's power supply status.

[0049] Further, as a clock to be given to LSI 1 having the above system, a clock having an operation frequency m times that of input data is given to the logic unit, thereby reducing the computation time to 1 / m. As a result, the computation time can be reduced to 1 / m, and the power supply time can be reduced to 1 / m of the conventional one. The leakage current of the logic part can be stopped during the power-off period.

(Example 2)

The second embodiment is not a direct control between the operation block and the power switch control unit as shown in the first embodiment. A token bus is provided between the token issuing unit and each calculation block, and power is supplied using tokens (power supply right). Immediately after LSI81 is started, the right calculation is granted to the first stage calculation block. Then, as soon as the computation in the computation block is completed, the right is returned to the power switch control unit. The token issuing unit that received the return token is the next It has a mechanism for starting a power supply by passing a token to the operation block of the stage.

FIG. 8 shows an example in which the LSI 81 is composed of a power supply unit 82, a data network 83, a token issuing unit 84, arithmetic blocks 85a to 85z, and the like.

For example, when considering the function of the LSI 81 as a baseband processing unit of a demodulation unit such as a wireless LAN as in the first embodiment, each of the operation blocks 85a to 85z is a circuit that realizes functions such as a filter unit and an FFT unit. In addition, each of the operation blocks 85a to 85z performs an operation process and transfers it to the next operation block via the data network 83. If the output of the previous-stage calculation block is used as the input of the next-stage calculation block after the previous-stage calculation block completes processing, power is supplied only to the currently used calculation block, so that leakage current can be reduced.

The power supply unit 82 supplies power to each circuit of the LSI 81. The data network 83 is a data path that interconnects the respective operation blocks 85a to 85z configured by a crossbar network or a bus network. The data network 83 sends the input data and valid data to each computation block, and further forwards the output data and output valid signal of each computation block to other peripheral circuits via the computation block and output port. The valid data is data for determining whether or not the input data used in each calculation block is valid.

[0052] The token issuing unit 84 controls the power supply timing of each of the operation blocks 85a to 85z. Each arithmetic block 85a to 85z is provided with a buffer part 86a to 86z and a logic part 87a to 87z. The power is supplied together with the buffer units 86a to 86z and the logic units 87a to 87z. As in the first embodiment, the buffer units 86a to 86z always supply power so that input data can be held at any time. The logic units 87a to 87z supply power by controlling the switch units 88a to 88z by the power control units 89a to 89z only when executing the arithmetic processing described above.

[0053] The configuration of the token issuing unit 84 may be a CPU, reconfigurable hardware, or dedicated hardware. When the program is executed by the CPU, or when it is configured by reconfigurable hardware, the program may be read and executed when LSI81 is started.

Next, the operation blocks 85a to 85z have the configuration shown in FIG. The buffer unit 86 includes a selector unit 91, a W / R control unit 92, a data buffer unit 93, and the like.

Input data and Valid signals are input to the calculation blocks 85a to 85z. Output the output data and output valid signal from the computation block. The selector unit 91 presets the connection between the data network 83 and the buffer unit 86 by the circuit setting signal, and takes in the input data and the Valid signal to the calculation block.

The W / R control unit 92 performs control for writing the input data and the valid signal input via the selector unit 91 into the data buffer unit 93. The input data has a data value used in the logic unit 87 and is synchronized with the data input clock. Further, only valid input data is written to the data buffer unit 93 based on the Valid signal input via the selector unit 91.

The data buffer unit 93 stores the input data in the memory and transfers the data to the logic unit 87. Data can be written to memory by writing data to a general address, or it can be saved in the order of input like FIFO. Also, data transfer to the logic unit 87 is performed.

The power supply control unit 89 in the calculation block switches the switch unit 88 when detecting that a predetermined number of data is accumulated in the data buffer unit 93 and a token is acquired from the token issuing unit 84. Then, power is supplied to the logic unit 87. Transfer of accumulated data to the logic unit 87 is started in the data buffer unit 93.

The switch unit 88 controls power supply using transistors 95 and 96. For example, control is performed using an inverter 94 and transistors 95 and 96. In this example, since transistors 95 and 96 use different junctions, the power supply control signal (operation start trigger) from the power supply control unit 89 is inverted by the inverter 94 and input to the transistor 95. Input to one transistor 96 without inversion. Power is turned on / off on the VDD and GND sides. In this example, the GND side is switched by the transistor 96. Only the VDD side can be switched.

(Description of operation)

Next, the operation flow of the second embodiment will be described with reference to FIG.

[0059] In step S101, the token issuing unit 84 sets a control program for issuing a token. As described above, a token is issued to each computation block to grant rights to the computation block and notify the power on / off timing.

[0060] Further, in step S102, parameters for realizing functions for the logic unit, etc. Set. The circuit setting signal shown in Fig. 9 sets parameters corresponding to the real and imaginary parts of the complex data, for example, in FFT calculations. For digital filter operation, set the corresponding filter coefficient parameter.

In step S103, the selector unit 91 of each calculation block shown in FIG. 10 is set (SEL) by the circuit setting signal shown in FIG.

In step S104, the power supply of each calculation block is set. In the W / R control unit 92, the number of accumulated data (Ndata) and the logic unit processing time (Toutoff) are set as constants. Step S105 initializes the data read count (Counter) and logic processing time count (timer) as variables. In this figure, initialization is set to 0 and up-counting is performed, but down-counting is acceptable. Here, step S10 in the setting process surrounded by a broken line: The order of! To 105 is not limited. The setting process is a setting by the CPU or dedicated hardware that controls the entire system.

In step S106, the token issuing unit 84 issues a token to the target calculation block.

In step S107, the input data and valid signal of each calculation unit are fetched based on the connection (SEL) of the selector unit 91.

In step S108, the W / R control unit 92 writes only data for which the Valid signal is valid into the data buffer unit 93. When the Valid signal is valid, it writes the input data and Valid signal to the data buffer unit 93 and outputs the control signal. Each time one valid data is written, the data reading count (Counter) is incremented.

[0064] In step S109, the power supply control unit 89 receives the token and determines the force with which a predetermined number of valid input data is written in the data buffer unit 93. In other words, it is judged whether the number of data read counts (Counter) = the number of stored data (Ndata) is satisfied. If established (YES), the process proceeds to step S1010. If not established, loops at S109 until established. When the number of data set in advance is reached, the WZR control unit outputs a read control signal for starting data transfer from the data buffer unit 103 and a full signal to the power supply control unit 103 to the data buffer unit 103.

[0065] In step S1010, the power supply control signal (operation start trigger) from the power supply control unit 89 controls and introduces the switch unit 88 that supplies power to the logic unit 87 of the corresponding computation block. Start counting up the logic part processing time count (timer).

In step S 1011, the data buffer unit 93 transfers the stored data for Ndata to the logic unit. In step S1012, the logic unit 87 receives data and starts calculation. After that, the completed data is output from the logic unit 87 in step S1013.

In step S1014, after the processing of the logic unit 87 is completed, the power is turned off when the logic unit processing time (Toutof f) = the logic unit processing time count (timer). Also initialize variables.

In step S1015, the power supply control unit 89 returns the right to the token issuing unit 84. In step S1016, the token issuing unit 84 receives the return token.

Then, the processing shifts to step S106 in order to perform arithmetic processing in the next arithmetic block. For example, processing block A is the first stage, the next processing block to be processed is processing block B, and processing up to processing block Z is performed in order. Computation block B obtains input data from computation block A or data network 3. Computation block B completes the processing of the buffer part and the processing of the logic part in the same way as computation block A, and moves to computation block C in the next stage. This process is repeated until computation block Z is performed.

[0069] Here, there is no problem even if computation block A and computation block B perform computations simultaneously. When such parallel processing is required, the control program of token issuing unit 84 is different from that shown in FIG. do it.

(Example 3)

When the order of data transfer between blocks (data network topology) is switched, or when there are inputs from multiple operation blocks, the connection between the network and the operation blocks becomes complicated. In that case, only the relationship between the source and target computation blocks needs to be defined in the power supply controller. Fine-grained control can be easily performed by subdividing the calculation block.

FIG. 11 shows an example in which the LSI 111 is configured from a power supply unit 112, a data network 113, arithmetic blocks 114a to 114z, and the like.

For example, assuming that the function of LSI 111 is the baseband processing unit of a demodulation unit such as a wireless LAN, as in the first embodiment, each calculation block 114a to 114z implements the function of the filter unit, the FFT unit, and the like. This is the circuit that appears. In addition, each of the operation blocks 114a to 114z performs an operation process and transfers it to the next operation block via the data network 113. If the output of the previous-stage calculation block is used as the input of the next-stage calculation block after the previous-stage calculation block has completed processing, power is supplied only to the currently used calculation block, so that leakage current can be reduced.

The power supply unit 112 supplies power to each circuit of the LSI 111. The data network 113 is a data path that interconnects the respective operation blocks 114a to 114z configured by a cross spa network or a bus network. The data network 113 sends the input data and valid signal to each computation block, and further transfers the output data and output valid signal of each computation block to other peripheral circuits via the computation block and output port.

[0072] Each of the operation blocks 114a to 114z is provided with a node 115a to 115z and a logic block 16a to 116z. The power is supplied to the buffer units 115a to 115z and the logic units 116a to 116z. The buffer units 115a to 115: 115z always supplies power so that input data can be held at any time. The logic units 116a to 116z execute the arithmetic processing described above, and control the switch units 117a to 117z to supply power when performing the arithmetic processing. The power control units 118a to 118z of the respective arithmetic blocks 1 14a to 14z control the timing of power supply.

Next, the calculation blocks 1 14a to 114z have the configuration shown in FIG. The buffer unit 115 includes a selector unit 121, a W / R control unit 122, a data buffer unit 123, and the like.

[0074] The calculation blocks 114a to 114z are provided with an input port for inputting input data and a valid signal, and an output port for output data from the calculation block.

The selector unit 121 sets the connection between the data network 113 and the buffer unit 115 based on the circuit setting signal, and takes the input data and the Valid signal into the calculation block.

The W / R control unit 122 performs control for writing the input data input via the selector unit 121 to the data buffer unit 123. In addition, the W / R control unit 122 switches the switch unit 117 by a toggle signal. When a predetermined number of data is accumulated in the data buffer unit 123, transfer to the logic unit 116 is started. The input data has data used by the logic unit 116 and is synchronized with the data input clock. Further, only valid input data is written to the data buffer unit 123 based on the Valid signal input via the selector unit 121. The data buffer unit 123 stores input data in the memory and transfers the data to the logic unit 116. Data write to the memory (Write) may be a method of storing data at a general address, or may be stored in the order of input like a FIFO.

The switch unit 117 can control power supply by the transistors 125, 126 and the like. For example, the inverter 124 and transistors 125 and 126 are used for control. In this example, since the transistors 125 and 126 are different junctions, the signal from the power supply control unit 118 is inverted by the inverter 124 and input to the transistor 125. Input to one transistor 126 without inversion.

[0078] In this example, the transistor 126 is also used to switch the GND side, and only the transistor 125 is used, and only the VDD side can be switched.

(Description of operation)

In the third embodiment, after the setting of the logic unit 116, the WZR control unit 122, and the selector unit 121 is completed by the circuit setting signal, (1) input data is taken into the calculation block via the selector unit. Only the input data for which the Valid signal is valid is selected by the W / R control unit 122 and written to the data buffer unit 123. The data buffer unit 123 transfers the data to the logic unit 116 when a certain number of data determined by the circuit setting signal is accumulated in the data buffer unit 123. The W / R control unit 122 turns on the power supply Vdd 'and the ground GND' to supply power by sending a signal serving as a toggle for conducting the switch to the power supply control unit 118 simultaneously with data writing. . In addition, the W / R control unit 122 sends a signal after the processing data is output from the logic unit 116 to shut off the power supply. Timing setting from power supply to shut-off is made by circuit setting signal.

Next, the operation flow of the third embodiment will be described with reference to FIG.

In step S 131, parameters for realizing the function are set for the logic unit. The circuit setting signal shown in Fig. 13 sets parameters corresponding to the real and imaginary parts of the complex data, for example, in FFT calculations. For digital filter operations, set the corresponding filter coefficient parameter.

In step S132, the selector unit 121 of each calculation block is set (SEL) by the circuit setting signal shown in FIG. In step S133, the power supply of each calculation block is set. In the W / R control unit 122, the number of accumulated data (Ndata) and the logic unit processing time (Toutoff) are set as constants. In step 134, the data reading count (Counter) and the logic section processing time count (timer) are initialized as variables. In this figure, initialization is set to 0 and up-counting is performed, but down-counting is acceptable. Here, the order of steps S131 to S34 of the setting process surrounded by a broken line is not limited.

In step S135, the input data and valid signal of each calculation unit are fetched based on the connection (S EL) of the selector unit 121.

In step S 136, only data for which the Valid signal is valid is written into the data buffer unit 123, and the data reading count (Counter) is incremented each time one valid data is written. When the Valid signal is valid, the input data and Valid signal are written to the data buffer unit 123 and the control signal is output.

In step S 137, it is determined whether a predetermined number of valid input data has been written in the data buffer unit 123. That is, it is determined whether or not the data read count number (Counter) = the accumulated data number (Ndata) is satisfied. If satisfied and YES (YES), the process proceeds to step SI38, and if not satisfied, loops at S137 until satisfied. When the W / R control unit reaches the preset number of data, it outputs a read control signal for starting data transfer from the data buffer unit 123 and a full signal to the power control unit 123 to the data buffer unit 123.

In step S 138, the power supply control unit 118 receives the toggle signal, and controls and turns on the switch unit 117 that supplies power to the logic unit 116. Then, the logic unit processing time count number (timer) starts counting up.

In step S 139, the data buffer unit 123 transfers the stored data for Ndata to the logic unit 116. In step S1310, the logic unit 116 receives data and starts calculation. Thereafter, the data and the V alid signal are output from the logic unit 106 in step S1311 for the completed data.

In step S1312, the power is shut down when the logic unit processing time (Tout off) = the logic unit processing time count (timer) after the processing of the logic unit 116 is completed. Also initialize variables. Then, the process proceeds to step S135 in order to perform calculation processing in the calculation block at the next stage. For example, processing block A is the first stage, the next processing block to be processed is processing block B, and processing up to processing block Z is performed in order. Computation block B obtains input data from computation block A or data network 3. Computation block B completes the processing of the buffer part and the processing of the logic part in the same way as computation block A, and moves to computation block C in the next stage. This process is repeated until computation block Z is performed.

Here, there is no problem even if different calculation blocks perform calculations simultaneously.

The present invention is not limited to the above-described embodiment, and various improvements and modifications can be made without departing from the gist of the present invention.

Claims

The scope of the claims

[1] A semiconductor integrated circuit provided with an arithmetic block for executing arithmetic processing,

The input data and a Valid signal indicating whether the input data is valid data are input, and the buffer block of the arithmetic block that holds the input data when valid, and the number of stored data held in the buffer unit When reaches the preset number of data

An arithmetic process using the accumulated data, and an output data after execution of the arithmetic process and a valid signal indicating whether the output data is valid.

A power switch control unit that controls the switch unit of the calculation block to perform power on / off to supply power before the logic unit performs the calculation process;

A semiconductor integrated circuit comprising:

[2] The calculation block is:

A selector unit for setting a connection with the data network provided for inputting the input data and the Valid signal to the arithmetic block;

A data buffer unit for inputting the input data and the Valid signal via the selector unit and holding the input data for which the Valid signal is valid;

When the Valid signal is valid, the control unit writes the input data and the Valid signal to the data buffer unit, outputs a control signal, and the input data reaches the preset number of data, and the logic unit from the power switch control unit In response to a power supply instruction to the data buffer unit, a read control signal for starting data transfer from the data buffer unit is output to the data buffer unit, and the time from the start of power supply to the logic unit to the end of the arithmetic processing of the logic unit W / R control unit that counts

The semiconductor integrated circuit according to claim 1, comprising:

[3] The power switch controller

2. The semiconductor integrated circuit according to claim 1, wherein a switching timing of the switch unit that controls power supply to the logic unit is periodically notified.

[4] The power consumption is reduced by determining an operating frequency of the logic unit based on a ratio between a leakage current of the logic unit and a charge / discharge current applied to the calculation. The semiconductor integrated circuit according to claim 1.

[5] A semiconductor integrated circuit provided with an arithmetic block for executing arithmetic processing,

When input data and a Valid signal indicating whether the input data is valid are input, the input data is retained when the data is valid, and the number of stored data that has been retained reaches a preset number of data When the number of accumulated data held in the buffer unit reaches a preset number of data, an arithmetic process is executed using the accumulated data, The logic block of the calculation block that outputs a valid signal indicating whether the output data and the output data are valid after execution of the calculation process;

Issuing a token for controlling power on / off to the power control unit, allowing the power supply to the logic unit, and canceling the power supply permission from the power control unit when the logic unit completes the arithmetic processing A semiconductor integrated circuit comprising: a token issuing unit that receives a return token;

[6] The calculation block is:

When the Valid signal is valid, write the input data and the Valid signal to the data buffer unit, and output a control signal. The input data reaches the preset number of data, and data transfer from the data buffer unit is started. A WZR control unit that outputs a read control signal and a full signal to the power control unit to the data buffer unit;

When the token for issuing power supply to the logic unit issued from the token issuing unit and the full signal are received, the switch unit is switched to supply power to the logic unit, and supply power to the logic unit. From the start to the end of the arithmetic processing of the logic part A power control unit for counting time;

6. The semiconductor integrated circuit according to claim 5, further comprising:

[7] The desired power consumption is reduced by determining an operating frequency of the logic unit based on a ratio between a leakage current of the logic unit and a charge / discharge current applied to the calculation. 5. The semiconductor integrated circuit according to 5.

[8] A semiconductor integrated circuit provided with an arithmetic block for executing arithmetic processing,

The logic unit receives the toggle signal from the buffer unit to supply power before executing the arithmetic processing, and controls the switch unit of the arithmetic block that performs power on / off to the logic unit. The power control section of the block;

A semiconductor integrated circuit comprising:

[9] The desired power consumption is reduced by determining an operating frequency of the logic unit based on a ratio between a leakage current of the logic unit and a charge / discharge current applied to the calculation. 5. The semiconductor integrated circuit according to 5.

[10] The selector outputs the input data and the Valid signal as the output of the arithmetic block, and the transfer source information of the arithmetic block that transmits the input data and the Valid signal for each arithmetic block. 2. The semiconductor integrated circuit according to claim 1, wherein transfer destination information of the operation block of the transfer destination to be set is set.

[11] The selector outputs the input data and the Valid signal as the output of the operation block, and the transfer source information of the operation block that transmits the input data and the Valid signal for each operation block. 6. The semiconductor integrated circuit according to claim 5, wherein transfer destination information of the operation block of the transfer destination to be set is set.

[12] The selector outputs the input data and the Valid signal as the output of the arithmetic block, and the transfer source information of the arithmetic block that transmits the input data and the Valid signal for each arithmetic block. 9. The semiconductor integrated circuit according to claim 8, wherein transfer destination information of the operation block of the transfer destination to be set is set.

13. The semiconductor integrated circuit according to claim 1, wherein the switch unit switches a power supply on and off of the logic unit by causing a power supply source and a ground to be connected by a transistor. .

14. The semiconductor integrated circuit according to claim 5, wherein the switch unit switches a power supply on and off of the logic unit by connecting a power supply source and a ground with a transistor. .

15. The semiconductor integrated circuit according to claim 8, wherein the switch unit switches a power supply on and off of the logic unit by connecting a power supply source and a ground with a transistor. .