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WO2007100551A3 - Very large scale integration of field effect transistors on si nanowires - Google Patents

Very large scale integration of field effect transistors on si nanowires Download PDF

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Publication number
WO2007100551A3
WO2007100551A3 PCT/US2007/004383 US2007004383W WO2007100551A3 WO 2007100551 A3 WO2007100551 A3 WO 2007100551A3 US 2007004383 W US2007004383 W US 2007004383W WO 2007100551 A3 WO2007100551 A3 WO 2007100551A3
Authority
WO
WIPO (PCT)
Prior art keywords
nanowires
field effect
large scale
effect transistors
scale integration
Prior art date
Application number
PCT/US2007/004383
Other languages
French (fr)
Other versions
WO2007100551A2 (en
WO2007100551A9 (en
Inventor
King-Ning Tu
Original Assignee
Univ California
King-Ning Tu
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ California, King-Ning Tu filed Critical Univ California
Publication of WO2007100551A2 publication Critical patent/WO2007100551A2/en
Publication of WO2007100551A9 publication Critical patent/WO2007100551A9/en
Publication of WO2007100551A3 publication Critical patent/WO2007100551A3/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
    • H10D62/121—Nanowire, nanosheet or nanotube semiconductor bodies oriented parallel to substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)

Abstract

An electronic device has a first electrical lead, a nonowire disposed on the first electrical lead, the nanowire having at least one semiconductor section between first and second metallic sections, a second electrical lead constructed to be in electrical contact with the first metallic section of the nanowire, and a third electrical lead in electrical contact with the metallic section of the nanowire. The nanowire has at least a partial oxide outer layer.
PCT/US2007/004383 2006-02-22 2007-02-21 Very large scale integration of field effect transistors on si nanowires WO2007100551A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US77534306P 2006-02-22 2006-02-22
US60/775,343 2006-02-22

Publications (3)

Publication Number Publication Date
WO2007100551A2 WO2007100551A2 (en) 2007-09-07
WO2007100551A9 WO2007100551A9 (en) 2007-11-01
WO2007100551A3 true WO2007100551A3 (en) 2008-07-17

Family

ID=38459517

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/004383 WO2007100551A2 (en) 2006-02-22 2007-02-21 Very large scale integration of field effect transistors on si nanowires

Country Status (1)

Country Link
WO (1) WO2007100551A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110001117A1 (en) * 2008-01-21 2011-01-06 President And Fellows Of Harvard College Nanoscale wire-based memory devices
FR3029010B1 (en) * 2014-11-24 2017-12-15 Commissariat Energie Atomique POLYCRYSTALLINE SEMICONDUCTOR NANOSTRUCTURE MATERIAL

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6465782B1 (en) * 1999-09-10 2002-10-15 Starmega Corporation Strongly textured atomic ridges and tip arrays
US20050066883A1 (en) * 2003-09-25 2005-03-31 Nanosys, Inc. Methods, devices and compositions for depositing and orienting nanostructures
WO2005093831A1 (en) * 2004-02-13 2005-10-06 President And Fellows Of Harvard College Nanostructures containing metal-semiconductor compounds
US20060008942A1 (en) * 2004-07-07 2006-01-12 Nanosys, Inc. Systems and methods for harvesting and integrating nanowires
WO2006132659A2 (en) * 2005-06-06 2006-12-14 President And Fellows Of Harvard College Nanowire heterostructures

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6465782B1 (en) * 1999-09-10 2002-10-15 Starmega Corporation Strongly textured atomic ridges and tip arrays
US20050066883A1 (en) * 2003-09-25 2005-03-31 Nanosys, Inc. Methods, devices and compositions for depositing and orienting nanostructures
WO2005093831A1 (en) * 2004-02-13 2005-10-06 President And Fellows Of Harvard College Nanostructures containing metal-semiconductor compounds
US20060008942A1 (en) * 2004-07-07 2006-01-12 Nanosys, Inc. Systems and methods for harvesting and integrating nanowires
WO2006132659A2 (en) * 2005-06-06 2006-12-14 President And Fellows Of Harvard College Nanowire heterostructures

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
VAN ZANT: "Microchip Fabrication", vol. FIFTH ED, 2004, MCGRAW-HILL, ISBN: 0-07-143241-8, pages: 405 *

Also Published As

Publication number Publication date
WO2007100551A2 (en) 2007-09-07
WO2007100551A9 (en) 2007-11-01

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