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WO2007036911A3 - Routage a fin pas dans une trame de fil d'apres un dispositif boitier de systeme sip - Google Patents

Routage a fin pas dans une trame de fil d'apres un dispositif boitier de systeme sip Download PDF

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Publication number
WO2007036911A3
WO2007036911A3 PCT/IB2006/053553 IB2006053553W WO2007036911A3 WO 2007036911 A3 WO2007036911 A3 WO 2007036911A3 IB 2006053553 W IB2006053553 W IB 2006053553W WO 2007036911 A3 WO2007036911 A3 WO 2007036911A3
Authority
WO
WIPO (PCT)
Prior art keywords
fine
component pads
package
sip
lead frame
Prior art date
Application number
PCT/IB2006/053553
Other languages
English (en)
Other versions
WO2007036911A2 (fr
Inventor
Dirk Peters
Original Assignee
Nxp Bv
Philips Corp
Dirk Peters
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv, Philips Corp, Dirk Peters filed Critical Nxp Bv
Priority to US12/088,713 priority Critical patent/US7825526B2/en
Priority to JP2008532965A priority patent/JP2009510759A/ja
Priority to EP06809439A priority patent/EP1935017A2/fr
Priority to CN2006800442975A priority patent/CN101317267B/zh
Publication of WO2007036911A2 publication Critical patent/WO2007036911A2/fr
Publication of WO2007036911A3 publication Critical patent/WO2007036911A3/fr

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    • H—ELECTRICITY
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

Dans un mode de réalisation illustratif, on prévoit un substrat de boîtier (200) permettant le montage d'un circuit intégré (CI) (205). Le substrat comprend une zone de mise en place du dispositif CI (290) entourée par des pastilles (235a, 235b, 235c, 235d). La pluralité des pastilles entoure les liaisons (215). Une pluralité de broches (225a, 225b, 225c, 225d, 245a, 245b, 245c, 245d) entoure les pastilles. Une ou plusieurs des broches, présentant des chemins conducteurs à pas fin (270), couple(nt) une ou plusieurs des broches avec un ensemble de connexions correspondantes (215) ou avec un ensemble de pastilles correspondantes. Les chemins conducteurs (270) traversent les régions placées entre la pluralité de pastilles.
PCT/IB2006/053553 2005-09-30 2006-09-28 Routage a fin pas dans une trame de fil d'apres un dispositif boitier de systeme sip WO2007036911A2 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US12/088,713 US7825526B2 (en) 2005-09-30 2006-09-28 Fine-pitch routing in a lead frame based system-in-package (SIP) device
JP2008532965A JP2009510759A (ja) 2005-09-30 2006-09-28 リードフレームベースのシステム−イン−パッケージデバイスにおけるファインピッチ配線
EP06809439A EP1935017A2 (fr) 2005-09-30 2006-09-28 Routage a fin pas dans une trame de fil d'apres un dispositif boitier de systeme sip
CN2006800442975A CN101317267B (zh) 2005-09-30 2006-09-28 基于引线框架中的精密间距布线的系统封装(sip)器件

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US72316105P 2005-09-30 2005-09-30
US60/723,161 2005-09-30

Publications (2)

Publication Number Publication Date
WO2007036911A2 WO2007036911A2 (fr) 2007-04-05
WO2007036911A3 true WO2007036911A3 (fr) 2007-07-05

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US (1) US7825526B2 (fr)
EP (1) EP1935017A2 (fr)
JP (1) JP2009510759A (fr)
CN (1) CN101317267B (fr)
WO (1) WO2007036911A2 (fr)

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US8203201B2 (en) * 2010-03-26 2012-06-19 Stats Chippac Ltd. Integrated circuit packaging system with leads and method of manufacture thereof
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JP5618873B2 (ja) * 2011-03-15 2014-11-05 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US9345137B2 (en) * 2013-11-04 2016-05-17 Lattice Semiconductor Corporation Partially depopulated interconnection arrays for packaged semiconductor devices and printed circuit boards
CN104637911B (zh) 2013-11-08 2019-07-05 恩智浦美国有限公司 具有路由基板的基于引线框架的半导体装置
US9947636B2 (en) * 2014-06-02 2018-04-17 Stmicroelectronics, Inc. Method for making semiconductor device with lead frame made from top and bottom components and related devices
FR3041209B1 (fr) * 2015-09-15 2017-09-15 Sagem Defense Securite Systeme electronique compact et dispositif comprenant un tel systeme
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CN108038274B (zh) * 2017-11-27 2021-08-20 深圳市兴森快捷电路科技股份有限公司 一种pcb与ic封装协同设计方法及装置
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CN112989744B (zh) * 2021-02-08 2023-11-17 泰凌微电子(上海)股份有限公司 一种半导体芯片的封装设计方法以及装置

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JP2009510759A (ja) 2009-03-12
US7825526B2 (en) 2010-11-02
US20100006992A1 (en) 2010-01-14
WO2007036911A2 (fr) 2007-04-05
CN101317267B (zh) 2010-09-08
EP1935017A2 (fr) 2008-06-25
CN101317267A (zh) 2008-12-03

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