+

WO2007031788A1 - Synthétiseur de fréquence avec une résolution fine - Google Patents

Synthétiseur de fréquence avec une résolution fine Download PDF

Info

Publication number
WO2007031788A1
WO2007031788A1 PCT/GB2006/003462 GB2006003462W WO2007031788A1 WO 2007031788 A1 WO2007031788 A1 WO 2007031788A1 GB 2006003462 W GB2006003462 W GB 2006003462W WO 2007031788 A1 WO2007031788 A1 WO 2007031788A1
Authority
WO
WIPO (PCT)
Prior art keywords
frequency
signal
phase lock
mixer
lock loop
Prior art date
Application number
PCT/GB2006/003462
Other languages
English (en)
Inventor
Dominic Thomas Parfrey Banham
Original Assignee
Radioscape Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Radioscape Limited filed Critical Radioscape Limited
Publication of WO2007031788A1 publication Critical patent/WO2007031788A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B21/00—Generation of oscillations by combining unmodulated signals of different frequencies
    • H03B21/01—Generation of oscillations by combining unmodulated signals of different frequencies by beating unmodulated signals of different frequencies
    • H03B21/02—Generation of oscillations by combining unmodulated signals of different frequencies by beating unmodulated signals of different frequencies by plural beating, i.e. for frequency synthesis ; Beating in combination with multiplication or division of frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/16—Multiple-frequency-changing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/16—Multiple-frequency-changing
    • H03D7/161—Multiple-frequency-changing all the frequency changers being connected in cascade
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/185—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using a mixer in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
    • H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/12—Indirect frequency synthesis using a mixer in the phase-locked loop

Definitions

  • the field of the invention is phase-locked loop (PLL) frequency synthesisers, and applications thereof.
  • PLL phase-locked loop
  • the smallest frequency step is determined by the comparison (or reference) frequency at which the phase detector operates.
  • the comparison (or reference) frequency at which the phase detector operates.
  • the loop bandwidth must be set significantly lower (usually by a factor of about 10) than the comparison/reference frequency. Because the loop response time varies inversely with the loop bandwidth, this means that the loop response time is large, leading to long settling times when the frequency is changed, and to increased close-in phase noise, where close-in phase noise is the noise in the phase value as the frequency in the loop approaches the new target frequency.
  • a number of methods are known which can overcome the disadvantages of conventional phase-locked loop frequency synthesisers.
  • the principal methods known which can overcome the disadvantages of conventional phase-locked loop frequency synthesisers include the use of fractional-N loops and of dkect digital synthesis (DDS).
  • fractional-N loops are known to suffer from spurious output frequencies, and DDS devices are relatively expensive and have a relatively low operating frequency range.
  • Implementations of the present invention provide a phase-locked loop frequency synthesiser that overcomes at least some of the known disadvantages of the alternatives to conventional phase-locked loop frequency synthesisers; implementations avoid the output of spurious frequencies, are relatively low cost, and provide an acceptably large operating frequency range, or provide any one or more combinations of these advantages.
  • an incoming radio frequency (RF) signal at a receiver is converted to a fixed intermediate frequency (IF).
  • IF intermediate frequency
  • the RF frequency resolution is limited by the properties of the one or more conventional phase-locked loop frequency synthesisers utilized. An implementation of die invention addresses this.
  • phase-locked loop frequency synthesisers include their use in radio transmitters /receivers, radio/TV receivers, thek use in spreading the electromagnetic noise spectrum generated by an electronic device over an increased bandwidth by varying the operating frequency of the electronic device, and their use in varying the phase and frequency of the signals derived from feedback clocks in electronic circuitry such that the signals match the reference clock of the electronic circuitry.
  • An improved phase-locked loop frequency synthesiser may replace conventional phase-locked loop frequency synthesisers in such applications.
  • An implementation of the invention provides a phase-locked loop frequency synthesiser with improved characteristics relative to conventional phase-locked loop frequency synthesisers.
  • the improved characteristics may include reduced settling times when the frequency is changed, reduced close-in phase noise, and reduced susceptibility to microphonic effects. These improved characteristics may be achieved using a comparison/reference frequency at which the phase detector in the PLL operates which is significantly higher than in conventional PLL designs.
  • the implementation requires a main PLL, which includes the phase detector. This main PLL takes as its input the comparison/reference frequency.
  • auxiliary PLL which uses as its comparison/reference frequency a frequency that differs from the comparison/reference frequency used in the main PLL by a small amount, ⁇ , which is approximately equal to the smallest frequency step required to be used in the synthesiser or some submultiple thereof.
  • the higher comparison/reference frequencies of the two phase-locked loops may lead to reduced settling times when the phase detector frequency is changed, for example, because the settling time is typically inversely proportional to the comparison frequency.
  • sum frequency generation between the two phase-locked loops may also be utilized in the overall frequency conversion process.
  • Embodiments of the invention provide systems with improved characteristics, where the improved characteristics derive from the improved characteristics of the phase-locked loop frequency synthesisers described above.
  • Such systems may include radio receivers and radio transmitters, for example, or receivers or transmitters which function in other parts of the electromagnetic spectrum, such as for optical wavelengths, which include infra-red, visible or ultra-violet wavelengths.
  • Such systems may also include those in which the electromagnetic waves are transmitted along conducting wires, or along optically transmissive cables such as fibre optic cables. More specifically, applications which utilize such systems may include frequency division multiplexing on mains cables, on telephone lines, on optical fibres, or for electromagnetic waves which propagate in air or in a vacuum.
  • Figure 1 is a phase-locked loop frequency synthesiser circuit diagram.
  • Figure 2 is a phase-locked loop frequency synthesiser circuit diagram.
  • Figure 3 is a phase-locked loop frequency synthesiser circuit diagram.
  • a frequency synthesiser includes two phase-locked loops U and 12 with high, but slightly different comparison/reference frequencies which enter the circuit via transmitting media 13 and 17, as shown in Figure 1.
  • a fine resolution in the frequency generation process is achieved through the use of a small difference between the frequencies of the two reference signals. Means are supplied for generating the comparison frequencies.
  • the two loops are the main loop 11 and the auxiliary loop 12; the main loop 11 produces the final output frequency which propagates in the transmitting medium 16.
  • elements 14 and 18 are phase detectors.
  • the frequency output of the auxiliary loop 12 is mixed at mixer 100 with the frequency output of the main loop 11 to produce the sum frequency and the difference frequency.
  • the sum frequency or the difference frequency may be removed by filtering, leaving one remaining frequency.
  • the one remaining frequency may then be used as the feedback term for the main loop.
  • the difference frequency would be used as the feedback term for the main loop. Filtering is also employed elsewhere in the circuit of Figure 1.
  • the reference frequencies for the main loop U and for the auxiliary loop 12 are Rl and R2, respectively. These enter the circuit via transmitting media 13 and 17, respectively, and are chosen such that
  • the auxiliary loop 12 has a programmable feedback divider 19 operating with a ratio N2.
  • a programmable feedback divider is an adjustable frequency changing device. It follows that the auxiliary loop generates a frequency F 311x given by
  • N2 over a range of values of the order of P.
  • F aux over a range of values of about P (P + 1) ⁇ .
  • the frequency F aux is subtracted from the output frequency F out of the main loop U to provide the main loop's feedback term.
  • the main loop 11, which has a programmable feedback divider 15 operating with a ratio Nl, will lock when its frequency F main is given by the sum of its internally generated frequency Nl P ⁇ and F aux i.e. when
  • the output frequency F out is equal to F main . It can be seen from the above that if N2 is increased by 1, and Nl is decreased by 1, F out will increase by ⁇ . It is also evident that the value of P does not affect the step size ⁇ . However, in order to achieve continuous frequency coverage, the auxiliary loop 12 should cover a frequency range of at least about P (P + 1) ⁇ , which may put practical limits on the value of P. In some embodiments of the invention, Rl and R2 may be derived from a common reference source, which may put further restrictions on practical values of P.
  • the outputs of the main loop 21 and of the auxiliary loop 22 are mixed together at mixer 200 to generate the sum frequency and the difference frequency.
  • the reference frequencies enter the circuit via transmitting media 23 and 27, elements 24 and 28 are phase detectors, and elements 25 and 29 are integer dividers. A fine resolution in the frequency generation process is achieved through the use of a small difference between the frequencies of the two reference signals. Means are supplied for generating the comparison/reference frequencies.
  • F main is Nl P ⁇ . If the sum frequency is used as the output frequency F out it follows that F out in Figure 2 in transmitting medium 26 will be given by
  • two phase-locked loops with high, but somewhat different, comparison frequencies may be used to provide high resolution tuning in a radio receiver.
  • a fine resolution in the frequency conversion process from the input signal to the output signal is achieved through the use of a small difference between the frequencies of the first and second reference signals.
  • Means are supplied for generating the comparison frequencies.
  • two integer-N phase locked loops 31 and 33 are used as local oscillators to perform two consecutive frequency conversions on an incoming RF signal, which enters the circuit via transmitting medium 30.
  • PLLl 31 has a reference frequency Ql and a divider ratio Ml.
  • PLL2 33 has frequency reference Q2 and divider ratio M2.
  • Ql and Q2 are multiples of the desired step size ⁇ such that
  • the two frequency conversions are equivalent to a single frequency conversion with an output frequency given by
  • the receiver of Figure 3 may be applied to receive electromagnetic waves within any of many regions of the electromagnetic spectrum, including regions such as those characteristic of radio waves, microwaves, infra-red radiation, visible radiation and ultra-violet radiation.
  • filtering may be employed to allow frequencies in a particular range to propagate, thereby blocking frequencies outside the said range.
  • more than one auxiliary loop may be used. This has the advantage of restricting the tuning range required of the auxiliary oscillators or of the intermediate frequencies.
  • the value of ⁇ could be selectable using a computer program, rather than being fixed by the circuitry.
  • One example of an application of this embodiment of the invention is an application in a radio receiver, where a variable value of ⁇ would enable one to scan a wide band of frequencies, or to receive broadcasts which are consistent with various different broadcasting standards.
  • the system may be used for automatic frequency control or for sample-timing adjustment in digital receiver or transmitter systems.
  • the circuitry of Figures 1, 2 or 3 may be used to provide a reference for another PLL.
  • a further embodiment of the invention consists of a transmitter of electromagnetic waves in which the apparatus of Figure 3 is employed to convert an input frequency into an output frequency for transmission, where the output frequency is different to the input frequency.
  • the first PLL 31 is taken to have a comparison frequency of 100 kHz
  • the second PLL 33 is taken to have a comparison frequency of 99 kHz. This implies that ⁇ is 1 kHz and that P is 99.
  • the incoming signal in transmitting medium 30 is taken to have a frequency S of 6.000 MHz; we wish to convert it to an IF2 value of 45.000 MHz.
  • the second LO 34 is set to 99 MHz.
  • the frequency resolution which will be achieved in implementations of the invention may be approximately equal to ⁇ , rather than being exactly equal to ⁇ , for various reasons such as but not limited to the signal dispersion which may occur during signal propagation, the quantitative measure of frequency resolution adopted, or non-ideal behaviour of the elements of the circuits.
  • the two PLLs 31 and 33 will have a bandwidth of about one tenth of their frequency i.e. about 10 kHz. This suggests a response time for each PLL of the order the reciprocal of these bandwidths i.e. of the order of 100 microseconds.
  • a conventional PLL with a phase detector comparison frequency of 1 kHz will have a bandwidth of about one tenth of 1 kHz which is about 100 Hz. This suggests a response time of the order the reciprocal of this bandwidth i.e. of the order of 10 milliseconds.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

L'invention concerne un synthétiseur de fréquence qui reçoit un signal d'entrée, mélange le signal d'entrée avec la sortie provenant d'un premier oscillateur à boucle qui inclut une première boucle à phase asservie, mélange ensuite le signal résultant avec la sortie provenant d'un second oscillateur à boucle qui inclut une seconde boucle à phase asservie, ce qui produit de ce fait une fréquence de sortie qui diffère de la fréquence d'entrée dans une certaine mesure qui peut être régulée. La régulation est obtenue du fait que chaque boucle à phase asservie inclut un dispositif ajustable de changement de fréquence destiné à changer la fréquence d'un signal à l'intérieur de chaque boucle d'un facteur ajustable. Le synthétiseur de fréquence présente un temps de réponse rapide, parmi d'autres avantages. Des applications du synthétiseur de fréquence sont décrites par exemple dans des récepteurs radio et dans des émetteurs radio. Des applications d'autres circuits synthétiseurs de fréquence présentant des avantages semblables sont également décrits.
PCT/GB2006/003462 2005-09-15 2006-09-15 Synthétiseur de fréquence avec une résolution fine WO2007031788A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0518842.0 2005-09-15
GBGB0518842.0A GB0518842D0 (en) 2005-09-15 2005-09-15 Vernier synthesiser

Publications (1)

Publication Number Publication Date
WO2007031788A1 true WO2007031788A1 (fr) 2007-03-22

Family

ID=35248830

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2006/003462 WO2007031788A1 (fr) 2005-09-15 2006-09-15 Synthétiseur de fréquence avec une résolution fine

Country Status (2)

Country Link
GB (2) GB0518842D0 (fr)
WO (1) WO2007031788A1 (fr)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4234929A (en) * 1979-09-24 1980-11-18 Harris Corporation Control device for a phase lock loop vernier frequency synthesizer
DE19708772A1 (de) * 1997-03-04 1998-06-25 Siemens Ag Verfahren und Vorrichtung zur Erzeugung von Signalfrequenzen
US6163684A (en) * 1997-08-01 2000-12-19 Microtune, Inc. Broadband frequency synthesizer
EP1085657A1 (fr) * 1999-09-17 2001-03-21 Sony United Kingdom Limited Boucle à verrouillage de phase à double boucle
US20020118308A1 (en) * 2001-02-27 2002-08-29 Ati Technologies, Inc. Integrated single and dual television tuner having improved fine tuning
US20030119466A1 (en) * 2001-12-21 2003-06-26 Goldman Stanley J. Fully integrated low noise multi-loop synthesizer with fine frequency resolution for HDD read channel and RF wireless local oscillator applications

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2099645A (en) * 1981-05-29 1982-12-08 Racal Res Ltd Frequency synthesisers
US5390346A (en) * 1994-01-21 1995-02-14 General Instrument Corporation Of Delaware Small frequency step up or down converters using large frequency step synthesizers
JPH11205137A (ja) * 1998-01-14 1999-07-30 Matsushita Electric Ind Co Ltd Ｐｌｌ周波数シンセサイザ回路
GB2402564B (en) * 2003-06-07 2006-04-05 Zarlink Semiconductor Ltd Multiple conversion tuner
JP2007522726A (ja) * 2004-01-26 2007-08-09 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ マルチバンドｏｆｄｍベースの超広帯域無線の周波数発生

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4234929A (en) * 1979-09-24 1980-11-18 Harris Corporation Control device for a phase lock loop vernier frequency synthesizer
DE19708772A1 (de) * 1997-03-04 1998-06-25 Siemens Ag Verfahren und Vorrichtung zur Erzeugung von Signalfrequenzen
US6163684A (en) * 1997-08-01 2000-12-19 Microtune, Inc. Broadband frequency synthesizer
EP1085657A1 (fr) * 1999-09-17 2001-03-21 Sony United Kingdom Limited Boucle à verrouillage de phase à double boucle
US20020118308A1 (en) * 2001-02-27 2002-08-29 Ati Technologies, Inc. Integrated single and dual television tuner having improved fine tuning
US20030119466A1 (en) * 2001-12-21 2003-06-26 Goldman Stanley J. Fully integrated low noise multi-loop synthesizer with fine frequency resolution for HDD read channel and RF wireless local oscillator applications

Also Published As

Publication number Publication date
GB0518842D0 (en) 2005-10-26
GB0618224D0 (en) 2006-10-25
GB2432061A (en) 2007-05-09

Similar Documents

Publication Publication Date Title
US7701299B2 (en) Low phase noise PLL synthesizer
US5034703A (en) Frequency synthesizer
US8704562B2 (en) Ultra low phase noise signal source
CN103490777B (zh) 低杂散频率合成器
US8242818B2 (en) Phase-locked loop frequency synthesizer
US5152005A (en) High resolution frequency synthesis
US6665523B1 (en) Receiver tuning system
US4720688A (en) Frequency synthesizer
NO302599B1 (no) Frekvenssyntetiserer samt fremgangsmåte derved
US7250823B2 (en) Direct digital synthesis (DDS) phase locked loop (PLL) frequency synthesizer and associated methods
US5831481A (en) Phase lock loop circuit having a broad loop band and small step frequency
US9628066B1 (en) Fast switching, low phase noise frequency synthesizer
US7579916B1 (en) Low noise frequency synthesizer
US6509802B2 (en) PLL-tuning system having a phase detector with a sampling frequency equal to a reference frequency
US20080258833A1 (en) Signal Generator With Directly-Extractable Dds Signal Source
US20040232996A1 (en) Phase locked loop (PLL) frequency synthesizer and method
US6519305B1 (en) Frequency converter arrangement
WO2000077936A1 (fr) Ensemble d'un systeme electronique
KR101298621B1 (ko) Fmcw 주파수 합성기 및 그것의 제어 방법
WO2007031788A1 (fr) Synthétiseur de fréquence avec une résolution fine
US6636086B2 (en) High performance microwave synthesizer using multiple-modulator fractional-N divider
US4095190A (en) Tuning system
EP0203756A2 (fr) Synthétiseurs de fréquence
EP0943180A1 (fr) Dispositif radio multicanal, systeme de radiocommunication, et synthetiseur de frequence a division fractionnelle
US6297703B1 (en) Method and apparatus for producing an offset frequency

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 06779472

Country of ref document: EP

Kind code of ref document: A1

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载