WO2007013744A1

WO2007013744A1 - Sharing multi-partitioned memory through a plurality of routes

Info

Publication number: WO2007013744A1
Application number: PCT/KR2006/002740
Authority: WO
Inventors: Jong-Sik Jeong
Original assignee: Mtekvision Co., Ltd
Priority date: 2005-07-26
Filing date: 2006-07-12
Publication date: 2007-02-01
Also published as: KR100728650B1; KR20070013620A

Abstract

A method and a device for sharing a multi-partitioned memory through a plurality of routes are disclosed. The digital processing apparatus in accordance with an embodiment of the present invention comprises: a main processor; an application processor, being controlled by the main processor and being connected to the main processor through one connection bus; and a memory, having a plurality of ports, each of which is coupled to the application processor through an independent memory bus, and being partitioned to n (a natural number) partitioned areas. With the present invention, it becomes possible to increase the speed of processing a high-quality image.

Description

[DESCRIPTION]

[Invention Title]

SHARING MULTI-PARTITIONED MEMORY THROUGH A PLURALITY

OF ROUTES

[Technical Field]

The present invention is directed to sharing of a memory (storage device), more

specifically to a method and a device for having a memory shared by a plurality of

processors in an electrical/electronic device (digital processing apparatus).

[Background Art]

As an example of electrical/electronic devices, portable terminals refer to

electronic devices that can be easily carried by making the size compact in order to

perform functions such as game and mobile communication. Portable terminals include

mobile communication terminals, personal digital assistants (PDA) and portable

multimedia players (PMP).

Among the portable terminals, the mobile communication terminal is essentially

a device designed to enable a mobile user to telecommunicate with a receiver who is

remotely located. Thanks to scientific development, however, the latest mobile

communication terminals have functions, such as camera and multimedia data playback, in addition to the basic functions, such as voice communication, short message service

and address book.

FIG. 1 shows a block diagram of a conventional mobile communication terminal

having a camera function.

Referring to FIG. 1, the mobile communication terminal 100 having a camera

function comprises a high frequency processing unit 110, an analog-to-digital converter

115, a digital-to-analog converter 120, a processing unit 125, a power supply 130, a key

input 135, a main memory 140, adisplay 145, a camera 150, an image processing unit 155

and a support memory 160.

The high frequency processing unit 110 processes a high frequency signal,

which is transmitted or received through an antenna.

The analog-to-digital converter 115 converts an analog signal, outputted from

the high frequency processing unit 110, to a digital signal and sends to the processing unit

125.

The digital-to-analog converter 120 converts a digital signal, outputted from the

processing unit 125, to an analog signal and sends to the high frequency processing unit

110.

The processing unit 125 controls the general operation of the mobile

communication terminal 100. The processing unit 125 can comprise a central processing

unit (CPU) or a micro-controller. The power supply 130 supplies electric power required for operating the mobile

communication terminal 100. The power supply 130 can be coupled to, for example, an

external power source or a battery.

The key input 135 generates key data for, for example, setting various functions

or dialing of the mobile communication terminal 100 and sends to the processing unit

125.

The main memory 140 stores an operating system and a variety of data of the

mobile communication terminal 100. The main memory 140 can be, for example, a flash

memory or an EEPROM (Electrically Erasable Programmable Read Only Memory).

The display 145 displays the operation status of the mobile communication

terminal 100, relevant information (e.g. date and time) and an external image

photographed by the camera 150.

The camera 150 photographs an external image (a photographic subject), and the

image processing unit 155 processes the external image photographed by the camera 150.

The image processing unit 155 can perform functions such as color interpolation, gamma

correction, image quality correction and JPEG encoding. The support memory 160 stores

the external image processed by the image processing unit 155. The support memory 160

can be an SRAM (Static RAM) or an SDRAM (Synchronous DRAM).

As described above, the mobile communication terminal 100 having a camera

function is equipped with a plurality of processing units (that is, a main processor and one or more application processors for performing additional functions). In other words, as

shown in FIG. 1, the processing unit 125 for controlling general functions of the mobile

communication terminal 100 and the image processing unit 155 for controlling the

camera function are included. Each processing unit is structured to be coupled with an

independent memory. The operation of each application processor can be controlled by

the main processor.

The application processor can take different forms and quantity depending on

the kinds of additional functions, with which the portable terminal is equipped. For

example, the application processor for controlling the camera function can process

functions such as JPEG encoding and JPEG decoding; the application processor for

controlling the movie file playback function can process functions such as video file (e.g.,

MPEG4, DIVX, H.264) encoding and decoding; and the application processor for

controlling the music file playback function can process functions such as audio file

encoding and decoding. The portable terminal can also comprise an application processor

for controlling games. Each of these processing units has an individual memory for

storing the processed data and/or data to be processed.

In an arrangement as this, various attempts are being made to have the memory

in each application processor shared by another application processor or the main

processor, in order to expand the storage space or improve the process efficiency.

However, the conventional memory sharing structure uses a memory having a single port, delaying the time and lacking the efficiency in processing a high-resolution,

high-performance image.

FIG. 2 is a coupling structure between a processor and a memory in accordance

with the prior art.

As shown in FIG. 2, one processor can comprise a plurality of processing units,

such as an image signal processor 210, a multimedia processor 220 and a control function

processor 230. Each of the processors is coupled parallel to a memory 240 through one

bus.

Each processor accesses the memory sequentially in accordance with the priority

or a predetermined order because a plurality of processors can not access the memory 240

at the same time. This causes each processor to prolong its processing time and makes the

processor overwork due to the amount of data.

Besides, the length of time for the image signal processor 210 occupying the

memory 240 becomes inevitably longer in proportion to the number of pixels of an image

sensor, limiting the time used by other processors for predetermined operations.

FIG. 3 is a block diagram showing a main processor and an application

processor sharing a supplementary memory coupled to the application processor, in

accordance with the prior art. In this description, it is assumed that the application

processor is a multimedia processor for controlling an image sensor 330 and for

processing multimedia data inputted from the image sensor 330. Referring to FIG. 3, the main processor 310 comprises a plurality of memory

controllers (i.e. a first memory controller 333 and a second memory controller 336). By

accessing the multimedia processor 320 through an MP (Main Processor)- AP

(Application Processor) bus in accordance with the operation of the first memory

controller 333, the main processor 310 writes data in the supplementary memory 325

coupled to the multimedia processor 320 or reads data stored in the supplementary

memory 325.

In addition, the main processor 310 writes data or reads the stored data by

accessing a main memory 315 directly coupled to the main processor 310 through an MP

(Main Processor)-MM (Main Memory) bus in accordance with the operation of the

second memory controller 336.

The multimedia processor 320 comprises an interface 342, a controller 344, a

multimedia processing unit 346, an image sealer 348, a priority control unit 353 and a

memory control unit 356.

The multimedia processor 320 is coupled to the supplementary memory 325

having one port through an AP-AM (application memory) bus. In addition, the

multimedia processor 320 can be coupled to the display 145 in order to display the

processed multimedia data.

The interface 342 communicates information between the multimedia processor

320 and the main processor 310. The multimedia processor 320 carries out an operation corresponding to a control signal, instructing a process operation, received from the main

processor 310 through the interface 342.

The controller 344 controls the operation of the multimedia processor 320 in

accordance with a program installed for the operation of the multimedia processor 320. In

other words, the operation of the multimedia processor 320 is controlled; the data needed

for executing the program is read from the supplementary memory 325; and the processed

programming result is stored in the supplementary memory 325. The controller 344 can

access the supplementary memory 325 through a system bus 350 and the memory control

unit 356. In general, the controller 344 controls the operation of the multimedia processor

320 in accordance with a control signal received from the main processor 310. The

controller 344 can be, for example, an MCU (microcontroller unit).

The multimedia processing unit 346 reads image data stored in the

supplementary memory 325 and compresses it to a predetermined format (e.g. JPEG or

MPEG4) or add an effect, hi addition, the multimedia processing unit 346 reads a

compressed file, received from the main processor 310 and stored in the supplementary

memory 325, and decodes it before displaying it on the display 145.

The image sealer 348 processes data inputted from the image sensor 330 in

accordance with the control of the controller 344 and coverts the data to predetermined

data. The image sealer 348 performs, for example, adjustment of the image size, changing

of color and softening of image through filtering. The data processed by the image sealer 348 is stored in the supplementary memory 325 through the AP-AM bus by the memory

control unit 356.

The priority control unit 353 determines the priority between a request to access

the supplementary memory 325 from the multimedia processor 320 and a request to

access the supplementary memory 325 from the main processor 310, and controls one of

the processors to access the supplementary memory 325. The priority control unit 353

also determines the priority among the requests to access the supplementary memory 325

from elements (i.e. function units) in the multimedia processor 320 and controls the

memory control unit 356. The multimedia processor 320 can access the supplementary

memory 325 when, for example, storing image data processed by the image sealer 348,

processing data stored in the supplementary memory 325 by the multimedia processing

unit 346 and storing the processed data.

The memory control unit 356 controls one of the processors to access the

supplementary memory 325 in accordance with the priority control signal from the

priority control unit 353 when the main processor 310 and the multimedia processor 320

request an access to the supplementary memory 325 at the same time. Moreover, the

memory control unit 356 controls one of the elements to access the supplementary

memory 325 in accordance with the control of the priority control unit 353 in case the

elements in the multimedia processor 320 request an access to the supplementary

memory 325 at the same time. As shown in FIG. 3, in the conventional memory sharing structure, a plurality of

processors and/or elements access a single memory through a single bus. Thus, the main

processor 310 has temporal limitation to use a memory of the supplementary processor

320.

For example, in case of playing back an MPEG file, the main processor 310 must

deliver the MPEG file, stored in the coupled main memory 315 or inputted real time, to

the multimedia processor. Since the size of an MPEG file is large, the MPEG file is first

written in the supplementary memory 325 coupled to the multimedia processor 320, and,

when necessary, a particular element (e.g. multimedia processing unit 346) of the

multimedia processor 320 reads the data and decodes the data before delivering the data

to the display 145.

As a result, in the memory sharing structure shown in FIG. 3, the bigger the size

of the data delivered between the processors is, the more restriction there is in using the

supplementary memory 325 connected to the multimedia processor 320. This is because

each element included in the multimedia processor 320 must use the AP-AM bus

connected to the supplementary memory 325 every time a process operation is

performed.

As described above, the conventional memory sharing structure had the problem

of delayed time when processing a high-performance, high-resolution image. Moreover,

there has been a loss of process efficiency in the application processor. [Disclosure]

[Technical Problem]

Therefore, in order to solve the above problems, it is an object of the present

invention to provide a method for sharing a multi-partitioned memory through a plurality

of routes and a device thereof that can minimize the loss of process efficiency of an

application processor and minimize the delay of time when processing a

high-performance, high-resolution image.

It is also an object of the present invention to provide a method for shaing a

multi-partitioned memory through a plurality of routes and a device thereof that can

maximize the efficiency of data storage and data process by allowing a plurality of

elements needing data process and data storage to use separate storage areas through

separate routes.

The present invention also aims to provide a method for sharing a

optimize the memory efficiency by allowing image data inputted from an image sensor to

be stored in a supplementary memory regardless of the operation status of a multimedia

processor.

The present invention also aims to provide a method for sharing a memory

through a plurality of routes and a device thereof that can control the loss of data by eliminating the delay in time when storing the image data inputted from the image sensor.

Another object of the present invention is to provide a method for sharing a

easily control a storage device by having an interface to the storage device connect to

only an element performing the function of a bus controller.

Another object of the present invention is to provide a method for sharing a

multi-partitioned memory through a plurality of routes and a device thereof in which the

main processor can control the application processor and communicate data with the

application processor through one bus.

It is still another object of the present invention to provide a method for sharing a

reduce the traffic in the system bus by allowing a plurality of elements to access the

supplementary memory through independent routes.

Other objects of the present invention will become apparent through the

preferred embodiments described below.

[Technical Solution]

In order to achieve the above objects, an aspect of the present invention features

an apparatus sharing a multi-partitioned memory.

The digital processing apparatus in accordance with a preferred embodiment of the present invention can comprise: a main processor; an application processor, being

controlled by the main processor and being connected to the main processor through one

connection bus; and a memory, having a plurality of ports, each of which is coupled to the

application processor through an independent memory bus, and being partitioned to n (a

natural number) partitioned areas.

The application processor can comprise: a multimedia data input unit,

processing multimedia data inputted from an input device and storing the multimedia data

in a storage area A; a multimedia data processing unit, reading and processing the

multimedia data stored by the multimedia data input unit and then storing the multimedia

data in a storage area B, displaying the multimedia data through a display, or sending the

multimedia data to the main processor; a first memory control unit, setting a route

through a memory bus such that the multimedia data processing unit accesses the storage

area A or the storage area B in accordance with a read order or a store order received from

the multimedia data processing unit; and a second memory control unit, setting a route

through another memory bus such that the multimedia data input unit accesses the storage

area A in accordance with a store order of the multimedia data input unit.

The m (a natural number between 2 and n-1, including 2) storage areas of the n

storage areas can be exclusively used by the multimedia data input unit.

In case all of the storage space of the storage area A is used, the multimedia data

input unit can send a corresponding status signal to the second memory control unit, and the second memory control unit can renew a route such that the multimedia data input

unit accesses a storage area C in accordance with the status signal.

The application processor can further comprise: a controller, controlling the

operation of the multimedia data input unit and the multimedia data processing unit; and

an access control unit, controlling the first memory control unit in order to adjust the

access priority of the main processor, multimedia data processing unit and controller.

The access control unit can control the second memory control unit such that one

of the main processor, multimedia data processing unit and controller accesses one of the

plurality of storage areas through said another memory bus in accordance with the access

priority, in case the multimedia data input unit does not output the processed multimedia

data.

The application processor can further comprise an interface, which receives

information corresponding to one from a group consisting of a control signal and data

from the main processor and sends data corresponding to the control signal.

The input device can be an image sensor. Moreover, the application processor

and the memory can be embodied in the same chip.

The digital processing apparatus in accordance with another preferred

embodiment of the present invention can comprise: a memory, having a plurality of ports;

and a processor, being coupled to the plurality of ports of the memory through each bus.

The memory can comprise 2 or more partitioned storage areas. The processor can comprise a plurality of processing units, which writes data in

the memory or reads the written data. At least one of the plurality of partitioned storage

areas can be exclusively used by a predetermined processing unit.

The processor and the memory can be embodied in the same chip.

hi order to achieve the above objects, another aspect of the present invention

features a method for sharing a memory and/or a recorded medium recording a program

for executing the method thereof.

The method in accordance with a preferred embodiment of the present invention

for having a memory shared by each element included in an application processor can

comprise the steps of: (a) a first memory control unit setting a route in accordance with a

store order of a multimedia data input unit such that the multimedia data input unit

accesses a first storage area through a first memory bus; (b) the multimedia data input unit

sending a status signal to the first memory control unit in case the multimedia data input

unit used all of the storage space of the first storage area; (c) the first memory control unit

resetting a route such that the multimedia data input unit accesses a second storage area

through the first memory bus; and (d) a second memory control unit setting a route in

accordance with a read order of a multimedia data processing unit processing data such

that the multimedia data processing unit accesses the first storage area through a second

memory bus. Each of the first memory bus and the second memory bus can couple the application processor to the memory.

The above method can further comprise the step of (e) the second memory

control unit resetting a route in accordance with a store order of the multimedia data

processing unit such that the multimedia data processing unit accesses a third storage area

through the second memory bus in order to store data processed by the multimedia data

processing unit.

The step (d) can comprise the steps of: an access control unit setting an access

priority between a controller and the multimedia data processing unit if the access control

unit receives a request to access the memory from the controller and the multimedia data

processing unit; and the second memory control unit setting a route in accordance with a

read order of the multimedia data processing unit such that the multimedia data

processing unit accesses the first storage area through the second memory bus, in case the

multimedia data processing unit has the priority.

The memory can have a plurality of ports and be partitioned to n (a natural

number) partitioned areas, which are accessible through the plurality of ports. Each port is

coupled to the application processor through an independent memory bus.

According to another preferred embodiment of the present invention, the

recorded medium tangibly embodies a program of instructions executable by a digital

processing apparatus to execute a method for having a memory shared by each element

included in an application processor. The program is readable by the digital processing apparatus. The program executes the acts of: a first memory control unit setting a route in

accordance with a store order of a multimedia data input unit such that the multimedia

data input unit accesses a first storage area through a first memory bus; the multimedia

data input unit sending a status signal to the first memory control unit in case the

multimedia data input unit used all of the storage space of the first storage area; the first

memory control unit resetting a route such that the multimedia data input unit accesses a

second storage area through the first memory bus; and a second memory control unit

setting a route in accordance with a read order of a multimedia data processing unit

processing data such that the multimedia data processing unit accesses the first storage

area through a second memory bus. Each of the first memory bus and the second memory

bus can couple the application processor to the memory.

The program can further execute the act of the second memory control unit

resetting a route in accordance with a store order of the multimedia data processing unit

such that the multimedia data processing unit accesses a third storage area through the

second memory bus in order to store data processed by the multimedia data processing

unit.

[Description of Drawings]

FIG. 1 shows a block diagram of a conventional mobile communication terminal

having a camera function; FIG. 2 shows a coupling structure between a processor and a memory in

accordance with the prior art;

FIG. 3 shows a block diagram of a main processor and an application processor

sharing a supplementary memory coupled to the application processor, in accordance

with the prior art;

FIG. 4 shows a multi-partitioned memory sharing structure in accordance with a

preferred embodiment of the present invention;

FIG. 5 shows a form of partition of a multi-partitioned memory in accordance

with a preferred embodiment of the present invention; and

FIG. 6 shows a flowchart of the operation of an application processor in

accordance with a preferred embodiment of the present invention.

[Mode for Invention]

The above objects, features and advantages will become more apparent through

the below description with reference to the accompanying drawings.

Since there can be a variety of permutations and embodiments of the present

invention, certain embodiments will be illustrated and described with reference to the

accompanying drawings. This, however, is by no means to restrict the present invention

to certain embodiments, and shall be construed as including all permutations, equivalents

and substitutes covered by the spirit and scope of the present invention. Throughout the drawings, similar elements are given similar reference numerals. Throughout the

description of the present invention, when describing a certain technology is determined

to evade the point of the present invention, the pertinent detailed description will be

omitted.

Terms such as "first" and "second" can be used in describing various elements,

but the above elements shall not be restricted to the above terms. The above terms are

used only to distinguish one element from the other. For instance, the first element can be

named the second element, and vice versa, without departing the scope of claims of the

present invention. The term "and/or" shall include the combination of a plurality of listed

items or any of the plurality of listed items.

When one element is described as being "connected" or "accessed" to another

element, it shall be construed as being connected or accessed to the other element directly

but also as possibly having another element in between. On the other hand, if one element

is described as being "directly connected" or "directly accessed" to another element, it

shall be construed that there is no other element in between.

The terms used in the description are intended to describe certain embodiments

only, and shall by no means restrict the present invention. Unless clearly used otherwise,

expressions in the singular number include a plural meaning. In the present description,

an expression such as "comprising" or "consisting of is intended to designate a

characteristic, a number, a step, an operation, an element, a part or combinations thereof, and shall not be construed to preclude any presence or possibility of one or more other

characteristics, numbers, steps, operations, elements, parts or combinations thereof.

Unless otherwise defined, all terms, including technical terms and scientific

terms, used herein have the same meaning as how they are generally understood by those

of ordinary skill in the art to which the invention pertains. Any term that is defined in a

general dictionary shall be construed to have the same meaning in the context of the

relevant art, and, unless otherwise defined explicitly, shall not be interpreted to have an

idealistic or excessively formalistic meaning.

Hereinafter, preferred embodiments will be described in detail with reference to

the accompanying drawings. Identical or corresponding elements will be given the same

reference numerals, regardless of the figure number, and any redundant description of the

identical or corresponding elements will not be repeated.

Although it is evident that the method for sharing a multi-partitioned memory in

accordance with the present invention can be equivalently applied to all types of digital

processing devices or systems (e.g. portable terminals and/or home digital appliances,

such as the mobile communication terminal, PDA, portable multimedia player (PMP),

MP3 player, digital camera, digital television, audio equipment, etc.), which has a

plurality of processors and in which a particular memory needs to be shared by a plurality

of processors or a plurality of elements included in one processor needs to share a

memory at the same time, the portable terminal will be described hereinafter for the convenience of description and understanding. Moreover, it shall be easily understood

through the below description that the present invention is not limited to a specific type of

terminal but is applicable equivalently to any terminal having a memory shared by a

plurality of processors or elements.

FIG. 4 is a block diagram showing a multi-partitioned memory sharing structure

in accordance with a preferred embodiment of the present invention, and FIG. 5 is a form

of partition of a multi-partitioned memory in accordance with a preferred embodiment of

the present invention.

In this description, it is assumed that the application processor 320 is a

multimedia processor for controlling the image sensor 330 and for processing multimedia

data (e.g. image data and/or voice data) inputted from the image sensor 330. Moreover,

the supplementary memory 430 coupled to the application processor 320 can be shared by

the main processor 310 and the elements included in the application processor 320, but

only the case of the supplementary memory 430 being shared by the elements included in

the application processor 320 will be described.

Referring to FIG. 4, the application processor 320 in accordance with the present

invention is coupled to the main processor 310 through the MP-AP bus (host interface),

and to the supplementary memory 430 having two ports through the first memory bus and

the second memory bus. The application processor 320 can also process multimedia data inputted from the image sensor 330 and store the data in the supplementary memory 430.

The multimedia data stored in the supplementary memory 430 can be processed by the

application processor 320 and displayed through the display 145.

The application processor 320 can comprise an interface 343, a controller 344, a

multimedia processing unit 346, an image sealer 348, an access control unit 410, a first

memory control unit 415 and a second memory control unit 420.

The interface 343 communicates information between the multimedia processor

320 and the main processor 310. The multimedia processor 320 carries out an operation

corresponding to a control signal, for ordering a process, received from the main

processor 310 through the interface 343.

The controller 344 controls the operation of the multimedia processor 320 in

accordance with a program built in for the operation of the multimedia processor 320.

That is, the controller 344 controls the operation of the multimedia processor 320, reads

data needed when operating the program from the supplementary memory 325 and stores

the result of the processed programming in the supplementary memory 325. The

controller 346 can be, for example, an MCU (microcontroller unit). The controller 344

can access a particular partitioned area (refer to FIG. 5) of the supplementary memory

325 through system bus 350, the first memory control unit or the second memory control

unit 420. In general, the controller 344 controls the operation of the multimedia processor

320 in accordance with a control signal received from the main processor 310. The controller 344 can be, for example, an MCU (microcontroller unit).

After accessing a particular partitioned area of the supplementary memory 325

through the first memory control unit 415 or the second memory control unit 420, the

multimedia processing unit 346 reads image data stored in the partitioned area and

compresses the data to a predetermined format (e.g. JPEG or MPEG4) or add necessary

effects to the data. The multimedia processing unit 346 can also read and decode a

compressed file, which is received from the main processor 310 and stored in the

supplementary memory 325, and display on the display 145. The multimedia processing

unit 346 can also store the processed data in a storage area of the supplementary memory

325.

The image sealer 349 processes data inputted from the image sensor 330 in

accordance with the control of the controller 344 to convert it to a predetermined data.

The image sealer 349 can, for example, generate a softened image through size

adjustment, color change and filtering of the image. The data processed by the image

sealer 349 can be stored in a particular storage area of the supplementary memory 325

through the second memory bus by the second memory control unit 420.

The image sealer 348 of the present invention is merely one embodiment of an

element storing multimedia data in the supplementary memory 325, and it shall be

evident that the present invention can be widely applied to any multimedia data input unit

that needs to store multimedia data (e.g. image data and/or voice data) real time in the supplementary memory 325.

Similarly, the multimedia processing unit 346, illustrated in FIG. 4, is merely

one embodiment of an element processing multimedia data stored in the supplementary

memory 325, and it shall be evident that the present invention can be widely applied to

any multimedia data processing unit that processes multimedia data stored in the

supplementary memory 325 and stores the data in supplementary memory 325 again,

displays the data through the display 145 or sends the data to the main processor 310.

The access control unit 410 determines the priority between a request to access

the supplementary memory 325 from the multimedia processor 320 and a request to

access the supplementary memory 325 from the main processor 310. Based on the

determination of the access control unit 410, either the multimedia processor 320 or the

main processor 310 is controlled to access the supplementary memory 325. Moreover,

when different elements (i.e. function units) in the multimedia processor 320 request to

access the supplementary memory 325, the access control unit 410 determines the priority

of each of these elements and controls the first and second memory control units 415 and

420. The access control unit 410, however, may exclude multimedia data inputted from

the image sealer 348 when determining the priority, that is, the multimedia data inputted

from the image sealer 348 can be set to have the priority. In other words, the second

memory control unit 420 can control the multimedia data inputted from the image sealer

348 and have the multimedia data stored real time in a particular partitioned area of the supplementary memory 325 through the second memory bus.

The first memory control unit 415 controls one of the processors to access the

supplementary memory 325 through the first memory bus in accordance with the priority

control signal from the access control unit 410 when the main processor 310 and the

multimedia processor 320 request an access to the supplementary memory 325 at the

same time. Moreover, the first memory control unit 415 controls one of the elements to

access the supplementary memory 325 through the first memory bus in accordance with

the control of the access control unit 410 when different elements (except for the image

sealer 348) in the multimedia processor 320 request an access to the supplementary

memory 325 at the same time.

In case multimedia data (e.g. image data and/or voice data) is inputted from the

image sealer 348, the second memory control unit 420, controlled by the access control

unit 410, stores the data in a particular partitioned area of the supplementary memory 325

through the second memory bus. If no data is inputted from the image sealer 348, the

second memory control unit 420, controlled by the access control unit 410, allows another

element or the main processor 310 to access the supplementary memory 325 through the

second memory bus.

The supplementary memory 325, coupled to the application processor 320

through two buses, has two access ports, and its storage area is partitioned to n (a natural

number) storage areas. As illustrated in FIG. 5, the supplementary memory 325 has one memory core

inside, and any of the first storage area, second storage area or third storage area can be

accessed through two access ports. The first storage area can be set to be exclusively used

by the controller 344 and/or the multimedia processing unit 346, and the second storage

area and the third storage area can be set as a dedicated area for storing multimedia data

inputted from the image sealer 348. Although FIG. 5 shows a case of partitions of 3, for

the sake of convenience, it should be evident that the number of partitions in the storage

area can vary based on the convenience.

In case the main processor 310 and/or a particular element of the application

processor 320 attempts to write data in A, a storage area, the main processor 310 and/or

the particular element sends a writing order (i.e. address information (Addr_A: an address

signal of storage area A), data to write (Data A), control signals (e.g. WE A (Write

Enable) for ordering data to be written in storage area A, a chip selection signal for

storage area A (CS A: Chip Select _ A) and a clock (CLK A))) for writing data to the

supplementary memory 325. Likewise, in case the main processor 310 and/or a particular

element of the application processor 320 attempts to read data in B, a storage area, the

main processor 310 and/or the particular element sends a reading order (i.e. address

information (Addr B: an address signal of storage area B), data to write (Data B), control

signals (e.g. OE B (Output Enable) for ordering data to be read from storage area B, a

chip selection signal for storage area B (CS B: Chip Select _ B) and a clock (CLKJB))) for writing data to the supplementary memory 325. The above information for storing

and/or data can be provided to the first memory control unit 415 and/or the second

memory control unit 420.

For instance, if the image sealer 348 only performs the storage operation of

multimedia data, only a storage order (e.g. WE_A) for storing the data will be sent to the

second memory control unit 420. However, since the multimedia processing unit 346 can

selectively read or store data as necessary, the read order or store order can be sent to the

first memory control unit 415 or the second memory control unit 420. A request by

elements other than the image sealer 348 through the second memory control unit 420 can

be restricted to a period during which the image sealer 348 is not occupying the second

memory bus.

As described above, a parallel process by a plurality of elements is possible with

the method for sharing a multi-partitioned memory in accordance with the present

invention, by storing multimedia data inputted from the image sensor 330 in the

supplementary memory 325 real time through one of two access ports, and requesting an

access by another element or the main processor 310 through the other of the two access

ports. While the size of the image sensor 330 has been 640x480 pixels, it is typically

1280x1024 pixels at present and is expected to increase to 1920x1200 pixels or

2560x2048 pixels. With this increase, the size of the image data is also expected to

increase. The present invention can solve the problem of prolonged time taken to store data resulted from this increase.

FIG. 6 is a flowchart showing the operation of an application processor in

accordance with a preferred embodiment of the present invention.

In describing the operation of the application processor and the method for

sharing a multi-partitioned memory, the internal structure of a shared memory shown in

FIG. 5 will be referenced. It will be assumed that the first storage area is a dedicated area

for the controller 344 and/or the multimedia processing unit 346 while the second and

third storage areas are dedicated for the image sealer 348. As described earlier, the name

and number of the storage area will not be restricted to what is described here.

Referring to FIG. 6, the image sealer, in step 610, stores multimedia data,

inputted real time from the image sensor 330, in the second storage area. The access

control unit 410 controls the route such that the multimedia data outputted from the image

sealer 348 can be stored in the second storage area through the second memory control

unit 420 and the second memory bus. The multimedia data inputted to the image sealer

348 and the multimedia data outputted from the image sealer 348 can have different

characteristics.

In step 615, the image sealer 348 determines whether the multimedia data is

completely stored in the second storage area. If there is storage space remaining in the

second storage area to store multimedia data, step 610 is repeated. However, if the storage space in the second storage area is completely occupied

by the multimedia data, step 620 is performed. In step 620, the image sealer 348

terminates access to the second storage area. That is, the image sealer 348, which used up

the storage space of the second storage area, sends a status signal (e.g. information that

the multimedia data is completely stored, information that the storage space of the storage

area is used up or a request to access another storage area) to the second memory control

unit 420 through the system bus 350. The second memory control unit 420 controls the

image sealer 348 to access the third storage area by making reference to the received

status signal. The image sealer 348 can send the status signal to the access control unit

410, which can order the second memory control unit 420 to change the access status of

the image sealer 348.

In step 635, the image sealer 348 stores the multimedia data, inputted real time

from the image sensor 330, in the accessed third storage area. The access control unit 410

controls the route such that the multimedia data outputted from the image sealer 348 is

stored in the third storage area through the second memory control unit 420 and the

second memory bus. Steps following step 635 may be performed only if the data that the

image sealer 348 is to store in the supplementary memory 325 is bigger than the second

storage area, the multimedia data is continuously received real time from the image

sensor 330, or the image sealer stores data in the second storage area and terminates the

access and then re-accesses the third storage area to store new data. In step 640, the image sealer 348 determines whether the multimedia data is

completely stored in the third storage area. If there is space left for storing multimedia

data in the third storage area, step 635 is repeated.

However, if the storage space in the third storage area is completely occupied by

the multimedia data, step 645 is performed. In step 645, the image sealer 348 terminates

access to the third storage area. That is, the image sealer 348, which used up the storage

space of the third storage area, sends a status signal (e.g. information that the multimedia

data is completely stored, information that the storage space of the storage area is used up

or a request to access another storage area) to the second memory control unit 420

through the system bus 350. The second memory control unit 420 controls the image

sealer 348 to access another storage area by making reference to the received status signal.

The image sealer 348 can send the status signal to the access control unit 410, which can

order the second memory control unit 420 to change the access status of the image sealer

348. If the image sealer 348 is designated to store multimedia data in the second and third

storage areas only, the second memory control unit 420 will make the image sealer 348

access the second storage area again after step 645. In this case, as described below, if the

multimedia processing unit 346 is still accessed to the second storage area and is reading

the stored data, the image sealer 348 may be restricted from storing data in the second

storage area until the data reading is completed by the multimedia processing unit 346.

Referring to step 620 again, the image sealer 348 sends a status signal for terminating the access to the second storage area to the second memory control unit 420

and/or the access control unit 410, which then sends the status signal to the controller 344

and/or the multimedia processing unit 346.

In step 625, the multimedia processing unit 346 (or the controller 344,

hereinafter) sends to the access control unit 410 and/or the first memory control unit 415

a request to access (may include a read order) the second storage area, and the first

memory control unit 415 controls the multimedia processing unit 346 to access the first

storage area through the first memory bus in accordance with a priority control signal

received from the access control unit 410. The multimedia processing unit 346 reads the

multimedia data stored in the second storage area and carries out necessary processes, and

then either stores the result data in the first storage area or sends the result data to the main

processor 310 through the MP-AP bus, in step 630. It should be also evident that the

processed data can be displayed through the display 145.

Steps 625-630 are carried out for a separate storage area parallel to steps

635-645. Hence, each element does not have to stand by until the operation of another

element is completed in order to use the shared memory.

Likewise, in step 645, the multimedia processing unit 346 sends to the access

control unit 410 and/or the first memory control unit 415 a request to access the third

storage area, and the first memory control unit 415 controls the multimedia processing

unit 346 to access the third storage area. The multimedia processing unit 346 then reads the multimedia data stored in the third storage area and carries out necessary processes,

and then either stores the result data in the first storage area or sends the result data to the

main processor 310 through the MP-AP bus, in step 650. It should be also evident that the

processed data can be displayed through the display 145.

So far, the case of the multimedia processor 320 being coupled to the

supplementary memory 430 through a plurality of buses has been described. It should be

evident, however, that the same technical idea can be applied without restriction to all

types of processors, having a plurality of processing units that read data written in the

coupled memory or write data in the coupled memory, or allowing the memory coupled

by another processor to be shared.

The drawings and detailed description are only examples of the present

invention, serve only for describing the present invention and by no means limit or

restrict the spirit and scope of the present invention. Thus, any person of ordinary skill in

the art shall understand that a large number of permutations and other equivalent

embodiments are possible. The true scope of the present invention must be defined only

by the spirit of the appended claims.

[Industrial Applicability]

As described above, the present invention can minimize the loss of process efficiency of an application processor and minimize the delay of time when processing a

high-performance, high-resolution image.

The present invention can also maximize the efficiency of data storage and data

process by allowing a plurality of elements needing data process and data storage to use

separate storage areas through separate routes.

The present invention also can optimize the memory efficiency by allowing

image data inputted from an image sensor to be stored in a supplementary memory

regardless of the operation status of a multimedia processor.

The present invention also can control the loss of data by eliminating the delay in

time when storing the image data inputted from the image sensor.

Moreover, the present invention can easily control a storage device by having an

interface to the storage device connect to only an element performing the function of a

bus controller.

Moreover, with the present invention, the main processor can control the

application processor and communicate data with the application processor through one

bus.

Furthermore, the present invention can reduce the traffic in the system bus by

allowing a plurality of elements to access the supplementary memory through

independent routes.

Claims

[CLAIMS]

[Claim 1]

A digital processing apparatus comprising:

a main processor;

an application processor, being controlled by the main processor and being

connected to the main processor through one connection bus; and

a memory, having a plurality of ports and being partitioned to n (a natural

number) partitioned areas, each port being coupled to the application processor through

an independent memory bus.

[Claim 2]

The digital processing apparatus of claim 1, wherein the application processor

comprises:

a multimedia data input unit, processing multimedia data inputted from an input

device and storing the multimedia data in a storage area A;

a multimedia data processing unit, reading and processing the multimedia data

stored by the multimedia data input unit and then storing the multimedia data in a storage

area B, displaying the multimedia data through a display, or sending the multimedia data

to the main processor;

a first memory control unit, setting a route through a memory bus such that the multimedia data processing unit accesses the storage area A or the storage area B in

accordance with a read order or a store order received from the multimedia data

processing unit; and

a second memory control unit, setting a route through another memory bus such

that the multimedia data input unit accesses the storage area A in accordance with a store

order of the multimedia data input unit.

[Claim 3]

The digital processing apparatus of claim 2, wherein m (a natural number

between 2 and n-1, including 2) storage areas of the n storage areas are exclusively used

by the multimedia data input unit.

[Claim 4]

The digital processing apparatus of claim 2, wherein:

input unit sends a corresponding status signal to the second memory control unit; and

the second memory control unit renews a route such that the multimedia data

input unit accesses a storage area C in accordance with the status signal.

[Claim 5] The digital processing apparatus of claim 2, wherein the application processor

further comprises:

a controller, controlling the operation of the multimedia data input unit and the

multimedia data processing unit; and

an access control unit, controlling the first memory control unit in order to adjust

the access priority of the main processor, multimedia data processing unit and controller.

[Claim 6]

The digital processing apparatus of claim 5, wherein the access control unit

controls the second memory control unit such that one of the main processor, multimedia

data processing unit and controller accesses one of the plurality of storage areas through

said another memory bus in accordance with the access priority, in case the multimedia

data input unit does not output the processed multimedia data.

[Claim 7]

The digital processing apparatus of claim 2, wherein the application processor

further comprises an interface, the interface receiving, from the main processor,

information corresponding to one from a group consisting of a control signal and data and

sending data corresponding to the control signal.

[Claim 8]

The digital processing apparatus of claim 2, wherein the input device is an image

sensor.

[Claim 9]

The digital processing apparatus of claim 1, wherein the application processor

and the memory are embodied in the same chip.

[Claim 10]

A digital processing apparatus comprising:

a memory, having a plurality of ports; and

a processor, being coupled to the plurality of ports of the memory through each

bus.

[Claim 11 ]

The digital processing apparatus of claim 10, wherein the memory comprises 2

or more partitioned storage areas.

[Claim 12]

The digital processing apparatus of claim 11 , wherein the processor comprises a plurality of processing units, the processing units writing data in the memory or reading

the written data.

[Claim 13]

The digital processing apparatus of claim 12, wherein at least one of the plurality

of partitioned storage areas is exclusively used by a predetermined processing unit.

[Claim 14]

The digital processing apparatus of claim 10, wherein the processor and the

memory are embodied in the same chip.

[Claim 15]

A method for having a memory shared by each element included in an

application processor, the method comprising the steps of:

(a) a first memory control unit setting a route in accordance with a store order of

a multimedia data input unit such that the multimedia data input unit accesses a first

storage area through a first memory bus;

(b) the multimedia data input unit sending a status signal to the first memory

control unit in case the multimedia data input unit used all of the storage space of the first

storage area; (c) the first memory control unit resetting a route such that the multimedia data

input unit accesses a second storage area through the first memory bus; and

(d) a second memory control unit setting a route in accordance with a read order

of a multimedia data processing unit processing data such that the multimedia data

processing unit accesses the first storage area through a second memory bus,

wherein each of the first memory bus and the second memory bus couples the

application processor to the memory.

[Claim 16]

The method of claim 15, further comprising the step of (e) the second memory

processing unit.

[Claim 17]

The method of claim 15, wherein the step (d) comprises the steps of:

an access control unit setting an access priority between a controller and the

multimedia data processing unit if the access control unit receives a request to access the

memory from the controller and the multimedia data processing unit; and the second memory control unit setting a route in accordance with a read order of

the multimedia data processing unit such that the multimedia data processing unit

accesses the first storage area through the second memory bus, in case the multimedia

data processing unit has the priority.

[Claim 18]

The method of claim 15, wherein the memory has a plurality of ports and being

partitioned to n (a natural number) partitioned areas, each port being coupled to the

application processor through an independent memory bus, the partitioned areas being

accessible through the plurality of ports.

[Claim 19]

A recorded medium tangibly embodying a program of instructions executable by

a digital processing apparatus to execute a method for having a memory shared by each

element included in an application processor, the program readable by the digital

processing apparatus, the program executing the acts of:

a first memory control unit setting a route in accordance with a store order of a

multimedia data input unit such that the multimedia data input unit accesses a first storage

area through a first memory bus;

the multimedia data input unit sending a status signal to the first memory control unit in case the multimedia data input unit used all of the storage space of the first storage

area;

the first memory control unit resetting a route such that the multimedia data

input unit accesses a second storage area through the first memory bus; and

a second memory control unit setting a route in accordance with a read order of a

multimedia data processing unit processing data such that the multimedia data processing

unit accesses the first storage area through a second memory bus,

wherein each of the first memory bus and the second memory bus couples the

application processor to the memory.

[Claim 20]

The recorded medium of claim 19, further executing the act of the second

memory control unit resetting a route in accordance with a store order of the multimedia

data processing unit such that the multimedia data processing unit accesses a third storage

area through the second memory bus in order to store data processed by the multimedia

data processing unit.