WO2007004658A1 - Carte de circuit imprimé - Google Patents
Carte de circuit imprimé Download PDFInfo
- Publication number
- WO2007004658A1 WO2007004658A1 PCT/JP2006/313343 JP2006313343W WO2007004658A1 WO 2007004658 A1 WO2007004658 A1 WO 2007004658A1 JP 2006313343 W JP2006313343 W JP 2006313343W WO 2007004658 A1 WO2007004658 A1 WO 2007004658A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- solder
- diameter
- wiring board
- printed wiring
- opening
- Prior art date
Links
- 229910000679 solder Inorganic materials 0.000 claims abstract description 411
- 239000004020 conductor Substances 0.000 claims abstract description 82
- 239000010410 layer Substances 0.000 claims description 132
- 238000009413 insulation Methods 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 21
- 230000003746 surface roughness Effects 0.000 claims description 16
- 239000011347 resin Substances 0.000 claims description 15
- 229920005989 resin Polymers 0.000 claims description 15
- 239000011229 interlayer Substances 0.000 claims description 13
- 230000008569 process Effects 0.000 claims description 8
- 238000007747 plating Methods 0.000 claims description 7
- 235000011962 puddings Nutrition 0.000 claims description 7
- 238000007788 roughening Methods 0.000 claims description 6
- 238000005476 soldering Methods 0.000 claims description 3
- 238000007789 sealing Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 14
- 238000012360 testing method Methods 0.000 description 12
- 239000007921 spray Substances 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 238000007639 printing Methods 0.000 description 10
- 230000008859 change Effects 0.000 description 8
- 239000000758 substrate Substances 0.000 description 8
- 238000011161 development Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000005259 measurement Methods 0.000 description 7
- 230000002950 deficient Effects 0.000 description 6
- 230000004907 flux Effects 0.000 description 6
- 101100269850 Caenorhabditis elegans mask-1 gene Proteins 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical compound [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
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- 238000005452 bending Methods 0.000 description 3
- 239000012141 concentrate Substances 0.000 description 3
- 238000001514 detection method Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- WZFUQSJFWNHZHM-UHFFFAOYSA-N 2-[4-[2-(2,3-dihydro-1H-inden-2-ylamino)pyrimidin-5-yl]piperazin-1-yl]-1-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)ethanone Chemical compound C1C(CC2=CC=CC=C12)NC1=NC=C(C=N1)N1CCN(CC1)CC(=O)N1CC2=C(CC1)NN=N2 WZFUQSJFWNHZHM-UHFFFAOYSA-N 0.000 description 2
- KDCGOANMDULRCW-UHFFFAOYSA-N 7H-purine Chemical compound N1=CNC2=NC=NC2=C1 KDCGOANMDULRCW-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910000029 sodium carbonate Inorganic materials 0.000 description 2
- OHVLMTFVQDZYHP-UHFFFAOYSA-N 1-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)-2-[4-[2-[[3-(trifluoromethoxy)phenyl]methylamino]pyrimidin-5-yl]piperazin-1-yl]ethanone Chemical compound N1N=NC=2CN(CCC=21)C(CN1CCN(CC1)C=1C=NC(=NC=1)NCC1=CC(=CC=C1)OC(F)(F)F)=O OHVLMTFVQDZYHP-UHFFFAOYSA-N 0.000 description 1
- YIWGJFPJRAEKMK-UHFFFAOYSA-N 1-(2H-benzotriazol-5-yl)-3-methyl-8-[2-[[3-(trifluoromethoxy)phenyl]methylamino]pyrimidine-5-carbonyl]-1,3,8-triazaspiro[4.5]decane-2,4-dione Chemical compound CN1C(=O)N(c2ccc3n[nH]nc3c2)C2(CCN(CC2)C(=O)c2cnc(NCc3cccc(OC(F)(F)F)c3)nc2)C1=O YIWGJFPJRAEKMK-UHFFFAOYSA-N 0.000 description 1
- HMUNWXXNJPVALC-UHFFFAOYSA-N 1-[4-[2-(2,3-dihydro-1H-inden-2-ylamino)pyrimidin-5-yl]piperazin-1-yl]-2-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)ethanone Chemical compound C1C(CC2=CC=CC=C12)NC1=NC=C(C=N1)N1CCN(CC1)C(CN1CC2=C(CC1)NN=N2)=O HMUNWXXNJPVALC-UHFFFAOYSA-N 0.000 description 1
- VZSRBBMJRBPUNF-UHFFFAOYSA-N 2-(2,3-dihydro-1H-inden-2-ylamino)-N-[3-oxo-3-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)propyl]pyrimidine-5-carboxamide Chemical compound C1C(CC2=CC=CC=C12)NC1=NC=C(C=N1)C(=O)NCCC(N1CC2=C(CC1)NN=N2)=O VZSRBBMJRBPUNF-UHFFFAOYSA-N 0.000 description 1
- LDXJRKWFNNFDSA-UHFFFAOYSA-N 2-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)-1-[4-[2-[[3-(trifluoromethoxy)phenyl]methylamino]pyrimidin-5-yl]piperazin-1-yl]ethanone Chemical compound C1CN(CC2=NNN=C21)CC(=O)N3CCN(CC3)C4=CN=C(N=C4)NCC5=CC(=CC=C5)OC(F)(F)F LDXJRKWFNNFDSA-UHFFFAOYSA-N 0.000 description 1
- IHCCLXNEEPMSIO-UHFFFAOYSA-N 2-[4-[2-(2,3-dihydro-1H-inden-2-ylamino)pyrimidin-5-yl]piperidin-1-yl]-1-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)ethanone Chemical compound C1C(CC2=CC=CC=C12)NC1=NC=C(C=N1)C1CCN(CC1)CC(=O)N1CC2=C(CC1)NN=N2 IHCCLXNEEPMSIO-UHFFFAOYSA-N 0.000 description 1
- YLZOPXRUQYQQID-UHFFFAOYSA-N 3-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)-1-[4-[2-[[3-(trifluoromethoxy)phenyl]methylamino]pyrimidin-5-yl]piperazin-1-yl]propan-1-one Chemical compound N1N=NC=2CN(CCC=21)CCC(=O)N1CCN(CC1)C=1C=NC(=NC=1)NCC1=CC(=CC=C1)OC(F)(F)F YLZOPXRUQYQQID-UHFFFAOYSA-N 0.000 description 1
- DEXFNLNNUZKHNO-UHFFFAOYSA-N 6-[3-[4-[2-(2,3-dihydro-1H-inden-2-ylamino)pyrimidin-5-yl]piperidin-1-yl]-3-oxopropyl]-3H-1,3-benzoxazol-2-one Chemical compound C1C(CC2=CC=CC=C12)NC1=NC=C(C=N1)C1CCN(CC1)C(CCC1=CC2=C(NC(O2)=O)C=C1)=O DEXFNLNNUZKHNO-UHFFFAOYSA-N 0.000 description 1
- RSWGJHLUYNHPMX-UHFFFAOYSA-N Abietic-Saeure Natural products C12CCC(C(C)C)=CC2=CCC2C1(C)CCCC2(C)C(O)=O RSWGJHLUYNHPMX-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- NIPNSKYNPDTRPC-UHFFFAOYSA-N N-[2-oxo-2-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)ethyl]-2-[[3-(trifluoromethoxy)phenyl]methylamino]pyrimidine-5-carboxamide Chemical compound O=C(CNC(=O)C=1C=NC(=NC=1)NCC1=CC(=CC=C1)OC(F)(F)F)N1CC2=C(CC1)NN=N2 NIPNSKYNPDTRPC-UHFFFAOYSA-N 0.000 description 1
- AFCARXCZXQIEQB-UHFFFAOYSA-N N-[3-oxo-3-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-yl)propyl]-2-[[3-(trifluoromethoxy)phenyl]methylamino]pyrimidine-5-carboxamide Chemical compound O=C(CCNC(=O)C=1C=NC(=NC=1)NCC1=CC(=CC=C1)OC(F)(F)F)N1CC2=C(CC1)NN=N2 AFCARXCZXQIEQB-UHFFFAOYSA-N 0.000 description 1
- 244000089486 Phragmites australis subsp australis Species 0.000 description 1
- 235000014676 Phragmites communis Nutrition 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- KHPCPRHQVVSZAH-HUOMCSJISA-N Rosin Natural products O(C/C=C/c1ccccc1)[C@H]1[C@H](O)[C@@H](O)[C@@H](O)[C@@H](CO)O1 KHPCPRHQVVSZAH-HUOMCSJISA-N 0.000 description 1
- 229910020816 Sn Pb Inorganic materials 0.000 description 1
- FHKPLLOSJHHKNU-INIZCTEOSA-N [(3S)-3-[8-(1-ethyl-5-methylpyrazol-4-yl)-9-methylpurin-6-yl]oxypyrrolidin-1-yl]-(oxan-4-yl)methanone Chemical compound C(C)N1N=CC(=C1C)C=1N(C2=NC=NC(=C2N=1)O[C@@H]1CN(CC1)C(=O)C1CCOCC1)C FHKPLLOSJHHKNU-INIZCTEOSA-N 0.000 description 1
- JAWMENYCRQKKJY-UHFFFAOYSA-N [3-(2,4,6,7-tetrahydrotriazolo[4,5-c]pyridin-5-ylmethyl)-1-oxa-2,8-diazaspiro[4.5]dec-2-en-8-yl]-[2-[[3-(trifluoromethoxy)phenyl]methylamino]pyrimidin-5-yl]methanone Chemical compound N1N=NC=2CN(CCC=21)CC1=NOC2(C1)CCN(CC2)C(=O)C=1C=NC(=NC=1)NCC1=CC(=CC=C1)OC(F)(F)F JAWMENYCRQKKJY-UHFFFAOYSA-N 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000036541 health Effects 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000012286 potassium permanganate Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000011734 sodium Substances 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 150000003457 sulfones Chemical class 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- KHPCPRHQVVSZAH-UHFFFAOYSA-N trans-cinnamyl beta-D-glucopyranoside Natural products OC1C(O)C(O)C(CO)OC1OCC=CC1=CC=CC=C1 KHPCPRHQVVSZAH-UHFFFAOYSA-N 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K3/00—Tools, devices, or special appurtenances for soldering, e.g. brazing, or unsoldering, not specially adapted for particular methods
- B23K3/06—Solder feeding devices; Solder melting pans
- B23K3/0607—Solder feeding devices
- B23K3/0623—Solder feeding devices for shaped solder piece feeding, e.g. preforms, bumps, balls, pellets, droplets
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2101/00—Articles made by soldering, welding or cutting
- B23K2101/36—Electric or electronic devices
- B23K2101/42—Printed circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/8121—Applying energy for connecting using a reflow oven
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0102—Calcium [Ca]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0191—Dielectric layers wherein the thickness of the dielectric plays an important role
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/099—Coating over pads, e.g. solder resist partly over pads
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
- H05K2203/041—Solder preforms in the shape of solder balls
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0548—Masks
- H05K2203/0557—Non-printed masks
Definitions
- the present invention relates to a printed wiring board for mounting electronic components such as capacitors and ICs on a surface layer, and more particularly to a printed wiring board adapted to narrow pitch of a solder bump for mounting electronic components.
- solder bumps are applied to a semiconductor element mounting pad (hereinafter simply referred to as a “conductor pad”) formed on the printed wiring board. Is formed. Part of the conductor pad is covered with a solder resist layer, and only the center part of the conductor pad is exposed.
- a solder printing such as a metal mask or a plastic mask is performed on the printed wiring board. Layered masks (with printing openings corresponding to the conductor pads formed on the printed circuit board), and alignment marks formed on the printed circuit board and the mask for printing — Align with the camera.
- solder paste is printed on the conductor pads and the printing mask is removed from the printed wiring board
- the printed wiring board is set in a reflow device and reflow processing is performed, whereby solder is applied to the conductive pads.
- Bumps are formed (see Japanese Patent Application Laid-Open No. 11-1-104009).
- the above-described prior art has the following problems.
- the solder bump since the solder bump has a semicircular shape with the conductor pad surface as the bottom surface, the gap between the side wall of the opening provided in the solder resist layer and the solder bump is provided. It means that there will be a gap. If there is such a gap, it is easy for flux residue and cleaning liquid residue to remain in the gap.
- Insulation reliability is reduced in printed wiring boards with a diameter of 2 0 0 ⁇ m or less.
- a residue causes a decrease in adhesion, peeling between the solder resist and the underfill is likely to occur, resulting in a decrease in connection reliability.
- it becomes difficult to fill the underfill so if you try to install a large IC chip, voids will easily enter the underfill material, and the connection reliability and insulation reliability will be reduced.
- the object of the present invention is to solve the above-mentioned problems of the prior art, and is excellent in connection reliability and insulation reliability even in a sandwich pitch structure in which the pitch of the conductor pad is 2 OO ⁇ m or less. Propose a printed wiring board. Disclosure of the invention
- solder bump the solder bump diameter (hereinafter referred to as “solder bump”) provided on the conductor pad exposed from the opening provided in the solder resist layer.
- the ratio between the diameter J) and the opening diameter of the opening is within a predetermined range, the connection reliability between the solder bump and the electronic component such as an IC chip and the insulation reliability can be improved.
- a solder resist layer is provided on the surface of a wiring board on which a conductor circuit is formed, and a part of the conductor circuit exposed from the opening provided in the solder resist ⁇ layer is mounted on an electronic component.
- the printed wiring board which is formed as a conductor pad and formed with solder bumps on the conductor pad,
- the conductor pads are arranged at a pitch of 200 im or less,
- a printed wiring board characterized in that a ratio (W / D) of the solder bump diameter and the opening diameter D of the opening provided in the solder resist layer is in the range of 1.05 to 1.7. is there.
- the present invention also provides
- a solder resist layer is provided on the surface of the wiring board on which the conductor circuit is formed, and a part of the conductor circuit exposed from the opening provided in the solder resist layer is mounted on the electronic component.
- a solder bump is formed on the conductor pad, an electronic component is mounted via the solder bump, and a resin seal is formed between the electronic component and the solder resist layer by an underfill.
- the conductor pads are arranged at a pitch of 200 m or less
- the printed wiring board characterized in that a ratio (W / D) of the solder bump diameter W and the opening diameter D of the opening provided in the solder resist layer is in the range of 1.05 to 1.7. It is.
- the ratio (WZD) between the solder bump diameter W and the opening diameter D of the opening provided in the solder resist layer is preferably in the range of 1.05 to 1.5.
- the opening provided in the solder resist layer is preferably formed in a taper shape in which the opening diameter D 1 on the top surface is larger than the opening diameter D 2 on the bottom surface.
- the surface of the solder resist layer can be flattened at least in the electronic component mounting region, and the flattened surface has a maximum surface roughness of 0.8 to 3.0 m. Is desirable.
- the surface of the solder resist layer that has been flattened can be further roughened, and the surface of the solder resist layer that has been roughened is the maximum of the flattened surface. It is desirable to be smaller than the surface roughness and arithmetic mean roughness (Ra) to be 0.2 to 0.5 m.
- the conductor pad defined as a part of the conductor circuit exposed from the opening provided in the solder resist layer is within the opening provided in the interlayer resin insulation layer where the plated conductor is located in the outermost layer. Formed in the form of a filled via that is completely filled, and the amount of irregularities on the surface of the filled via exposed from the surface of the interlayer resin insulation layer is equal to the thickness of the conductor circuit formed on the interlayer resin insulation layer. + 5 / im is desirable.
- the “conductor pad” is defined as a part of the conductor circuit exposed from the opening provided in the solder resist layer, and the conductor circuit is, for example, in the form of a connection pad or Can be formed in the form of via holes (including filled vias in which the plating conductor is completely filled in the opening provided in the resin insulation layer) and in the form of conductor circuits connected to the via holes and via holes. Is defined as a part of a conductor circuit including connection pads and via holes.
- the “solder bump diameter J” is the maximum value of the diameter of the circle or the major axis of the ellipse that appears when the solder bump protruding from the surface of the solder resist layer is cut in a horizontal section. Means.
- the “aperture diameter (D)” of the opening provided in the solder resist layer means the “diameter J” of the opening when the opening sidewall does not have a tapered shape. In the case of a taper shape, it means the diameter of the opening that appears on the surface of the solder resist layer (the diameter of the upper part of the opening).
- the height of the solder resist layer on the conductor pad or the conductor circuit and the height of the solder resist layer in the adjacent conductor pad non-formation part or conductor circuit non-formation part It means the maximum value among the differences X1, X2, X3, X4, X5.
- arithmetic mean roughness means the arithmetic mean roughness (Ra) defined in JIS B0601.
- the side wall of the opening provided in the solder resist ridge layer into a taper shape, the shape of the solder bump does not change extremely at the periphery of the opening, so that stress is less likely to concentrate. As a result, connection reliability is improved.
- the volume of the solder resist layer can be increased in areas where stress is high, and bending that stress is concentrated Since the portion is eliminated, the heat cycle resistance of the solder resist layer is improved.
- the adhesion between the surface of the solder resist layer and the underfill can be improved. it can.
- the underfill has better wettability, and it is possible to fill the underfill even in narrow areas of the bag path such as the boundary between the solder bump and the solder resist layer. Improves.
- the conductive pad is formed in the form of a filled via, and the unevenness of the filled via surface exposed from the surface of the outermost interlayer resin insulation layer is reduced by 15% relative to the thickness of the conductor circuit formed on the interlayer resin insulation layer.
- m the number of contact points between filled vias and solder poles can be increased to improve the wettability when forming solder bumps.
- Bumps that are not mounted (mixing bumps) can be reduced, and it becomes easier to adapt to finer processing.
- FIG. 1 is a cross-sectional view of a printed wiring board according to the present invention.
- FIG. 2 is a cross-sectional view showing a state where an IC chip is mounted on the printed wiring board shown in FIG. 1 and placed on the daughter pole.
- 3A to 3C are diagrams illustrating a process of forming solder bumps on a printed wiring board.
- FIGS. 4A to 4B are schematic views showing the configuration of the solder pole mounting device.
- Fig. 5 A is a schematic diagram for explaining the positioning of the printed wiring board.
- FIG. B is a schematic diagram for explaining the supply of solder poles to the mounting cylinder.
- FIG. FIG. 6A is a schematic diagram for explaining the assembly of solder balls by the mounting cylinder
- FIG. 6B is a schematic diagram for explaining the assembly and induction of solder poles by the mounting cylinder.
- FIG. 7A is a schematic diagram for explaining the dropping of the solder ball onto the connection pad
- FIG. 7B is a schematic diagram for explaining the removal of the solder pole by the suction ball removing cylinder.
- Fig. 8 is a schematic diagram for explaining the maximum roughness of the surface of the Solder Regis Saddle.
- FIG. 9 is a schematic view for explaining the relationship between the solder bump diameter (W) and the solder resist layer opening diameter (D) in the present invention.
- Fig. 10 A is a schematic diagram for explaining the bump shape near the boundary between the solder bump and the surface of the solder resist layer when the solder resist layer layer opening has a rectangular cross section.
- FIG. 5 is a schematic diagram for explaining a bump shape in the vicinity of a boundary between a solder bump and a solder resist layer surface when the solder resist layer opening has a trapezoidal cross section.
- FIGS. 11A to 11B are schematic diagrams for explaining unevenness of the filled via surface as a connection pad.
- 12A to 12B are schematic diagrams for explaining the connection pad region.
- an embodiment of the printed wiring board of the present invention is provided with an opening in a solder resist layer (SR layer) formed in the outermost layer of the wiring board, and a conductor exposed from the opening.
- a part of the circuit is formed as a conductor pad for mounting electronic components, and the conductor pads are arranged at a pitch of 200 m or less, and solder bumps formed on the conductor pads Is disposed in a form completely filled in the opening, and the ratio (W / D) of the solder bump diameter W to the opening diameter D of the opening is 1.05 to 1.7. It is characterized by.
- a fine diameter as described later is used instead of a conventional printing method using a mask. It is desirable to use a new method and apparatus for dropping a solder pole having a solder pole onto a connection pad through an opening of a pole alignment mask.
- FIG. 1 shows a cross-sectional view of the printed wiring board 10
- FIG. 2 shows a state where the IC chip 90 is attached to the printed wiring board 10 shown in FIG. 1 and mounted on the daughter pad 94.
- conductor circuits 34 are formed on both surfaces of the core substrate 30, and these conductor circuits are electrically connected through the through holes 36.
- a conductor circuit 58 that forms a conductor circuit layer is formed on the conductor circuit 34 of the core substrate 30 via an interlayer resin insulation layer 50.
- the conductor circuit 58 is connected to the conductor circuit 34 via the via hole 60.
- a conductor circuit 1 5 8 is formed on the conductor circuit 5 8 via an interlayer resin insulation layer 1 5 50.
- the conductor circuit 1 5 8 is connected to the conductor circuit 5 8 through a via hole 1 60 formed in the interlayer resin insulation layer 1 5 0.
- the solder resist layer 70 is formed so as to cover the conductor circuit 15 8 and the via hole 160, and the nickel plating layer 72 and the gold plating layer 74 are formed in the opening 71 provided in the solder resist layer 70.
- the connection pad 75 is formed.
- Solder bumps 7 8 are formed on the connection pad 75 on the upper surface
- BGA (pole grid array) 7 8 D is formed on the connection pad 75 on the lower surface.
- the solder bump 7 8 U on the upper surface side of the printed wiring board 10 is connected to the electrode 92 of the IC chip 90 to constitute an IC mounting printed wiring board.
- the wiring board is connected to the land 96 of the daughter pad 94 via the BGA 78D provided on the lower surface side.
- the surface of the solder resist layer is preferably subjected to a planarization process at least in the electronic component mounting region. Since the solder resist layer and the solder bump have different coefficients of thermal expansion, the shrinkage and expansion are repeated near the boundary between the solder bump and the solder resist layer due to thermal changes. When there are large irregularities on the surface of the solder resist layer, that is, when the flatness is low, the volume of the solder resist layer near the solder bumps is small, so that the solder resist layer is easily broken. Therefore, by reducing the flatness of the surface of the solder resist layer to some extent, the volume of the solder resist layer where stress is high can be increased, so there are fewer bends where the stress is concentrated and obscured. This is because the heat cycle resistance can be improved.
- the planarized surface of the solder regist soot layer preferably has a maximum surface roughness of 0.8 to 3.0 m.
- the planarized solder regis It is desirable to further roughen the surface of the soot layer. Since the surface of the solder resist ⁇ layer that has been flattened to a certain extent is roughened to form even smaller irregularities than the flattened surface, the wettability of the underfill can be improved. This is because the underfill can be filled in a narrow gap near the boundary between the solder bump and the solder bump, improving connection reliability.
- the surface of the soldered resist layer subjected to the roughening treatment is preferably smaller than the maximum surface roughness of the flattened surface and has an arithmetic average roughness (R a) of 0.2 to 0.5 U m. .
- the opening provided in the Solder Regis soot layer may be rectangular or trapezoidal in cross section, as shown in FIGS.
- the opening end is tapered, so the solder bump portion filled in the opening and the solder bump portion exposed outside the opening are smooth.
- the solder bump bends near the boundary with the solder resist layer become smaller, i.e., the shape of the solder bump does not change extremely at the boundary with the solder resist layer. It becomes difficult to concentrate. As a result, solder bumps are less likely to be broken and connection reliability is improved.
- D 1 — D 2 has a trapezoidal shape of 5 to 20 m.
- connection pads 75 provided on the upper surface the two connection pads located in the center are formed in the form of lands just above the via holes 160, and The two connection pads adjacent to each other are formed in the form of a pad adjacent to the land of the via hole 160, and the two connection pads located at the left and right ends are connected to the wiring pads of the conductor circuit 15 58. It is formed in the form of pads consisting of a part of the turn, and solder bumps are formed on these connection pads.
- connection pads 75 on the lower surface the two connection pads located at the left and right ends are formed in the form of lands just above the via holes 160, and the four connection pads located in the center are It is formed in the form of a pad adjacent to the via hole 160 land.
- the via hole 160 as the connection pad on which the solder bump 78 U is formed is preferably a filled via, and the unevenness of the filled via surface exposed from the surface of the interlayer resin insulation layer 15 50 is shown in FIG. As shown in A to 11 ⁇ , the range of 15 to 15 m is desirable for the conductor thickness of conductor circuit 15 8. The reason for this is that if the dent amount on the filled via surface exceeds 5 jU m (15 m), the number of contact points between the solder pole and the connection pad made up of the filled via is reduced, so that the wettability is reduced when the solder bump is formed. This is because it is easy to get a void inside the bump or not to install it (missing bump). On the other hand, if the convex amount on the filled via surface exceeds 5 mm (+5 mm), the thickness of the conductor circuit 15 8 will increase, and it will not be suitable for refinement.
- connection pad region is a region in which a conductor pad for mounting an electronic component such as a connection pad or a field via is formed (hereinafter simply referred to as “connection pad region”). Is roughly equivalent to
- Fig. 1 2 A shows an embodiment in which all of the outermost connection pads of the connection pads arranged in a grid are arranged along each side of the rectangle
- Fig. 1 2 B shows Out of the connection pads arranged in a grid, the outermost connection pad
- connection pad region J A rectangular region that is determined so that the area surrounding all the connection pads, including, is minimized.
- 3A to 3C are diagrams for explaining a process of forming solder bumps on the printed wiring board 10. '
- the conductor pad formed in the opening 71 provided in the solder resist layer 70 on the upper surface side of the printed wiring board 10, that is, the flux layer 80 covering the connection pad 75 is formed by a printing method. (See Figure 3A).
- solder pole 78s for example, made by Hitachi Metals or Tamura
- connection pad 75 is mounted on the upper surface side of the printed wiring board 10 using a solder ball mounting device described later.
- solder poles are preferably less than 4 O to 2 O O m0 in diameter. If the diameter is less than 40 ⁇ ⁇ ⁇ ⁇ , the solder pole will be too light to fall on the connection pad. On the other hand, if it exceeds 200 m0, it is too heavy, so that the solder poles cannot be assembled in the cylindrical member, and there are connection pads on which no solder balls are placed. For finer soldering, solder balls with a diameter of 80 m0 or less are desirable.
- connection pad 75 on the lower surface side of the printed wiring board 10 for example, using a suction head as described in Patent No. 1 9 75 4 29, the normal diameter (2 Adsorb 5 8 m) solder balls 7 8 L and place them (see Fig. 3C).
- overheating is performed in a reflow furnace, and as shown in FIG.
- 2500 BGA 78 8 D are formed on the lower surface side at a pitch of 2 mm.
- the pitch of the solder bumps is the pitch of the connection pads. This is because if the pad pitch is less than 60 ⁇ m, it becomes difficult to manufacture a solder pole suitable for the pitch. On the other hand, if the pitch of the connection pad exceeds 200 jw m, it is not possible to obtain a printed wiring board that can handle a narrow pitch.
- an IC mounting printed wiring board 10 is formed by mounting an IC chip 90 via solder bumps 7 8 U by reflow, and this IC mounting printed wiring board 10 0. It is attached to Dotapodo 9 4 via the BGA 7 8 D.
- solder ball mounting apparatus that mounts a small solder pole 78s on the connection pad of the printed wiring board described above will be described with reference to FIGS. 4A to 4B.
- FIG. 4A is a configuration diagram showing the configuration of the solder pole mounting device
- FIG. 4B is an arrow view of the solder ball mounting device of FIG. 4A as viewed from the arrow B side.
- the solder pole mounting device 20 includes an XY 0 suction table 14 that positions and holds the printed wiring board 10, a vertical movement shaft 12 that raises and lowers the XYS suction table 14, and a connection pad for the printed wiring board. Negative alignment pressure is applied to the mounting cylinder (cylindrical member) 2 4 and the mounting cylinder 2 4 for guiding the solder pole moving on the ball alignment mask 1 6, the ball alignment mask 16 having an opening corresponding to the cylinder 75.
- Suction ball removal suction device 6 8 mask clamp 4 4 for clamping pole alignment mask 1 6, mounting cylinder 2 4 and solder pole removal cylinder 6 1 are sent in X direction X direction moving shaft 40 and X direction Moving shaft support guide for supporting moving shaft 4 0 4 2
- Multi-layer printed circuit board 10 Alignment camera 4 6 for taking images, remaining amount detection sensor 1 8 for detecting remaining amount of solder pole under mounting cylinder 2 4, remaining amount detection sensor 1 8 And a solder pole supply device 2 2 for supplying a solder ball to the mounting cylinder 2 4 side based on the remaining amount detected by.
- a plurality of mounting cylinders 24 and solder pole removing cylinders 6 1 are arranged in the Y direction corresponding to the size of the connection pad region.
- the size may correspond to a plurality of connection pad areas.
- the Y direction is convenient and may be arranged in the X direction.
- the XY 0 suction table 14 positions, sucks, holds, and corrects the printed wiring board 10 on which the solder pole is mounted.
- Alignment ⁇ Camera 4 6 detects the alignment mark of printed wiring board 10 on XY 0 suction table 14 and positions of printed wiring board 10 and pole alignment mask 16 based on the detected position. Is adjusted.
- the remaining amount detection sensor 18 detects the remaining amount of the solder pole by an optical method.
- solder pole mounting process by the solder ball mounting apparatus 20 will be described with reference to FIGS.
- the alignment mark 3 4 M of the printed wiring board 10 is recognized by the alignment camera 46, and the position of the printed wiring board 10 relative to the pole alignment mask 16 is XY. 0 Correct with suction table 1 4. That is, the position is adjusted so that the openings 16 a of the pole alignment mask 16 correspond to the connection pads 75 of the printed wiring board 10, respectively.
- the position is adjusted so that the openings 16 a of the pole alignment mask 16 correspond to the connection pads 75 of the printed wiring board 10, respectively.
- only one printed wiring board 10 is shown, but actually, it is soldered to the printed wiring board of the worksheet size that constitutes a plurality of printed wiring boards. A pole is mounted, and after the formation of solder bumps, it is cut into individual multilayer printed wiring boards.
- the solder pole 78 2 s is quantitatively supplied from the solder pole supply device 22 to the mounting cylinder 24 side.
- the solder ball a commercially available product (for example, manufactured by Hitachi Metals) may be used, or manufactured according to the manufacturing apparatus and manufacturing method described in Japanese Patent Laid-Open No. 2 0 0 1-2 2 6 7 0 5. May be.
- the desired solder ball diameter also has a square slit (opening) whose vertical and horizontal dimensions are 1 / m smaller. Place it on a metal plate (for example, Ni with a thickness of 25 J Um), and then roll the solder ball down from the slit. As a result, a solder pole having a small diameter can be removed. After that, the solder balls remaining on the metal plate are classified by a metal plate having a square slit whose vertical and horizontal dimensions are 1 jt m larger than the desired solder ball diameter, and the solder balls have fallen from the slit. By collecting the pole, a solder ball having a diameter almost equal to the desired diameter can be obtained.
- a metal plate for example, Ni with a thickness of 25 J Um
- the mounting cylinder 2 is maintained above the pole alignment mask 16 while maintaining a predetermined clearance (for example, 50% to 300% of the pole diameter) with the ball alignment mask. 4 is positioned, and air is sucked from the suction part 2 4 B, so that the flow velocity in the gap between the mounting cylinder and the printed wiring board is 5 m / seG to 35 m / sec. Assembling the solder poles 7 8 s on the pole alignment masks 16 immediately below the opening 2 4 A.
- a predetermined clearance for example, 50% to 300% of the pole diameter
- the mounting cylinders 24 arranged along the vertical axis of the printed wiring board 10 are moved horizontally along the X axis via the X direction moving axis 40. send.
- the solder balls 7 8 s assembled on the pole alignment mask 1 6 are moved along with the movement of the mounting cylinder 2 4, and the solder poles are opened through the openings 1 6 a of the ball alignment mask 1 6.
- 7 8 s is dropped to the connection pad 7 5 of the printed wiring board 10 and mounted.
- the solder balls 78s are sequentially arranged on all the connection pads on the printed wiring board 10 side.
- solder pole removing cylinder 6 Aspirate with 1.
- the mounting cylinder 2 4 is positioned above the ball alignment mask 16, and the suction part 2 4 located above the mounting cylinder 24 By aspirating air from B, the solder poles 7 8 s are assembled, and the mounting cylinder 24 is moved in the horizontal direction, so that the assembled solder poles 7 8 s are transferred to the pole alignment mask 16.
- the solder ball 7 8 s can be dropped onto the connection pad 7 5 of the printed wiring board 10 through the opening 16 6 a of the ball alignment mask 16.
- solder pole can be mounted on the connection pad 75 without damaging it. 8 U height can be made uniform.
- the solder pole can be properly placed on the connection pad even on a printed wiring board with many undulations on the surface.
- the pitch of the connection pad is 60 to 200 mm, and the opening diameter of the solder one resist ⁇ is 4 Even on a printed wiring board with a pinned pitch arrangement such as 0-15 O jU m, it is possible to form stable solder bumps with almost uniform height for all bumps.
- solder pole is guided by the suction force, the solder balls can be prevented from agglomerating and adhering. Furthermore, by adjusting the number of installed cylinders 24, it can be applied to workpieces of various sizes (worksheet-sized multi-layer pudding and wiring boards), so it can be flexibly applied to multi-product and low-volume production. It is possible to do.
- a plurality of mounting cylinders 24 are arranged in the Y direction corresponding to the width of the workpiece (worksheet-sized printed wiring board) as shown in FIG. 4B. Solder balls can be securely mounted on all the connection pads 75 of the printed wiring board 10 simply by sending them in the direction perpendicular to the column direction (X direction).
- solder ball 78s remaining on the reball alignment mask 16 can be recovered by the solder pole removing cylinder 61, the surplus solder ball remains and does not cause troubles such as failure.
- solder pole mounted on the connection pad of the printed wiring board using the solder ball mounting method and apparatus as described above becomes a solder bump having a predetermined height by the riff mouth process, and such solder
- the IC chip is mounted on the substrate via the bump, and the printed wiring board according to the present invention is manufactured.
- a double-sided copper clad laminate (for example, product name “MC L-E-6 7” manufactured by Hitachi Chemical Co., Ltd.) was used as a starting material, and a sulfone conductor and a conductor circuit were formed on this substrate by a well-known method.
- the interlayer insulation layer and the conductor circuit layer are alternately Stacked, outermost conductor circuit layer, thickness: 20 / m, diameter (connection pad diameter): 120 kJ m, pitch: 150 mm, number: 50 x 40 (pieces) the IC chip mounting connection pad group consisting of) formed in the first 5 0 mm 2 connecting pad region.
- connection pad is formed by a method similar to the method described in Japanese Patent Laid-Open No. 2000-357762.
- connection pads In addition, when changing the size, pitch, number, and arrangement of the connection pads, it is necessary to change the pattern of the resist (opening diameter, pitch, arrangement, etc.). So do it.
- the solder resist layer is formed by screen printing using a commercially available solder resist under the following rough printing conditions to cover the connection pad 15 to 25 m thick (on the connection pad) The thickness of the solder resist layer is formed.
- the solder resist layer was formed to a thickness of 16 Jum. After that, in the state in which the fog mask on which the solder resist ⁇ opening pattern (mask pattern) is drawn is in close contact with the solder resist layer, exposure is performed with ultraviolet rays of 1 0 0-1 0 00 0 mj, and the following An opening with a diameter of 40 to 1550 m is formed on the connection pad by developing using a horizontal developing device under such development conditions.
- a horizontal transport developing device equipped with a conveyor for carrying a substrate into the development processing zone and transporting the development processing zone, and a plurality of spray nozzles positioned above and below the substrate and capable of adjusting the spray spray pressure. Is used.
- Spray type A slit nozzle (a nozzle that sprays liquid in a straight line) or a full cone nozzle (a nozzle that sprays liquid in a radial pattern) is used.
- Spray oscillation Yes ⁇ No
- Spray surface to be used Upper surface or lower surface (When developing with a spray located above the substrate, carry it into the horizontal developing unit with the solder resist surface forming the opening facing upward. Below the substrate With the spray located at When the image is taken, it is carried into the horizontal developing device with the solder resist surface that forms the opening facing downward. )
- a sodium carbonate solution Na 2 C 0 3
- a concentration of 10 g / L was used with the solder resist surface facing downward and the slit nozzle located below not being swung.
- pole alignment mask a Ni metal mask having an opening of 1 ⁇ / ⁇ 0 at a position corresponding to the connection pad of the printed wiring board was used.
- pole alignment mask made of SUS or polyimide.
- the diameter of the opening formed in the pole alignment mask is preferably 1.1 to 1.5 times the diameter of the ball used.
- the thickness of the pole alignment mask is equal to the diameter (diameter) of the solder pole used. 1/2 to 3/4 is preferred.
- connection pad formation area 1.2 to 3 times the connection pad area
- a height of 20 O mm maintains a clearance twice the solder ball diameter. Then place it on the metal mask (pole alignment mask) and mount the solder pole on the ball alignment mask in the vicinity.
- Sn Pb solder was used as the material for the solder pole, but Pb-free solder consisting of at least one metal selected from the group of Ag, Cu, In, Bi, Zn, etc. and Sn It may be. Then, air is sucked from the top of the mounting cylinder, and the flow velocity between the mounting cylinder and the printed circuit board is increased to 5 to 35 m / s e.
- the mounting cylinder is moved at a moving speed of 10 to 4 O mm / sec to roll the solder pole, and the solder pole is dropped from the opening of the pole alignment mask, and the solder pole is placed on the connection pad. Equipped with.
- solder pole alignment mask After removing the extra solder poles from the pole alignment mask, remove the solder pole alignment mask and the printed wiring board separately from the solder ball mounting device. Finally, remove the printed wiring board at 230 ° C. The solder bumps were formed in the reflow set to.
- solder bump diameter was measured by “WYK0 NT-2000J” manufactured by Beco Co., and found to be 8 4 j (m.
- the IC chip was mounted via the solder bump, and a commercially available underfill agent was filled between the IC chip and the solder resist to manufacture an IC mounted printed wiring board.
- a printed wiring board was manufactured in the same manner as in Example 1 except that a solder pole having a diameter of 10 O jw m was mounted. As a result, the solder bump diameter was 100 mm.
- a printed wiring board was manufactured in the same manner as in Example 1 except that a solder pole having a diameter of 120 m was mounted. As a result, the solder bump diameter was 1 20 m. (Example 4)
- a printed wiring board was manufactured in the same manner as in Example 1 except that a solder pole having a diameter of 140 m was mounted. As a result, the solder bump diameter was 1 3 5 m.
- a printed wiring board was produced in the same manner as in Example 1 except that the full cone nozzle was used without swinging. As a result, a trapezoidal opening with an upper opening diameter of 85 m and a bottom opening diameter of 80 jum was formed, but the solder bump diameter was 8 4 m as in Example 1. Met.
- solder bump volume occupies the majority of the solder bump volume, and it is assumed that this is not affected by the shape of the solder resist opening.
- the solder one resist layer opening has a trapezoidal cross section as shown in FIG. It can be seen that the shape of the boundary between the solder bump and the solder resist layer surface (the part indicated by the dotted line) is different by adopting the taper shape.
- a printed wiring board was manufactured in the same manner as in Example 5 except that solder balls having a diameter of 100 jUm were used. As a result, the solder bump diameter is 105 m.
- a printed wiring board was produced in the same manner as in Example 5 except that solder balls having a diameter of 120 m were used. As a result, the solder bump diameter was 1 28 jum.
- a printed wiring board was manufactured in the same manner as in Example 5 except that a solder ball having a diameter of 140 jw m was used. As a result, the solder bump diameter is 1 4 5 // m.
- a printed wiring board was produced in the same manner as in Example 5 except that the full cone nozzle was used while being swung and a solder ball having a diameter of 2 Um was used. As a result, a trapezoidal opening having an upper opening diameter of 90 m and a bottom opening diameter of 80 jum was formed, and the solder bump diameter was 9 Um. (Example 10)
- a printed wiring board was manufactured in the same manner as in Example 6 except that a full cone nozzle was used in a rocking state and a solder ball having a diameter of 2 m was used. As a result, a trapezoidal opening having a top opening diameter of 90 and a bottom opening diameter of 80 m was formed, and the solder pump diameter was 1 13 / m.
- a printed wiring board was manufactured in the same manner as in Example 8 except that the full cone nozzle was used in a rocking state and a solder ball having a diameter of 2 m was used. As a result, a trapezoidal opening having a top opening diameter of 90 / m and a bottom opening diameter of 80 m was formed, and the solder bump diameter was 1555 jum.
- a printed wiring board was manufactured in the same manner as in Example 9 except that the solder resist surface was turned upward, the full cone nozzle located above was swung, and a solder ball having a diameter of 2 jwm was used. As a result, the upper opening diameter is 10 A trapezoidal opening having a bottom opening diameter of 80 m was formed at 0 U, and the solder bump diameter was 105 m.
- Solder-resistor wiring board is mounted in the same manner as Example 10 except that the solder cone is faced upward, the full cone nozzle located above is swung, and a solder pole with a diameter of 2 j «m is used. Manufactured. As a result, a trapezoidal opening having a top opening diameter of 1 O O jt m and a bottom opening diameter of 80 m was formed, and the solder bump diameter was 125 mm.
- a printed wiring board was manufactured in the same manner as in Example 11 except that the solder resist surface was turned upward, the full cone nozzle located above was swung, and a solder pole with a diameter of 2 m was used. As a result, a trapezoidal opening having a top opening diameter of 100 m and a bottom opening diameter of 80 Um was formed, and the solder bump diameter was 150 mm;
- a printed wiring board was manufactured in the same manner as in Example 12 except that the solder cone ridge surface was turned upward, the full cone nozzle located above was swung, and a solder pole with a diameter of 2 jum was used. As a result, a trapezoidal opening having a top opening diameter of 100 m and a bottom opening diameter of 80 Um was formed, and the solder bump diameter was 170 m.
- the pudding board was manufactured. As a result, the solder bump diameter was 63 m.
- Example 1 A printed wiring board was manufactured in the same manner as in Example 17 except that a solder pole having a diameter of 70 m was used. As a result, the solder bump diameter was 75 jum.
- a printed wiring board was manufactured in the same manner as in Example 17 except that solder balls having a diameter of 80 m were used. As a result, the solder bump diameter was 90 m.
- a printed wiring board was manufactured in the same manner as in Example 17 except that a solder pole having a diameter of 95 m was used. As a result, the solder bump diameter was 102 m.
- Example 1 7 the size of the connection pad is set to 70 jU m, the pitch is set to 100 m, and the diameter of the mask for forming an opening in the Solder Regis layer is changed.
- connection pad size is 70 jU m
- its pitch is 100 m
- the mask diameter for forming the opening in the solder resist layer is changed.
- a printed wiring board is formed in the same manner as in Example 5 except that an opening having an opening diameter of 65 jum and a bottom opening diameter of 60 m is formed and a solder pole having a diameter of 70 ⁇ m is used. Manufactured. As a result, the solder bump diameter was 80 m.
- the size of the connection pad is 70 m in diameter
- the pitch is 100 m jm
- a mass for forming an opening in the solder registrant layer is formed.
- Example 5 except that the diameter of the screw was changed to form an opening with a top opening diameter of 65 / im and a bottom opening diameter of 60, and a solder pole with a diameter of 80 m was used.
- a printed wiring board was produced in the same manner as described above. As a result, the solder bump diameter was 96 m.
- connection pad size is 70 jw m
- its pitch is 100 m
- the mask diameter for forming an opening in the solder resist layer is changed.
- a printed wiring board was formed in the same manner as in Example 5 except that an opening having an opening diameter of 65 m and a bottom opening diameter of 60 was formed and a solder ball having a diameter of 95 ⁇ m was used. Manufactured. As a result, the solder bump diameter was 110 m.
- a printed wiring board was manufactured in the same manner as in Example 21 except that the full cone nozzle was swung and a solder pole with a diameter of 2 m was used. As a result, a trapezoidal opening with a top opening diameter of 70 jt / m and a bottom opening diameter of 60 m was formed, and the solder bump diameter was 73 m.
- a printed wiring board was manufactured in the same manner as in Example 22 except that the full cone nozzle was used in a rocking state and a solder ball having a diameter of 2 Um was used. As a result, a trapezoidal opening with a top opening diameter of 70 and a bottom opening diameter of 60 m was formed, and the solder bump diameter was 88 ⁇ m.
- a printed wiring board was manufactured in the same manner as in Example 23 except that the full cone nozzle was used in a rocking state and a solder ball having a diameter of 2 m was used. As a result, a trapezoidal opening having an upper opening diameter of 70 m and a bottom opening diameter of 60 m is formed, and the solder bump diameter is 10 5 im. I got it.
- a printed wiring board was produced in the same manner as in Example 2 4. As a result, a trapezoidal opening with an upper opening diameter of 70 m and a bottom opening diameter of 60 m was formed, and the solder bump diameter was 120 jw m.
- a printed wiring board was manufactured in the same manner as in Example 25 except that the solder resist surface was turned upward, the full cone nozzle located above was swung, and a solder pole with a diameter of 2 jUm was used. As a result, a trapezoidal opening having an upper opening diameter of 80 m and a bottom opening diameter of 60 IX m was formed, and the solder bump diameter was 84 m.
- a printed wiring board was manufactured in the same manner as in Example 26 except that the solder resist surface was faced upward, the full cone nozzle located above was swung, and a solder ball having a diameter of 2 m was used. As a result, a trapezoidal opening having an upper opening diameter of 80 ⁇ m and a bottom opening diameter of 60 ULm was formed, and the solder bump diameter was 100 degrees.
- a printed wiring board was produced in the same manner as in Example 27 except that the solder resist surface was turned upward, the full cone nozzle located above was swung, and a solder ball having a diameter of 2 m was used. As a result, a trapezoidal opening having an upper opening diameter of 80 ⁇ m and a bottom opening diameter of 60 ⁇ m was formed, and the solder bump diameter was 120 m.
- Example 2 with the exception of using a solder ball with a diameter of 2 m, with the Solder Regis saddle face facing upward and the full cone nozzle positioned above swaying.
- a printed wiring board was produced in the same manner as in FIG. As a result, a trapezoidal opening having an upper opening diameter of 80 pm and a bottom opening diameter of 60 Um was formed, and the solder bump diameter was 13.5 m.
- the pattern of the plating resist ⁇ for forming the connection pad was changed to form a connection pad with a diameter of 150 m at a pitch of 190 m, and a mask for forming openings in the solder resist layer.
- connection pad Change the pattern of the plating resists ⁇ to form the connection pad, form connection pads with a diameter of 70 ⁇ m at a pitch of 100 jU m, and solder balls with a diameter of 1 25 jum
- solder bump diameter was 1 30 jum.
- a printed wiring board was manufactured in the same manner as in Example 33, except that a solder pole having a diameter of 15 5 W m was used. As a result, the solder bump diameter was 1555 im.
- a printed wiring board was manufactured in the same manner as in Example 33 except that solder balls having a diameter of 180 m were used. As a result, the solder bump diameter was 1 75 / m.
- the size of the connection pad is set to 1 50 jum, its pitch is set to 190 m, and the diameter of the mask for forming the opening in the solder resist layer is changed.
- Forming an opening with a top opening diameter of 10 8 jum and a bottom opening diameter of 10 3 jum, and using a solder ball with a diameter of 10 5 jw m A printed wiring board was produced in the same manner as in Example 33, except that. As a result, the solder bump diameter was 1 1 3 mm.
- Example 3 3 except that an opening having an upper opening diameter of 10 8 j «m and a bottom opening diameter of 10 3 m was formed and a solder pole having a diameter of 1 2 5; Urn was used. A printed wiring board was produced in the same manner as described above. As a result, the solder bump diameter was 1 3 5 m.
- Example 3 3 except that an opening having a top opening diameter of 10 8 / im and a bottom opening diameter of 10 3 m was formed and a solder pole having a diameter of 15 5 m was used. Similarly, a printed wiring board was manufactured. As a result, the solder bump diameter was 16 2 jum.
- Example 3 3 similarly connected pad size 1 5 0 JU is the diameter m, the peak Tutsi and 1 9 0 JU m, changing the diameter of the mask for forming an opening in the solder Regis Bok layer Example 3 except that an opening having a top opening diameter of 10 8 jum and a bottom opening diameter of 10 3 / m was formed and a solder ball having a diameter of 180 m was used.
- a printed wiring board was produced in the same manner as in 3. As a result, the solder bump diameter was 1 85 m.
- Example 4 2 By swinging the full cone nozzle, an opening with a top opening diameter of 1 1 3 / J m and a bottom opening diameter of 10 3 m was formed, and a solder ball with a diameter of 2 m was used. Produced a printed wiring board in the same manner as in Example 37. As a result, the solder bump diameter was 1 18 m. (Example 4 2)
- Example 4 By swinging the full cone nozzle, except that the upper opening diameter 1 1 3 / m, the bottom opening diameter to form an opening such that 1 0 3 m, with diameters 2 ⁇ m high solder Paul Produced a printed wiring board in the same manner as in Example 39. As a result, the solder bump diameter was 17 O jw m. (Example 4 4)
- a printed wiring board was manufactured in the same manner as in Example 4-1, except that the solder resist surface was turned upward, the full cone nozzle located above was swung, and a solder pole with a diameter of 2 jum was used. . As a result, a trapezoidal opening having a top opening diameter of 123 ⁇ m and a bottom opening diameter of 103 jWm was formed, and the solder bump diameter was 1 29 mm.
- a printed wiring board was produced in the same manner as in Example 42 except that the solder resist surface was turned upward, the full cone nozzle located above was swung, and a solder ball having a diameter of 2 m was used. As a result, a trapezoidal opening having a top opening diameter of 12 3 ⁇ m and a bottom opening diameter of 10 3 U m was formed, and the solder bump diameter was 1 29 jU m.
- Example 4 A printed wiring board was manufactured in the same manner as in Example 43 except that the solder resist surface was turned upward, the full cone nozzle located above was swung, and a solder ball having a diameter of 2 jum was used. As a result, a trapezoidal opening having a top opening diameter of 1 2 3 jw m and a bottom opening diameter of 10 3 im was formed, and the solder bump diameter was 1 85 m.
- a printed wiring board was manufactured in the same manner as in Example 44 except that the solder resist surface was turned upward, the full cone nozzle located above was swung, and a solder ball having a diameter of 2 m was used. As a result, a trapezoidal opening with a top opening diameter of 12.3 jum and a bottom opening diameter of 103 m was formed, and the solder bump diameter was 210 jUm.
- a printed wiring board was manufactured in the same manner as in Example 1 except that a solder pole having a diameter of 160 jtim was used. As a result, the solder bump diameter was 1600) Wm.
- a printed wiring board was manufactured in the same manner as in Examples 1 to 48 except that the number of conductor pads was changed to 30 0 0 0 0 (connection pad area 1 2 200 mm 2 ).
- a printed wiring board was produced in the same manner as in Example 1 except that solder balls having a diameter of 60 m were used. As a result, the solder resist resist opening could not be completely filled with solder.
- Examples 1 to 48 8 IC mounted printed wiring board manufactured according to the reference example and comparative example, the electrical resistance of a specific circuit via the IG chip, that is, the IC chip mounting surface of the IC mounting printed wiring board Measure the electrical resistance between a pair of connection pads exposed on the opposite side and conducting to the IC chip. The value was set as the initial value. Then, after leaving them in an atmosphere of 85 ° C and 85% humidity for 24 hours on their Ic mounted pudding and wiring boards-5 5. A heat cycle test was performed in which GX 30 minutes and 1 25 ° CX 30 minutes were one cycle, and this was repeated 250 times.
- connection reliability is improved in Examples 1 to 48 and Reference Example, in which the solder bumps are completely filled in the solder resist openings compared to the comparative example. This is because the volume of the solder bump is large, so that the stress caused by the difference in thermal expansion between the IC chip and the printed wiring board can be relieved, or there is a gap between the solder resist ⁇ and the solder bump. This is probably because no voids are generated in the underfill, or there is no residue of flux or cleaning liquid.
- the solder resist opening When the ratio (WZD) of the solder bump diameter W to the solder resist ⁇ opening diameter D is in the range of 1.05 to 1.7, (2) the solder resist opening When the diameter is a tapered shape larger than the bottom opening diameter and the ratio (W / D) is in the range of 1.05 to 1.5, (3) Soldering If the diameter of the thread is tapered, the top opening diameter is larger than the bottom opening diameter, and the ratio (W / D) is in the range of 1.05 to 1.25, the connection reliability is as follows. It was observed that the sex was improved.
- the solder resist ⁇ opening may not be filled with solder bumps.
- the shape of the opening provided in the Solder Regis ⁇ layer becomes a trapezoidal shape (the upper opening diameter D 1 of the Solder Regis ⁇ opening> the bottom opening diameter D 2), as shown in FIG. It is assumed that the solder bumps are difficult to break.
- connection pad region such as a large (1 5 0 ⁇ 1 2 0 0 mm 2) is of great significance to be applied to purine Bok wiring board. This is because if the connection pad area (rectangular area including the outermost connection pad) is large, the shear stress resulting from the difference in thermal expansion coefficient between the IC chip and the printed wiring board increases.
- the surface of the solder resist layer is heated and pressed under the following conditions.
- Solder Regis An IC-mounted printed wiring board was manufactured in the same manner as in each Example, except that a flattening process was performed to reduce the irregularities on the surface of the solder layer, and Examples 49 to 66 were obtained.
- the surface roughness meter for example, “SURFCOM 480 AJ: manufactured by Tokyo Seimitsu Co., Ltd. or the product name“ WYKON—250 ” “0: manufactured by Beco Corporation”.
- the measurement points are the surface of the solder resist layer located above the connection pad and the surface of the solder resist soot layer adjacent to the connection pad non-forming part (see Fig. 8). In other words, the unevenness of the solder resist layer due to the presence or absence of the connection pad was measured, and the maximum value (max) and minimum value (min) of the five-point measurement results were recorded. These measurement results are shown in Table 3 (before flattening) and Table 4 (after flattening).
- Examples 49 to 66 after the planarization treatment, the surface of the solder resist layer was roughened under the following conditions to form uniform fine irregularities on the surface.
- An IC mounting printed wiring board was manufactured in the same manner as in each of Examples, and Examples 67 to 84 were obtained.
- the surface roughness of the Solder Regis ⁇ surface (For example, product name “SURFC OM 4 80 A”: manufactured by Tokyo Seimitsu Co., Ltd. or product name “WY KO N-2500”: manufactured by Beco Co., Ltd.) Measured at a standard length of 5 m at 10 random locations. did. As a result, the surface roughness of the roughened surface of the solder resist layer was a small surface with an unevenness of about 0 ⁇ 1 to 0.6 mm.
- “Surface roughness R a” here means “arithmetic mean roughness Ra” defined in JISB 060 1, but Ra has a range in the above measurement results. Of each Ra at 0 point, the one with the smallest Ra is represented as Ra (min), and the one with the largest Ra is represented as Ra (max).
- the average value of 10 ⁇ s is Rm a Indicated as X.
- the surface roughness is measured at random 10 points of the solder resist layer surface corresponding to the conductor circuit (pad) formation region and the solder resist layer surface corresponding to the conductor circuit non-formation region. Measurement was not performed near the boundary between the conductor circuit formation region and the conductor circuit non-formation region.
- Example 6 An IC-mounted printed wiring board manufactured according to 7 to 84 was left in an atmosphere at a temperature of 85 ° G and a humidity of 85% for 24 hours. Cx 30 minutes, 1 25 ° GX 30 minutes was used as a “! Cycle, and a heat cycle test was repeated 2500 times. 1 7 After 50 cycles and 2 000 cycles, the electrical resistance was measured and The rate of change (1 00 X (measured value-initial value) / initial value (%)) was calculated. If the rate of change was within ⁇ 10, it was evaluated as “good” and indicated by o. Is rated as “defective” And indicated by X. These test results are shown in Tables 3-5, respectively. (Table 3)
- the amount of unevenness on the surface of the Solder Regis heel layer is preferably 0.8 to 3.0 m, and the solder resist surface has an arithmetic average roughness Ra of 0.2 to 0.5. It can be seen that the connection reliability is improved when m.
- the bump diameter of the solder bump in the present invention is large, the bump height is also increased accordingly. As a result, the distance between the surface of the solder resist layer and the I c chip increases, making it difficult to fill the underfill and voids are likely to occur in the underfill.
- the underfill moving speed tends to depend on the distance between the solder resist layer surface and the IC chip, it is considered that the unevenness of the solder resist layer surface is preferably 2 jum or less.
- Examples 1 to 84 IC mounted pudding manufactured according to 4 and comparative example ⁇ For wiring boards, while applying a voltage of 3.3 V between independent solder bumps (between solder bumps that are not electrically connected) It was left in an atmosphere of 85 ° C. and 85% humidity for 100 hours. After standing, the insulation resistance between the solder bumps to which voltage was applied was measured. If the value was 10 7 ⁇ or more, it was evaluated as a good product, and if it was less than 10 7 ⁇ , it was evaluated as a defective product. As a result, it was confirmed that Examples 1 to 8 6 were non-defective products and the comparative examples were defective products. Industrial applicability
- the printed wiring board according to the present invention has the solder bump diameter W and the opening diameter provided in the solder resist layer even in a sandwich pitch structure in which the pitch of the solder bump is 20 O jUm or less.
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Abstract
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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CN2006800148638A CN101171895B (zh) | 2005-06-30 | 2006-06-28 | 印刷线路板 |
JP2007524084A JP5021473B2 (ja) | 2005-06-30 | 2006-06-28 | プリント配線板の製造方法 |
EP06780770A EP1887846A4 (fr) | 2005-06-30 | 2006-06-28 | Carte de circuit imprime |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2005-192863 | 2005-06-30 | ||
JP2005192863 | 2005-06-30 |
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WO2007004658A1 true WO2007004658A1 (fr) | 2007-01-11 |
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Application Number | Title | Priority Date | Filing Date |
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PCT/JP2006/313343 WO2007004658A1 (fr) | 2005-06-30 | 2006-06-28 | Carte de circuit imprimé |
Country Status (7)
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US (3) | US8017875B2 (fr) |
EP (1) | EP1887846A4 (fr) |
JP (1) | JP5021473B2 (fr) |
KR (1) | KR100905685B1 (fr) |
CN (2) | CN101854771A (fr) |
TW (1) | TW200718298A (fr) |
WO (1) | WO2007004658A1 (fr) |
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JP2012503887A (ja) * | 2008-09-29 | 2012-02-09 | インテル コーポレイション | マウントされたプロセッサの入出力アーキテクチャ |
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WO2006126621A1 (fr) * | 2005-05-23 | 2006-11-30 | Ibiden Co., Ltd. | Carte de circuit imprimé |
EP1887846A4 (fr) * | 2005-06-30 | 2010-08-11 | Ibiden Co Ltd | Carte de circuit imprime |
JP5021472B2 (ja) | 2005-06-30 | 2012-09-05 | イビデン株式会社 | プリント配線板の製造方法 |
WO2007007865A1 (fr) | 2005-07-11 | 2007-01-18 | Showa Denko K.K. | Procédé de fixation de poudre de soudure sur une carte de circuit électronique et carte de circuit électronique fixée par soudure |
WO2007029866A1 (fr) * | 2005-09-09 | 2007-03-15 | Showa Denko K.K. | Procédé de fixation de poudre de brasage à une carte imprimée électronique et carte imprimée électronique brasée |
JP4731574B2 (ja) * | 2006-01-27 | 2011-07-27 | イビデン株式会社 | プリント配線板及びプリント配線板の製造方法 |
WO2008016128A1 (fr) * | 2006-08-03 | 2008-02-07 | Showa Denko K.K. | Procédé de production d'une carte de circuit imprimé à brasure |
CN101296570A (zh) * | 2007-04-25 | 2008-10-29 | 富葵精密组件(深圳)有限公司 | 电路板及其制作方法 |
US8455766B2 (en) * | 2007-08-08 | 2013-06-04 | Ibiden Co., Ltd. | Substrate with low-elasticity layer and low-thermal-expansion layer |
CN101683001B (zh) * | 2008-05-30 | 2012-01-04 | 揖斐电株式会社 | 焊锡球搭载方法 |
KR101002680B1 (ko) * | 2008-10-21 | 2010-12-21 | 삼성전기주식회사 | 반도체 패키지 및 그 제조 방법 |
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CN102239753B (zh) | 2008-12-05 | 2013-11-06 | 揖斐电株式会社 | 多层印刷线路板和多层印刷线路板的制造方法 |
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JP5640892B2 (ja) * | 2011-05-23 | 2014-12-17 | 三菱電機株式会社 | 半導体装置 |
US8643196B2 (en) * | 2011-07-27 | 2014-02-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for bump to landing trace ratio |
US20130168132A1 (en) * | 2011-12-29 | 2013-07-04 | Sumsung Electro-Mechanics Co., Ltd. | Printed circuit board and method of manufacturing the same |
JP5502139B2 (ja) * | 2012-05-16 | 2014-05-28 | 日本特殊陶業株式会社 | 配線基板 |
FR2991108A1 (fr) * | 2012-05-24 | 2013-11-29 | St Microelectronics Sa | Ligne coplanaire blindee |
KR101497840B1 (ko) * | 2013-12-02 | 2015-03-02 | 삼성전기주식회사 | 솔더레지스트 개구 구조 및 회로 기판 |
JP2016015432A (ja) * | 2014-07-03 | 2016-01-28 | イビデン株式会社 | 回路基板及びその製造方法 |
KR102214512B1 (ko) | 2014-07-04 | 2021-02-09 | 삼성전자 주식회사 | 인쇄회로기판 및 이를 이용한 반도체 패키지 |
US9699921B2 (en) * | 2014-08-01 | 2017-07-04 | Fujikura Ltd. | Multi-layer wiring board |
JP6329027B2 (ja) * | 2014-08-04 | 2018-05-23 | ミネベアミツミ株式会社 | フレキシブルプリント基板 |
JP2016134409A (ja) * | 2015-01-16 | 2016-07-25 | イビデン株式会社 | プリント配線板 |
KR102532200B1 (ko) * | 2015-12-09 | 2023-05-12 | 삼성전자 주식회사 | 테스트 패턴, 반도체 소자의 테스트 방법, 및 집적 회로의 레이아웃 설계를 위한 컴퓨터 구현 방법 |
CN107732488A (zh) * | 2016-08-10 | 2018-02-23 | 泰科电子(上海)有限公司 | 连接件 |
US10164358B2 (en) * | 2016-09-30 | 2018-12-25 | Western Digital Technologies, Inc. | Electrical feed-through and connector configuration |
FR3069128B1 (fr) * | 2017-07-13 | 2020-06-26 | Safran Electronics & Defense | Fixation d'un cms sur une couche isolante avec un joint de brasure dans une cavite realisee dans une couche isolante |
JP6991014B2 (ja) * | 2017-08-29 | 2022-01-12 | キオクシア株式会社 | 半導体装置 |
US20190366460A1 (en) * | 2018-06-01 | 2019-12-05 | Progress Y&Y Corp. | Soldering apparatus and solder nozzle module thereof |
CN111334750B (zh) * | 2020-03-11 | 2022-02-01 | 京东方科技集团股份有限公司 | 一种soi精细掩模版及其制作方法 |
CN111640719B (zh) * | 2020-06-01 | 2022-04-01 | 厦门通富微电子有限公司 | 一种半导体器件及其制作方法 |
KR20210154454A (ko) * | 2020-06-12 | 2021-12-21 | 엘지이노텍 주식회사 | 인쇄회로기판 및 이의 제조 방법 |
US20220069489A1 (en) * | 2020-08-28 | 2022-03-03 | Unimicron Technology Corp. | Circuit board structure and manufacturing method thereof |
CN113524885B (zh) * | 2021-07-17 | 2022-07-08 | 江苏本川智能电路科技股份有限公司 | 一种厚铜板阻焊印刷设备及其印刷方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05121411A (ja) * | 1991-10-25 | 1993-05-18 | Rohm Co Ltd | 電子部品における接続用バンプの形成方法 |
JP2002208778A (ja) * | 2001-01-10 | 2002-07-26 | Ibiden Co Ltd | 多層プリント配線板 |
JP2002217531A (ja) * | 2001-01-12 | 2002-08-02 | Ibiden Co Ltd | 多層プリント配線板の製造方法 |
JP2004179578A (ja) * | 2002-11-29 | 2004-06-24 | Ngk Spark Plug Co Ltd | 配線基板及びその製造方法 |
JP2004207370A (ja) * | 2002-12-24 | 2004-07-22 | Cmk Corp | プリント配線板の製造方法 |
JP2004319676A (ja) * | 2003-04-15 | 2004-11-11 | Harima Chem Inc | はんだ析出方法およびはんだバンプ形成方法 |
Family Cites Families (48)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0245357B2 (ja) | 1982-06-25 | 1990-10-09 | Hitachi Ltd | Kibannosetsuzokukozo |
US5118027A (en) * | 1991-04-24 | 1992-06-02 | International Business Machines Corporation | Method of aligning and mounting solder balls to a substrate |
US5329423A (en) * | 1993-04-13 | 1994-07-12 | Scholz Kenneth D | Compressive bump-and-socket interconnection scheme for integrated circuits |
JPH1140908A (ja) | 1997-07-22 | 1999-02-12 | Ibiden Co Ltd | プリント配線板 |
JPH1174403A (ja) * | 1997-08-28 | 1999-03-16 | Mitsubishi Electric Corp | 半導体装置 |
US6046910A (en) * | 1998-03-18 | 2000-04-04 | Motorola, Inc. | Microelectronic assembly having slidable contacts and method for manufacturing the assembly |
JP2000022039A (ja) * | 1998-07-06 | 2000-01-21 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
US6461953B1 (en) * | 1998-08-10 | 2002-10-08 | Fujitsu Limited | Solder bump forming method, electronic component mounting method, and electronic component mounting structure |
JP3213292B2 (ja) * | 1999-07-12 | 2001-10-02 | ソニーケミカル株式会社 | 多層基板、及びモジュール |
TW434856B (en) * | 2000-05-15 | 2001-05-16 | Siliconware Precision Industries Co Ltd | Manufacturing method for high coplanarity solder ball array of ball grid array integrated circuit package |
CN1196392C (zh) * | 2000-07-31 | 2005-04-06 | 日本特殊陶业株式会社 | 布线基板及其制造方法 |
US6563210B2 (en) * | 2000-12-19 | 2003-05-13 | Intel Corporation | Parallel plane substrate |
TWI293315B (en) | 2000-12-26 | 2008-02-11 | Ngk Spark Plug Co | Wiring substrate |
JP2002290030A (ja) * | 2001-03-23 | 2002-10-04 | Ngk Spark Plug Co Ltd | 配線基板 |
JP3595283B2 (ja) * | 2001-06-27 | 2004-12-02 | 日本特殊陶業株式会社 | 配線基板及びその製造方法 |
DE10138042A1 (de) * | 2001-08-08 | 2002-11-21 | Infineon Technologies Ag | Elektronisches Bauteil und Verfahren zu seiner Herstellung |
JP3910387B2 (ja) * | 2001-08-24 | 2007-04-25 | 新光電気工業株式会社 | 半導体パッケージ及びその製造方法並びに半導体装置 |
US6753480B2 (en) * | 2001-10-12 | 2004-06-22 | Ultratera Corporation | Printed circuit board having permanent solder mask |
TW557521B (en) * | 2002-01-16 | 2003-10-11 | Via Tech Inc | Integrated circuit package and its manufacturing process |
JP2003218272A (ja) * | 2002-01-25 | 2003-07-31 | Sony Corp | 高周波モジュール及びその製造方法 |
JP3819806B2 (ja) * | 2002-05-17 | 2006-09-13 | 富士通株式会社 | バンプ電極付き電子部品およびその製造方法 |
JP4209178B2 (ja) * | 2002-11-26 | 2009-01-14 | 新光電気工業株式会社 | 電子部品実装構造及びその製造方法 |
JP4006699B2 (ja) * | 2003-04-22 | 2007-11-14 | 日立金属株式会社 | 微小ボール搭載用マスクおよび微小ボールの搭載方法 |
WO2004103039A1 (fr) * | 2003-05-19 | 2004-11-25 | Dai Nippon Printing Co., Ltd. | Tableau de connexion double face, procede de production d'un tableau de connexion double face et tableau de connexion multicouche |
KR100520961B1 (ko) * | 2003-05-30 | 2005-10-17 | 엘지전자 주식회사 | 인쇄회로기판의 제조방법 |
TWI222687B (en) * | 2003-08-14 | 2004-10-21 | Advanced Semiconductor Eng | Semiconductor chip with bumps and method for manufacturing the same |
TWI335195B (en) * | 2003-12-16 | 2010-12-21 | Ngk Spark Plug Co | Multilayer wiring board |
JP4387231B2 (ja) * | 2004-03-31 | 2009-12-16 | 新光電気工業株式会社 | キャパシタ実装配線基板及びその製造方法 |
TWI240389B (en) * | 2004-05-06 | 2005-09-21 | Advanced Semiconductor Eng | High-density layout substrate for flip-chip package |
CN100367491C (zh) * | 2004-05-28 | 2008-02-06 | 日本特殊陶业株式会社 | 中间基板 |
CN102413643A (zh) * | 2004-08-04 | 2012-04-11 | 揖斐电株式会社 | 焊球搭载方法及焊球搭载装置 |
US7626829B2 (en) * | 2004-10-27 | 2009-12-01 | Ibiden Co., Ltd. | Multilayer printed wiring board and manufacturing method of the multilayer printed wiring board |
JP2006216713A (ja) * | 2005-02-02 | 2006-08-17 | Ibiden Co Ltd | 多層プリント配線板 |
TWI414218B (zh) * | 2005-02-09 | 2013-11-01 | Ngk Spark Plug Co | 配線基板及配線基板內建用之電容器 |
US7183652B2 (en) * | 2005-04-27 | 2007-02-27 | Infineon Technologies Ag | Electronic component and electronic configuration |
WO2006126621A1 (fr) * | 2005-05-23 | 2006-11-30 | Ibiden Co., Ltd. | Carte de circuit imprimé |
EP1887846A4 (fr) * | 2005-06-30 | 2010-08-11 | Ibiden Co Ltd | Carte de circuit imprime |
JP5021472B2 (ja) | 2005-06-30 | 2012-09-05 | イビデン株式会社 | プリント配線板の製造方法 |
JP4838068B2 (ja) * | 2005-09-01 | 2011-12-14 | 日本特殊陶業株式会社 | 配線基板 |
WO2007072876A1 (fr) * | 2005-12-20 | 2007-06-28 | Ibiden Co., Ltd. | Procede de fabrication de tableau de connexion imprime |
TW200810646A (en) * | 2005-12-20 | 2008-02-16 | Ibiden Co Ltd | Method for manufacturing printed wiring board |
JP4731574B2 (ja) * | 2006-01-27 | 2011-07-27 | イビデン株式会社 | プリント配線板及びプリント配線板の製造方法 |
TWI413471B (zh) * | 2006-01-27 | 2013-10-21 | Ibiden Co Ltd | Method and device for mounting solder ball |
TW200746964A (en) | 2006-01-27 | 2007-12-16 | Ibiden Co Ltd | Method of manufacturing printed wiring board |
US7472473B2 (en) * | 2006-04-26 | 2009-01-06 | Ibiden Co., Ltd. | Solder ball loading apparatus |
US7823762B2 (en) * | 2006-09-28 | 2010-11-02 | Ibiden Co., Ltd. | Manufacturing method and manufacturing apparatus of printed wiring board |
US20090120832A1 (en) * | 2007-11-14 | 2009-05-14 | Debbie Munden | Single hand use baby food and container tray |
CN101683001B (zh) * | 2008-05-30 | 2012-01-04 | 揖斐电株式会社 | 焊锡球搭载方法 |
-
2006
- 2006-06-28 EP EP06780770A patent/EP1887846A4/fr not_active Withdrawn
- 2006-06-28 JP JP2007524084A patent/JP5021473B2/ja active Active
- 2006-06-28 CN CN201010166409A patent/CN101854771A/zh active Pending
- 2006-06-28 CN CN2006800148638A patent/CN101171895B/zh active Active
- 2006-06-28 WO PCT/JP2006/313343 patent/WO2007004658A1/fr active Application Filing
- 2006-06-29 US US11/476,559 patent/US8017875B2/en active Active
- 2006-06-30 TW TW095123799A patent/TW200718298A/zh unknown
-
2007
- 2007-10-31 KR KR1020077025325A patent/KR100905685B1/ko active Active
-
2009
- 2009-11-19 US US12/622,049 patent/US8022314B2/en active Active
-
2011
- 2011-05-17 US US13/109,745 patent/US8624132B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05121411A (ja) * | 1991-10-25 | 1993-05-18 | Rohm Co Ltd | 電子部品における接続用バンプの形成方法 |
JP2002208778A (ja) * | 2001-01-10 | 2002-07-26 | Ibiden Co Ltd | 多層プリント配線板 |
JP2002217531A (ja) * | 2001-01-12 | 2002-08-02 | Ibiden Co Ltd | 多層プリント配線板の製造方法 |
JP2004179578A (ja) * | 2002-11-29 | 2004-06-24 | Ngk Spark Plug Co Ltd | 配線基板及びその製造方法 |
JP2004207370A (ja) * | 2002-12-24 | 2004-07-22 | Cmk Corp | プリント配線板の製造方法 |
JP2004319676A (ja) * | 2003-04-15 | 2004-11-11 | Harima Chem Inc | はんだ析出方法およびはんだバンプ形成方法 |
Non-Patent Citations (1)
Title |
---|
See also references of EP1887846A4 * |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012503887A (ja) * | 2008-09-29 | 2012-02-09 | インテル コーポレイション | マウントされたプロセッサの入出力アーキテクチャ |
WO2012002273A1 (fr) * | 2010-06-28 | 2012-01-05 | アユミ工業株式会社 | Procédé de fabrication d'une structure de jonction, procédé de traitement par chauffage et fusion, et système associé |
JP2012033518A (ja) * | 2010-06-28 | 2012-02-16 | Ayumi Kogyo Kk | 接合構造体製造方法および加熱溶融処理方法ならびにこれらのシステム |
US8757474B2 (en) | 2010-06-28 | 2014-06-24 | Ayumi Industry Co., Ltd. | Bonding structure manufacturing method, heating and melting treatment method, and system therefor |
US9119336B2 (en) | 2010-06-28 | 2015-08-25 | Ayumi Industry Co., Ltd. | Bonding structure manufacturing method, heating and melting treatment method, and system therefor |
KR101805147B1 (ko) * | 2010-06-28 | 2017-12-05 | 아유미 고교 가부시키가이샤 | 접합 구조체 제조 방법 및 가열 용융 처리 방법과 그 시스템 |
JP2014049533A (ja) * | 2012-08-30 | 2014-03-17 | Toppan Printing Co Ltd | 半導体パッケージの製造方法 |
US20200135679A1 (en) * | 2018-10-31 | 2020-04-30 | Intel Corporation | Surface finishes with low rbtv for fine and mixed bump pitch architectures |
US11488918B2 (en) * | 2018-10-31 | 2022-11-01 | Intel Corporation | Surface finishes with low rBTV for fine and mixed bump pitch architectures |
US20230015619A1 (en) * | 2018-10-31 | 2023-01-19 | Intel Corporation | Surface finishes with low rbtv for fine and mixed bump pitch architectures |
US11935857B2 (en) | 2018-10-31 | 2024-03-19 | Intel Corporation | Surface finishes with low RBTV for fine and mixed bump pitch architectures |
Also Published As
Publication number | Publication date |
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CN101171895A (zh) | 2008-04-30 |
JP5021473B2 (ja) | 2012-09-05 |
CN101171895B (zh) | 2010-06-23 |
CN101854771A (zh) | 2010-10-06 |
EP1887846A4 (fr) | 2010-08-11 |
US8624132B2 (en) | 2014-01-07 |
US20100065323A1 (en) | 2010-03-18 |
US8017875B2 (en) | 2011-09-13 |
TWI323624B (fr) | 2010-04-11 |
KR100905685B1 (ko) | 2009-07-03 |
US20070086147A1 (en) | 2007-04-19 |
KR20070116967A (ko) | 2007-12-11 |
EP1887846A1 (fr) | 2008-02-13 |
JPWO2007004658A1 (ja) | 2009-01-29 |
US20110214915A1 (en) | 2011-09-08 |
TW200718298A (en) | 2007-05-01 |
US8022314B2 (en) | 2011-09-20 |
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