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WO2007067860A3 - Contacts sans vide à faible résistance - Google Patents

Contacts sans vide à faible résistance Download PDF

Info

Publication number
WO2007067860A3
WO2007067860A3 PCT/US2006/061351 US2006061351W WO2007067860A3 WO 2007067860 A3 WO2007067860 A3 WO 2007067860A3 US 2006061351 W US2006061351 W US 2006061351W WO 2007067860 A3 WO2007067860 A3 WO 2007067860A3
Authority
WO
WIPO (PCT)
Prior art keywords
low
opening
plug
eeprom devices
free contacts
Prior art date
Application number
PCT/US2006/061351
Other languages
English (en)
Other versions
WO2007067860A2 (fr
Inventor
Masaaki Higashitani
Original Assignee
Sandisk Corp
Masaaki Higashitani
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/296,235 external-priority patent/US7737483B2/en
Priority claimed from US11/296,022 external-priority patent/US7615448B2/en
Application filed by Sandisk Corp, Masaaki Higashitani filed Critical Sandisk Corp
Priority to EP06848514A priority Critical patent/EP1958252A2/fr
Publication of WO2007067860A2 publication Critical patent/WO2007067860A2/fr
Publication of WO2007067860A3 publication Critical patent/WO2007067860A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Electric Double-Layer Capacitors Or The Like (AREA)
  • Secondary Cells (AREA)

Abstract

Un bouchon est formé par dépôt d'un premier matériau en vue du remplissage partiel d'une ouverture de façon qu'il reste une partie non remplie présentant un rapport de forme inférieur à celui de l'ouverture initiale. Un second matériau est alors déposé en vue du remplissage de la partie restante de l'ouverture. Le premier matériau présente de bonnes caractéristiques de remplissage mais une résistivité supérieure à celle du second matériau. Le second matériau présente une faible résistivité, ce qui confère une faible résistance au bouchon.
PCT/US2006/061351 2005-12-06 2006-11-29 Contacts sans vide à faible résistance WO2007067860A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP06848514A EP1958252A2 (fr) 2005-12-06 2006-11-29 Contacts sans vide à faible résistance

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/296,235 US7737483B2 (en) 2005-12-06 2005-12-06 Low resistance void-free contacts
US11/296,022 US7615448B2 (en) 2005-12-06 2005-12-06 Method of forming low resistance void-free contacts
US11/296,235 2005-12-06
US11/296,022 2005-12-06

Publications (2)

Publication Number Publication Date
WO2007067860A2 WO2007067860A2 (fr) 2007-06-14
WO2007067860A3 true WO2007067860A3 (fr) 2007-09-07

Family

ID=38123591

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/061351 WO2007067860A2 (fr) 2005-12-06 2006-11-29 Contacts sans vide à faible résistance

Country Status (3)

Country Link
EP (1) EP1958252A2 (fr)
TW (1) TWI332252B (fr)
WO (1) WO2007067860A2 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10559571B2 (en) * 2017-04-13 2020-02-11 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor memory devices

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030098509A1 (en) * 1999-09-27 2003-05-29 Kabushiki Kaisha Toshiba Semiconductor device, semiconductor element and method for producing same
US20030111732A1 (en) * 2001-12-13 2003-06-19 Akira Goda Superconductor device and method of manufacturing the same
EP1530237A2 (fr) * 2003-11-10 2005-05-11 Kabushiki Kaisha Toshiba Mémoire non-volatile à sémiconducteur
US20050266678A1 (en) * 2004-05-27 2005-12-01 Micron Technology, Inc. Source lines for NAND memory devices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030098509A1 (en) * 1999-09-27 2003-05-29 Kabushiki Kaisha Toshiba Semiconductor device, semiconductor element and method for producing same
US20030111732A1 (en) * 2001-12-13 2003-06-19 Akira Goda Superconductor device and method of manufacturing the same
EP1530237A2 (fr) * 2003-11-10 2005-05-11 Kabushiki Kaisha Toshiba Mémoire non-volatile à sémiconducteur
US20050266678A1 (en) * 2004-05-27 2005-12-01 Micron Technology, Inc. Source lines for NAND memory devices

Also Published As

Publication number Publication date
TW200739827A (en) 2007-10-16
TWI332252B (en) 2010-10-21
EP1958252A2 (fr) 2008-08-20
WO2007067860A2 (fr) 2007-06-14

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