WO2007043010A1

WO2007043010A1 - Non-volatile memory device with improved data retention

Info

Publication number: WO2007043010A1
Application number: PCT/IB2006/053724
Authority: WO
Inventors: Robertus T. F. Van Schaijk; Nader Akil; Michiel Slotboom
Original assignee: Nxp B.V.
Priority date: 2005-10-14
Filing date: 2006-10-10
Publication date: 2007-04-19
Also published as: JP2009512211A; CN101288181A; EP1946384A1; TW200735360A

Abstract

A non-volatile memory device on a semiconductor substrate comprises a semiconductor base, and a programmable memory transistor comprising a storage stack, a control gate, source and drain regions and a channel in between source and drain. The storage stack comprises a first insulating layer (9) , a trapping layer (10) and a second insulating layer (11) . The first layer is positioned above the channel, the trapping layer above the first layer and the second layer above the trapping layer. Next, the control gate is arranged above the storage stack. The storage stack is arranged for trapping charge in the trapping layer by tunneling of charge carriers from the channel through the first layer which comprises a high-K material. The high-K material has a relatively smaller difference between the barrier height energy for electrons and the barrier height energy for holes in comparison to the difference between the barrier height energies for electrons and for holes in silicon dioxide .

Description

Non- volatile memory device with improved data retention

FIELD OF THE INVENTION

The present invention relates to a non-volatile memory device. Moreover, the present invention relates to a method of manufacturing such a non-volatile memory device. Also, the present invention relates to a semiconductor device comprising at least one such non- volatile memory device.

BACKGROUND

Future generations of non- volatile semiconductor memories are expected to use a charge storing layer stack that consists of a charge trapping layer which is located between a first or bottom layer and a second or top insulating layer. Such a charge storage layer stack comprises a bottom silicon dioxide layer, a charge trapping silicon nitride layer and a top silicon dioxide layer, also known as an ONO stack. Semiconductor memory devices based on such an ONO stack as the charge storage layer are often referred to as SONOS (Semiconductor Oxide-Nitride-Oxide Semiconductor) memory devices.

In these non- volatile semiconductor devices having an ONO layer stack, charge can be stored in the silicon nitride layer by a mechanism of direct tunneling of electrons (Fowler-Nordheim) through the bottom silicon dioxide layer (tunnel-oxide layer) from the current carrying channel to the silicon nitride layer.

The charge trapping properties of the silicon nitride layer allow for downscaling the thickness of the tunnel-oxide layer, which may result in lower program/erase voltages.

Disadvantageously, nMOS SONOS memory devices (based on an n-type channel) suffer from read disturb and low quality of data retention.

Read disturb is closely linked to the so-called erase saturation effect. Erasure of charge (electrons) in the charge trapping layer is done by tunneling of holes through the bottom insulating layer and recombination of the tunneled holes with the electrons in the charge trapping layer. Due to the erase saturation effect, a parasitic electron current from the top insulating layer is generated, and relatively large currents flow through the bottom and top insulating layer, which can cause the bottom and top insulating layers to deteriorate. Over the lifetime of the memory device, erase actions create defects (so-called deep traps) that accumulate in the insulating layers. As a consequence, the level of the threshold voltage, which defines the memory state, or bit value, of the memory device (being either '0' or ' 1 ', depending on the actual voltage of the memory device being below or above the threshold voltage), tends to increase gradually over the lifetime of the device. Clearly, the erase- induced change of the threshold voltage has an harmful effect on read actions of the memory device.

Another issue with SONOS memories concerns the quality of data retention. To retain charge in the charge storage layer, the energy barrier of the insulating layer should be sufficiently high to retain charge in the charge trapping layer for longer periods. However, in SONOS memory devices with silicon dioxide insulating layers, the thickness of the bottom layer is strongly restricted to about 2 nm for reasons of usable program/erase actions. Due to the small thickness of the bottom insulating layer, retention of charge is not optimal. Thus, to improve said retention, it would be desirable, during the design phase, to define a relatively thicker bottom silicon dioxide layer, but the charge transport to/from the charge trapping layer should still rely on the mechanism of direct tunneling. However, if one increases the bottom silicon dioxide layer in SONOS memory devices, it is observed that programming is still possible, but erasing becomes virtually impossible due to the fact that erasure is based on the transport of holes (rather than electrons) through the bottom insulating layer and the barrier height for hole tunneling is larger than for electrons.

It is an object of the present invention to improve both the read disturb and data retention issues.

SUMMARY

The present invention relates to a non- volatile memory device on a semiconductor substrate, comprising a semiconductor base layer and at least a programmable memory transistor, the programmable memory transistor comprising a charge storage layer stack and a control gate; the semiconductor base layer comprising source and drain regions and a current carrying channel region being positioned in between the source and drain regions; the charge storage layer stack comprising a first insulating layer, a charge trapping layer and a second insulating layer, the first insulating layer being positioned above the current carrying channel region, the charge trapping layer being above the first insulating layer and the second insulating layer being above the charge trapping layer; the control gate being positioned above the charge storage layer stack; the charge storage layer stack being arranged for trapping charge in the charge trapping layer by direct tunneling of charge carriers from the current carrying channel region through the first insulating layer, wherein the first insulating layer comprises a high-K material which has a relatively smaller energy level difference between a barrier height for electrons and a barrier height for holes in comparison to the energy level difference between the barrier height for electrons and the barrier height for holes in silicon dioxide.

Advantageously, the present invention allows the use of a relatively thicker bottom insulating layer, which improves the capability of retention of charge in the charge trapping layer. At the same time, the capability of erasing the charge stored in the charge trapping layer by the mechanism of holes tunneling through the thicker bottom insulating layer may be maintained, since the energy level of the barrier height for tunneling of holes is reduced. This allows the use of a lower read voltage, and hence a reduction of the read disturb effect.

Also, the present invention relates to a method of manufacturing a non-volatile memory device on a semiconductor substrate, comprising a semiconductor base layer and at least a programmable memory transistor as described above, wherein the method comprises: depositing as the first insulating layer (9) a high-K material which has a relatively improved symmetry of a barrier height for electrons and a barrier height for holes in comparison to the barrier heights for electrons and holes in silicon dioxide.

Also, the present invention relates to a memory array comprising at least one non- volatile memory device as described above.

Moreover, the present invention relates to a semiconductor device comprising at least one non- volatile memory device as described above

BRIEF DESCRIPTION OF THE DRAWINGS

For the purpose of teaching of the invention, an embodiment of the method and devices of the invention are described below. It will be appreciated by the person skilled in the art that other alternative and equivalent embodiments of the invention can be conceived and reduced to practice without departing form the true spirit of the invention, the scope of the invention being limited only by the appended claims. Figure 1 shows schematically an embodiment of a non- volatile memory device which comprises a charge storage layer stack;

Figure 2 schematically shows an energy barrier diagram for a SONOS memory device of the prior art;

Figure 3 schematically shows an energy barrier diagram for a SONOS memory device of the present invention;

Figure 4 shows a normalized threshold voltage window as a function of retention time;

Figure 5 shows the endurance of an enhancement-type transistor SONOS memory device.

DETAILED DESCRIPTION OF EMBODIMENTS

Figure 1 shows schematically an embodiment of a non- volatile memory device which comprises a charge storage layer stack.

The embodiment of the non- volatile memory device, shown as an example, is a planar two -transistor structure 1 on a semiconductor substrate 2. The transistor structure 1 comprises an access transistor Tl and a programmable memory transistor T2

The access transistor Tl comprises a first source/drain region 3a, a second source/drain region 3b, an access gate AG 4 and spacers 5. The access gate AG 4 is defined to overlap a channel region Cl between the first and second source/drain regions 3a, 3b. The spacers 5 are defined to cover the sidewalls of the access gate material 4. It is noted that in relation to the present invention, the access transistor, its detailed features, and its configuration with respect to the programmable memory transistor T2 are shown only as a non-limiting example, are not relevant to the present invention and will not be described further.

The programmable memory transistor T2 comprises a control gate CG, the second source/drain region 3b and a third source/drain region 3c. The control gate CG is defined to overlap a second channel region C2 between the second source/drain region 3b and the third source/drain region 3c. The control gate CG comprises a charge storage layer stack CT and a gate material 6. Further, the control gate CG may comprise a contact layer 7 on top of the gate material 6. Spacers 8 cover the sidewalls of the control gate CG. The gate material 6 may, for example, be (doped) poly-Si. The contact layer 7 may, for example, be (doped) poly-Si, a suicide compound or a metal. The charge storage layer stack CT comprises a bottom insulating layer 9, a charge trapping layer 10 and a top insulating layer 11.

In the related art, the charge storage layer CT comprises a silicon dioxide layer as bottom insulating layer 9, a silicon nitride layer as charge trapping layer 10 and a silicon dioxide layer as top insulating layer 11, also known as ONO stack. Hence, semiconductor memory devices based on such an ONO stack are known as SONOS non- volatile memory devices.

Figure 2 schematically shows an energy barrier diagram for a SONOS memory device of the prior art.

In the diagram, in the horizontal direction, the position of the second channel region C2 and each layer 9, 10, 11 in the charge storage layer stack CT is indicated as a vertical bar. In the vertical direction, an energy level is schematically depicted. A conduction band level bl and a valence band level b2 are shown. The height of each bar indicates the relative energy level of the corresponding layer in the stack 9, 10, 11, the width of each bar indicates the thickness of the respective layer. The upward arrow indicates the barrier height for electrons (relative to bl), the downward arrow indicates the barrier height for holes (relative to b2).

In the ONO stack 9, 10, 11 of the SONOS memory device 1, for electrons that tunnel from the second channel region C2 through the bottom silicon dioxide layer 9 to the silicon nitride charge trapping layer 10 the barrier height is about 3.1 eV. For holes the barrier height is between 4 and 5 eV, typically about 4.8 eV. Since the top insulating layer also comprises a silicon dioxide layer 11, the barrier height is basically the same as for the bottom silicon dioxide layer 9.

Clearly, the energy level of the (silicon nitride) charge trapping layer 10 is to be somewhat lower than the energy level of the bottom insulating layer 9 and top insulating layer 11, respectively, to avoid (spontaneous) leakage from the charge trapping layer 11.

As described above, the thickness of the bottom silicon dioxide layer 9 is a compromise between the programming and erasure performance by electrons and holes, respectively, with a non-optimal charge retention. An improvement of the reliability of the SONOS memory device of the prior art (i.e. a better retention) would be possible by an increase of the thickness of the bottom silicon dioxide layer 9.

For example, in SONOS memory devices of the prior art, the bottom silicon dioxide layer 9 typically has a thickness of 2.0 nm. For improvement of the data retention an increase of the oxide thickness to 3.0 nm would be desirable. However, this would relatively strongly affect erase actions by tunneling of holes, while programming by tunneling of electrons would only be slightly affected due to the asymmetry of the barrier height levels for electrons and holes.

It is considered that a reduction of the asymmetry between the barrier height for electrons and for holes would allow both programming and erasure at a thicker bottom insulating layer.

Figure 3 schematically shows an energy barrier diagram for a SONOS memory device of the present invention.

In the present invention, at least the bottom silicon dioxide layer is replaced by high-K materials, which will be described below in more detail.

The high-K materials for at least the bottom layer are selected to have a relatively improved symmetry of the barrier height for electrons and for holes in comparison to the barrier heights for electrons and holes in silicon dioxide, or, in other words, they are selected to obtain a barrier height for electron tunneling and a barrier height for hole tunneling which differ less than the barrier heights for electrons and holes in silicon dioxide, say about 30% or less. As a consequence of the improved barrier height symmetry, data retention is advantageously improved by allowing a relative increase of the thickness of the bottom high-K layer, while at the same time erasure of charge remains possible due to the relatively lower barrier height for holes.

It is noted that the high-K material of choice may not exhibit a barrier height for electrons that is too low in order to avoid leakage of charge from the charge trapping layer 11.

Furthermore, such high-K materials may be selected to have a relatively wide composition range, which would allow a variation and/or tuning of the relevant (e.g., physical, chemical, or electronic) properties of the high-K material as a function of the composition.

In an embodiment, the bottom insulating layer 9 of the charge storage layer stack contains Hafnium silicate. It is noted that the Hafnium silicate compound may have either a stoichiometric (HfSiO₄) or a non- stoichiometric composition (denoted as: HfSiO). For reason of clarity, in the following both compositions will be denoted by the stoichiometric compound.

The magnitude of the barrier height for electrons or holes of this HfSiO compound can be varied and tuned by the silicon content of the HfSiO compound. In a further embodiment, the high-K material is nitrided Hafnium silicate HfSiO₄(N), which, through decoration of defects in the high-K material by nitrogen, may provide an improved quality (i.e., physical/chemical stability) of the bottom insulating layer 9. Moreover, it is observed that the nitridation of the HfSiO₄ layer advantageously reduces the barrier height for hole tunneling even further and brings it closer to the barrier height level for electron tunneling, making the barrier heights for electrons and holes even more symmetric. Again, it is noted that the nitrided Hafnium silicate compound may have either a stoichiometric or a non- stoichiometric composition. Below, both compositions will be denoted by the stoichiometric compound.

More specifically, by varying the Si content of Hafnium silicate, with a silicon content of about x=0.77, the barrier height for electrons in Hf^_xSi_xO₂, with 0< x < 1, is between about 2.5 and about 3.1 eV, the barrier height for holes is between about 3.0 and about 3.6 eV. (Note that Hf^_xSi_xO₂ denotes a stoichiometric compound with variable Si content; in the present invention this compound with variable Si content may also be non- stoichio metric).

With a lower Si content of the (nitrided) Hafnium silicate compound, the barrier height for electrons will become lower, and the barrier height for holes will become higher.

The K-value of this Hf^_xSi_xO₂ layer (with a silicon content of x~0.77) will be about K~6. (Silicon dioxide: K~4.) It is noted that to ensure that, during use, the electrical potential is localized mainly across the bottom (nitrided) Hafnium silicate insulating layer, the top insulating layer 11 may have a similar or larger K-value.

Thus, in the SONOS memory device of the present invention the top insulating layer 11 may consist of a high-K material with a larger K-value than the K-value of the bottom insulating layer 9.

In an embodiment, the top high-K material is Hf^_xSi_xO₂ with a Si content of x~0.47. The K-value of this compound is about K~12. Again, the top high-K material may be nitrided.

For example, a SONOS memory device comprising a charge storage layer stack with high-K insulating layers may comprise a bottom Hfi__xSi_xθ₂(N) layer 9, with the silicon content between x~0.60 and x~0.90 and a thickness between about 2 and about 6 nm, and a charge trapping silicon nitride layer 10 with a thickness of about 4 to about 10 nm. The top insulating layer 11 may be a Hfi__xSi_xθ₂(N) layer with the same or a higher K-value and a larger thickness than the bottom high-K layer. Other high-K materials for the top insulating layer 11 may be used as well, for example, ZrO₂ and its silicates, HfO₂, Ta₂Os, Al₂θ3, Hf_xAlyO_z, and X-SCO3 (with X=Gd, Dy or La). It is noted that the barrier height of the selected high-K material may not be too low so as to avoid leakage of charge.

As a result of using a high-K material, such as Hf_0.23Sio_.77θ₂(N), in comparison with the silicon dioxide layer of the prior art (K~4), at a given applied potential a smaller electric field will be across the Hfo.₂3Sio.77θ₂(N) bottom layer 9 than would be across a silicon dioxide layer with the same thickness. Thus, the tunnel current will be lower in the SONOS memory device of the present invention. But, due to the relatively large reduction of especially the hole-barrier height in comparison to the barrier height of a silicon dioxide layer with the same thickness, an improvement of the erase efficiency results in a relatively larger threshold voltage (VT) window for a HfSiO₄(N) layer than for a silicon dioxide layer. The threshold voltage window is defined here as the difference between the programming voltage Vp and the erasure voltage Ve.

The larger VT window can be used to increase the thickness of the bottom insulating Hfi__xSi_xO₂(N) layer and improve the retention of the charge trapping layer.

Figure 4 shows a normalized threshold voltage window as a function of retention time.

In Figure 4, a SONOS memory device with a 2.2 nm silicon dioxide bottom layer 9 is compared with a SONOS memory device with a 4.0 nm (nitrided) Hfo.₂3Sio.₇₇0₄. In the horizontal direction the retention time is plotted. In the vertical direction the normalized voltage threshold window ΔVT is plotted. For each SONOS memory device (with either a silicon dioxide layer or a HfSiO layer as bottom insulating layer 9), the VT window is normalized with respect to the initial VT window value.

For the SONOS memory device with a silicon dioxide layer 9, ΔVT is plotted as a dashed curve. ΔVT for the Hafnium Silicate based SONOS memory device is plotted as a solid curve. The extrapolation for both curves to a retention time of 10 years is plotted as a dash-dotted line. As shown in Figure 4, in the course of time, ΔVT decreases gradually for each type of SONOS memory device. The extrapolated retention towards ten years gives a resulting window of 45% for a silicon dioxide layer 9 and 75% for a Hfo.₂3Sio.77θ₂ layer 9.

In Figure 5, an endurance measurement for a SONOS memory device with a 4.0 nm Hfo.₂3Sio.77θ₂ bottom dielectric layer 9 is shown. The SONOS memory device is an enhancement-type transistor, i.e., at a gate voltage of zero Volt, the drain current of the device is nil; the device is in an off-state.

In the plot of Figure 5, the threshold voltage for programming Vtp and the threshold voltage for erasure Vte are depicted as a function of the number of program/erase cycles PE. The magnitude of the programming voltage Vp is 12V for 0.5 ms. The magnitude of the erasure voltage Ve is -13V for 0.5 ms. As shown, the threshold voltage for programming Vtp is ~5V and the threshold voltage for erasure Vte is -2.5V, which requires the use of a high read voltage of about 3.5V.

Please note that in many applications with conditions as shown in Figure 5, a boosting circuit may be applied to obtain the read voltage of about 3.5V. Particularly for low power applications, this would be a disadvantage.

As shown in Figure 5, the threshold voltage for programming Vtp and the threshold voltage for erasure Vte gradually increase with the number of program/erase cycles, due to the described erase saturation effect. However, the VT window changes gradually from about 2.5V to about 1.8V (-72%). One may observe that for about 1E6 (1 million) PE cycles, difficulties for reading may occur due to the decreasing difference between the threshold voltage for erasure Vte and the read voltage. In practice, this condition would indicate the end of lifetime of the device.

Summarizing, with respect to Figure 5, an enhancement-type SONOS memory device with a 4.0 nm Hfo.23Sio.77O2 bottom insulating layer 9 shows a significantly improved retention. However, the read disturb (erase saturation), although improved, may remain an issue.

To overcome the read disturb more completely, it is considered to use a SONOS memory device based on a depletion-type transistor, which would allow a non-zero drain current at a gate voltage of zero Volt.

Advantageously, both the threshold voltage for programming Vtp and the threshold voltage for erasure Vte are lower in a depletion type transistor, thus the upper and lower boundaries of the VT window would each shift to a lower value.

Moreover, the read voltage can be reduced significantly. In principle, the read voltage can be zero Volt. For practical reasons, a read voltage of about IV could be used, which would cause virtually no read disturb. Also, no boosting circuitry would be needed to generate this voltage in devices of the 65 nm generation and smaller. For low-power applications, omitting boosting circuitry may enhance energy saving in such applications significantly. Also, it is noted that in comparison to the application of a silicon dioxide bottom dielectric 9, the application of a high-K bottom dielectric layer 9 would result in a lower mobility of carriers due to a less complete passivation of interface traps between the bottom dielectric layer 9 and the semiconductor channel region C2. However, a depletion- type SONOS memory device comprises a buried channel region C2, in which scattering of carriers on interface states at the interface of the bottom dielectric 9 and the semiconductor substrate 2 is strongly reduced. In fact, the mobility of a depletion type SONOS memory device may be increased in comparison to the mobility of an enhancement-type SONOS memory device.

In depletion-type SONOS memory devices it may be observed that the maximum transconductance is higher than for the enhancement-type device due to a higher mobility in the depletion-type SONOS memory device.

Normally, in enhancement-type devices, if one replaces the SiO₂ bottom dielectric with another dielectric, e.g. a high-K material, a severe decrease in mobility is observed. In depletion-type devices, however, such a replacement will result in a relatively higher read current.

Therefore, the SONOS memory device according to the present invention may be embodied by a programmable memory transistor T2 which is created as a depletion-type transistor.

In a SONOS memory device according to the present invention, the charge storage layer stack CT may be manufactured by way of the following method, which is to be regarded as a non- limiting example of manufacturing such a non- volatile memory device.

A semiconductor substrate 2 is provided. On the semiconductor substrate 2 active areas (comprising C2) are defined. Note that the characteristics of the active regions C2 and the substrate 2 are such that the programmable memory transistor T2 may be a depletion-type transistor.

Next, a deposition of the bottom high-K dielectric 9 Hfi__xSi_x0₂ in blanket mode is carried out. The deposition technique may be, for example, MOCVD (metal-organic chemical vapor deposition) or ALD (atomic layer deposition). The composition of the Hfi_ _xSi_x0₂(N) is controllable to allow a silicon content x between about 0.6 and about 0.9. The thickness may be between about 2 and about 6 nm.

Then, an annealing step may be carried out while at the same time nitrogen is provided to the high-K layer Hfi__xSi_x0₂ to form a nitrided high-K layer Hfi__xSi_x0₂(N). Nitrogen can be supplied by any conceivable precursor (for example, by supply of NH3). The annealing temperature may be between about 600 and about 900 °C.

Subsequently, the charge trapping layer 10, which typically comprises silicon nitride, is deposited by any suitable method known in the art, for example by a CVD process or a PVD process. The thickness of the charge trapping layer 10 is between about 4 and about 10 nm. Alternatively, another charge trapping layer material may be applied here, e.g. a layer of silicon nano-crystals or a high-K material layer.

Then, the top insulating layer 11 is deposited. This top layer 11 consists of a further high-K material, for example also HfU_xSi_xO₂(N). The thickness is at least equal to, or larger than, the thickness of the bottom high-K layer 9, depending on the K- value of the top dielectric layer 11 in comparison to the K- value of the bottom high-K dielectric layer 9. In the case of HfU_xSi_xO₂(N), the layer is deposited in a similar fashion as the bottom HfU_xSi_xO₂(N) dielectric layer 9. Alternatively, other high-K materials may be used, for example ZrO₂ and its silicates HfO₂, Ta₂O₅ ,Al₂O₃, Hf_xAl_yO_z, and X-ScO₃ (with X=Gd, Dy or La).

In a further step, a blanket poly-Si layer to form control gate materials 6 is deposited by a method known in the art. Alternatively, the control gate material 6 may comprise an intermetallic compound like a metal-silicide comprising for example Titanium, Tantalum or Cobalt as a metal, or a metal compound such as TiN or TaN.

Next, a blanket metal layer may be provided as contact layer 7.

Then, the blanket layers are patterned by suitable lithographic processing to form the bodies of the programmable memory transistor T2. Additionally, spacers 8 are formed on the sidewalls of the body of the programmable memory transistor T2.

Further, as known to persons skilled in the art, source/drain regions may be formed, and during back-end processing, a passivation layer may be deposited to cover the transistor structure 1 , contacts to source/drain regions and to access and control gates may be created, and interconnect wiring may be provided by some metallisation process(es).

Claims

CLAIMS:

1. Non- volatile memory device (1) on a semiconductor substrate, comprising a semiconductor base layer (2) and at least a programmable memory transistor (T2), the programmable memory transistor (T2) comprising a charge storage layer stack (CT) and a control gate (6; 6, 7); the semiconductor base layer (2) comprising source and drain regions (3b, 3c) and a current carrying channel region (C2) being positioned in between the source and drain regions (3b, 3c); the charge storage layer stack (CT) comprising a first insulating layer (9), a charge trapping layer (10) and a second insulating layer (11), the first insulating layer (9) being positioned above the current carrying channel region (C2), the charge trapping layer (10) being above the first insulating layer (9) and the second insulating layer (11) being above the charge trapping layer (10); the control gate (6, 7) being positioned above the charge storage layer stack (CT); the charge storage layer stack (CT) being arranged for trapping charge in the charge trapping layer (10) by direct tunneling of charge carriers from the current carrying channel region (C2) through the first insulating layer (9), wherein the first insulating layer (9) comprises a high-K material which has a relatively smaller energy level difference between a barrier height for electrons and a barrier height for holes in comparison to the energy level difference between the barrier height for electrons and the barrier height for holes in silicon dioxide.

2. Non- volatile memory device (1) on a semiconductor substrate according to claim 1 , wherein the programmable memory transistor (T2) is a depletion-type transistor.

3. Non- volatile memory device (1) on a semiconductor substrate according to claim 1 or 2, wherein the high-K material for the first insulating layer (9) has a relatively wide composition range, and is arranged for variation and/or tuning of barrier height properties of the high-K material as a function of a variation of the composition.

4. Non- volatile memory device (1) on a semiconductor substrate according to any one of the preceding claims 1, 2 or 3, wherein the high-K material for the first insulating layer (9) contains Hafnium silicate (Hfi__xS I_xO₂).

5. Non- volatile memory device (1) on a semiconductor substrate according to claim 4, wherein the barrier height for electrons and the barrier height for holes are varied and tuned by varying the silicon content x of the Hfi__xSi_xO₂ compound relative to the hafnium content, with 0 < x < 1.

6. Non- volatile memory device (1) on a semiconductor substrate according to claim 4 or 5, wherein the Hafnium silicate compound is a nitrided Hafnium silicate (HfL_xSi_xO₂(N)).

7. Non- volatile memory device (1) on a semiconductor substrate according to any one of the claims 4 - 6, wherein the Hafnium silicate compound for the first insulating layer (9) comprises a silicon content between about x=0.60 and about x=0.90.

8. Non- volatile memory device (1) on a semiconductor substrate according to any one of the claims 4 - 7, wherein the Hafnium silicate compound for the first insulating layer (9) comprises a silicon content of about x=0.77.

9. Non- volatile memory device (1) on a semiconductor substrate according to any one of the claims 4 - 8, wherein the barrier height for electrons is between about 2.5 and about 3.1 eV and the barrier height for holes is between about 3.0 and about 3.6 eV.

10. Non- volatile memory device (1) on a semiconductor substrate according to any one of the claims 4 - 9, wherein a K- value of the high-K material for the first insulating layer (9) is between K ~ 4 and K ~ 8.

11. Non- volatile memory device (1) on a semiconductor substrate according to any preceding claim, wherein the second insulating layer (11) comprises a second high-K material, the second high-K material having a K- value which is substantially equal to, or greater than, the K- value of the high-K material for the first insulating layer (9).

12. Non- volatile memory device (1) on a semiconductor substrate according to claim 11, wherein the second high-K material for the second insulating layer (11) comprises Hafnium silicate (Hfi__xS I_xO₂).

13. Non- volatile memory device (1) on a semiconductor substrate according to claim 12, wherein the silicon content of the Hafnium silicate (HfU_xSi_xO₂) of the second high- K material is lower than the silicon content of the high-K material for the first insulating layer.

14. Non- volatile memory device (1) on a semiconductor substrate according to claim 12 or 13, wherein the silicon content of the Hafnium silicate (Hfi__xSi_x0₂) of the second high-K material is about x=0.47.

15. Non- volatile memory device (1) on a semiconductor substrate according to claim 11, wherein the second high-K material comprises one of ZrO₂ and its silicates HfO₂, Ta₂O₅ ,Al₂O₃, Hf_xAl_yO_z, or X-ScO₃, with X being one of Gd, Dy or La.

16. Non- volatile memory device (1) on a semiconductor substrate according to any one of the claims 4 to 15, wherein the first insulating layer (9) has a thickness between about 2 nm and about 6 nm.

17. Method of manufacturing a non- volatile memory device (1) on a semiconductor substrate, comprising a semiconductor base layer (2) and at least a programmable memory transistor (T2), the programmable memory transistor (T2) comprising a charge storage layer stack (CT) and a control gate (6; 6, 7); the semiconductor base layer (2) comprising source and drain regions (3b, 3c) and a current carrying channel region (C2) being positioned in between the source and drain regions (3b, 3c); the charge storage layer stack (CT) comprising a first insulating layer (9), a charge trapping layer (10) and a second insulating layer (11), the first insulating layer (9) being positioned above the current carrying channel region (C2), the charge trapping layer (10) being above the first insulating layer (9) and the second insulating layer (11) being above the charge trapping layer (10); the control gate (6, 7) being positioned above the charge storage layer stack (CT); the charge storage layer stack (CT) being arranged for trapping charge in the charge trapping layer (10) by direct tunneling of charge carriers from the current carrying channel region (C2) through the first insulating layer (9), wherein the method comprises: a programmable memory transistor, deposition of a high-K material as the first insulating layer (9), which has a relatively improved symmetry of the barrier height for electrons and the barrier height for holes in comparison to the barrier heights for electrons and holes in silicon dioxide.

18. Method of manufacturing a non- volatile memory device (1) on a semiconductor substrate according to claim 17, wherein the method further comprises:

- providing a depletion-type transistor as the programmable memory transistor (T2).

19. Memory device array comprising at least one non- volatile memory device in accordance with any one of the preceding claims 1 to 16.

20. Semiconductor device comprising at least one non-volatile memory device in accordance with any one of the preceding claims 1 to 16.