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WO2006124235A1 - Dispositif de memoire resistive avec retention amelioree des donnees et consommation electrique reduite - Google Patents

Dispositif de memoire resistive avec retention amelioree des donnees et consommation electrique reduite Download PDF

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Publication number
WO2006124235A1
WO2006124235A1 PCT/US2006/016185 US2006016185W WO2006124235A1 WO 2006124235 A1 WO2006124235 A1 WO 2006124235A1 US 2006016185 W US2006016185 W US 2006016185W WO 2006124235 A1 WO2006124235 A1 WO 2006124235A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory device
active layer
state
electrode
memory
Prior art date
Application number
PCT/US2006/016185
Other languages
English (en)
Inventor
An Chen
Sameer Haddad
Tzu-Ning Fang
Original Assignee
Spansion Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Spansion Llc filed Critical Spansion Llc
Priority to EP06758720A priority Critical patent/EP1883930A1/fr
Priority to JP2008511151A priority patent/JP4731601B2/ja
Publication of WO2006124235A1 publication Critical patent/WO2006124235A1/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0009—RRAM elements whose operation depends upon chemical change
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/009—Write using potential difference applied between cell electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/10—Resistive cells; Technology aspects
    • G11C2213/12—Non-metal ion trapping, i.e. using memory material trapping non-metal ions given by the electrode or another layer during a write operation, e.g. trapping, doping
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/10—Resistive cells; Technology aspects
    • G11C2213/15—Current-voltage curve
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/34—Material includes an oxide or a nitride
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/50—Resistive cell structure aspects
    • G11C2213/56—Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor

Definitions

  • This invention relates generally to memory devices, and more particularly, to resistive memory device operation and resistive memory structure.
  • Storage devices include long term storage mediums such as, for example, hard disk drives, compact disk drives and corresponding media, digital video disk (DVD) drives, and the like.
  • the long term storage mediums typically store larger amounts of information at a lower cost, but are slower than other types of storage devices.
  • Storage devices also include memory devices, which are often, but not always, short term storage mediums.
  • Memory devices tend to be substantially faster than long te ⁇ n storage mediums. Such memory devices include, for example, dynamic random access memory (DRAM), static random access memory (SRAM), double data rate memory (DDR), flash memory, read only memory (ROM), and the like. Memory devices are subdivided into volatile and non- volatile types. Volatile memory devices generally lose their information if they lose power and typically require periodic refresh cycles to maintain their information. Volatile memory devices include, for example, random access memory (RAM), DRAM, SRAM and the like. Non-volatile memory devices maintain their information whether or not power is maintained to the devices.
  • DRAM dynamic random access memory
  • SRAM static random access memory
  • DDR double data rate memory
  • ROM read only memory
  • Memory devices are subdivided into volatile and non- volatile types. Volatile memory devices generally lose their information if they lose power and typically require periodic refresh cycles to maintain their information. Volatile memory devices include, for example, random access memory (RAM), DRAM, SRAM and the like. Non-volatile memory devices maintain
  • Non-volatile memory devices include, but are not limited to, ROM, programmable read only memory (PROM), erasable programmable read only memory (EPROM), flash memory and the like. Volatile memory devices generally provide faster operation at a lower cost as compared to non-volatile memory devices.
  • Memory devices generally include arrays of memory cells. Each memory cell can be accessed or “read”, “written”, and “erased” with information. The memory cells maintain information in an “off or an “on” state, also referred to as “0" and "1". Typically, a memory device is addressed to retrieve a specified number of byte(s) (e.g., 8 memory cells per byte). For volatile memory devices, the memory cells must be periodically "refreshed” in order to maintain their state. Such memory devices are usually fabricated from semiconductor devices that perform these various functions and are capable of switching and maintaining the two states. The devices are often fabricated with inorganic solid state technology, such as, crystalline silicon devices. A common semiconductor device employed in memory devices is the metal oxide semiconductor field effect transistor (MOSFET).
  • MOSFET metal oxide semiconductor field effect transistor
  • non-volatile memory devices Digital cameras, digital audio players, personal digital assistants, and the like generally seek to employ large capacity non-volatile memory devices (e.g., flash memory, smart media, compact flash, and the like). Because of the increasing demand for information storage, memory device developers and manufacturers are constantly attempting to increase storage capacity for memory devices (e.g., increase storage per die or chip).
  • a postage-stamp-sized piece of silicon may contain tens of millions of transistors, each transistor as small as a few hundred nanometers. However, silicon-based devices are approaching their fundamental physical size limits. Inorganic solid state devices are generally encumbered with a complex architecture which leads to high cost and a loss of data storage density.
  • Non-volatile semiconductor devices have a reduced data rate and relatively high power consumption and large degree of complexity. Typically, fabrication processes for such cells are also not reliable. Therefore, there is a need to overcome the aforementioned deficiencies.
  • FIG. 1 illustrates a type of memory device 30, which includes advantageous characteristics for meeting these needs.
  • the memory device 30 includes an electrode 32 (for example copper), a copper sulfide layer 34 on the electrode 32, an active layer 36, for example a copper oxide layer, on the layer 34, and an electrode 38 (for example titanium) on the active layer 36.
  • an electrode 32 for example copper
  • a copper sulfide layer 34 on the electrode 32
  • an active layer 36 for example a copper oxide layer
  • an electrode 38 for example titanium
  • an electrical potential V r (the "read” electrical potential) is applied across the memory device 30 from a higher to a lower electrical potential in the forward direction of the memory device 30.
  • This electrical potential is less than the electrical potential V pg applied across the memory device 30 for programming (see above).
  • the memory device 30 will readily conduct current (Ll), which indicates that the memory device 30 is in its programmed state.
  • a positive voltage is applied to the electrode 38, while the electrode
  • V er the "erase” electrical potential
  • This potential is sufficient to cause copper ions to be repelled from the active layer 36 toward the electrode 32 and into the layer 34 (C), causing the active layer 36 (and the overall memory device 30) to be in a high- resistance or substantially non-conductive state. This state remains upon removal of such potential from the memory device 30.
  • the electrical potential V r is again applied across the memory device 30 from a higher to a lower electrical potential in the forward direction of the memory device 30, as described above.
  • the active layer 34 (and memory device 30) in a high-resistance or substantially non-conductive state the memory device 30 will not conduct significant current (L2), which indicates that the memory device 30 is in its erased state.
  • the memory device when programmed, be capable of retaining its programmed state for a long period of time, i.e., until it is desired that the state be changed to its erased state.
  • the memory device when erased, be capable of retaining that state for a long period of time as chosen. While the above described device is effective in operation, it has been found that over a period of time, the conductive filaments formed in the programmed device can break down, causing the conductivity of the memory device to be significantly reduced, so that the memory device undesirably loses its programmed state. It will be understood that it is highly desirable for the device to be capable of stably retaining its programmed and erased states as desired.
  • program and erase operations described above require a relatively high current, in turn resulting in relatively high energy consumption. It will also be understood that it is desirable to decrease program and erase currents, to in turn reduce power consumption. It will also be understood that it is desirable to improve switching speeds of the device.
  • the present method is for changing the state of a memory device, the memory device having a first electrode, a passive layer on and in contact with the first electrode, an active layer on and in contact with the passive layer, and a second electrode on and in contact with the active layer.
  • Programming of the device into a low resistance state involves moving electronic charge carriers into the active layer to increase the conductivity thereof
  • erasing of the device into a high resistance state involves moving electronic charge carriers from the active layer to decrease the conductivity thereof.
  • Figure 1 is a cross-sectional view of an above-described memory device
  • Figure 2 is a plot of current vs. voltage illustrating operating characteristics of the memory device of Figure 1;
  • Figure 3 is a cross-sectional view of a first embodiment of the present memory device
  • Figure 4 is a cross-sectional view of the memory device of Figure 3 as part of an integrated circuit
  • Figures 5-8 illustrate programming and erasing of the memory device of Figure 3 in accordance with the present method
  • Figure 9 is a plot of current vs. voltage illustrating operating characteristics of the memory device of Figure 3, in accordance with the present method of Figures 5-8;
  • Figure 10 is a graph illustrating current and voltage in programming and reading the state of the device of Figure 3;
  • Figure 11 is a graph illustrating data retention of the device of Figure 3 when practicing the present method.
  • Figures 12-15 illustrate programming and erasing of a second embodiment of memory device in accordance with the present method.
  • Figure 3 illustrates a first embodiment of memory device 130 for use in the present invention.
  • a copper electrode 132 is formed.
  • the surface thereof is sulfidized using H 2 S, elemental S or aqueous Ammonium Sulfate to form a 20 - 100 angstroms thick Cu 2 S passive layer 134 on and in contact with the electrode 132.
  • the surface of the layer 134 is oxidized to form a 30 - 200 angstroms thick copper oxide active layer 136 on and in contact with the passive layer 134.
  • This manufacturing process forms deep charge carrier traps in the active layer 136.
  • a titanium electrode 138 is formed on and in contact with the active layer 136 by for example DC or RF sputtering or by evaporation.
  • Figure 3 illustrates the fabricated memory device 130, wherein the layers 134, 136 are formed between the electrodes 132, 138.
  • Figure 4 illustrates the memory device 130 as part of a larger electronic structure 150.
  • the structure 150 includes a semiconductor substrate 152 having formed therein the source and drain of a transistor 140.
  • a dielectric layer 154 which in turn has a nitride layer 160 thereon.
  • Copper plugs 164, 166 extend through the dielectric and nitride layers 154, 160 and contact the source and drain of the transistor 140.
  • Electrode 138 is formed on the active layer 136, so that the overall memory device 130 is formed.
  • An electrode 174 is formed in contact with the copper plug 172. It will be seen that the memory device 130 is connected in series with the transistor 140. Figures 5-8 illustrate this configuration and also illustrate the present method.
  • a positive voltage V pg i is applied to the electrode 138, while the source of the transistor 140 is connected to ground, so that an electrical potential is applied across the electrodes 138, 132 from a higher to a lower potential in the direction from the electrode 138 to the electrode 132 (and in the direction from active layer 136 to the passive layer 134).
  • the voltage V g i applied to the gate of the transistor 140 is set to a level so as to limit current through the device 130 during the programming operation.
  • the programming operation causes electronic charge carriers, i.e., electrons and/or holes, to move into and be held by the preexisting traps in the active layer 136.
  • the electronic charge carriers may be electrons, holes, or a combination of electrons and holes.
  • the movement of these electronic charge carriers causes the active layer 136 (and the overall memory device 130) to adopt and be in a low-resistance or conductive state, i.e., a programmed state.
  • the electronic charge carriers drawn into the active layer 136 during the programming step remain in and are held by the deep traps, so as to remain in the active layer 136, so that the active layer 136 (and memory device 130) remain in a conductive or low- resistance state.
  • ground is applied to the electrode 138, while a positive voltage V er i is applied to the source of the transistor 140, so that an electrical potential is applied across the electrodes 138, 132 from a higher to a lower potential in the direction from the electrode 132 to the electrode 138 (and in the direction from the passive layer 134 to the active layer 136).
  • the voltage V g2 of the gate of the transistor 140 is set to a level so as to limit current through the device 130 during the erase operation. This operation causes the electronic charge carriers to move from the active layer 136. The movement of these electronic charge carriers causes the active layer 136 (and the overall memory device 130) to be in a high- resistance state or erased state. Upon removal of such potential, this erased state is maintained so that the active layer 136 (and memory device 130) remain in an erased or high-resistance state.
  • the switching from erased to programmed state is very rapid (see Figure 10), and the current limiting transistor 140, with gate set at for example 2.0 volts, limits the current in the programming operation to a very low level (illustrated as approximately 45 ⁇ a in Figure 9).
  • the current limiting transistor 140 With the current limiting transistor 140 gate voltage set at for example 4.0 volts, and because of the very low erase voltage, the current in the erase operation is very low. Thus, rapid switching and low power usage are achieved. As illustrated in Figure 9, the device (both programmed and erased) exhibits non-linear current characteristics (see curves A and B). This non-linear characteristic results from space-charge-limited-current conduction within the device 130.
  • read current through the device 130 drops only very slightly over a very long period of time. This clearly indicates that the programmed device 130 retains its conductive, i.e., programmed state over a very long period of time.
  • FIG. 12-15 illustrate a second embodiment of the invention.
  • This memory device 230 includes a copper electrode 232, a copper oxide active layer 234 on and in contact with the copper electrode 232 (formed by oxidation of the copper electrode), and a titanium electrode 236 on and in contact with the active layer 234, so that the active layer 234 is between the electrodes 232, 236.
  • the device 230 is provided in series with a current limiting transistor 240 as described above. Similar to the previous embodiment, in programming the memory device 230, a positive voltage V pg2 is applied to the electrode 236, with ground applied to electrode
  • Reversing the electrical potential i.e., applying positive voltage V er2 to the electrode 236 with ground applied to the electrode 232
  • an electrical potential is applied across the device 230 from higher to lower potential in the direction from the electrode 232 to the electrode 236, so that the electronic charge carriers to leave the active layer 234, so that the overall memory device 230 adopts and is in a high-resistance (erased) state.
  • the switching from one state to the other is very rapid, and the transistor 240, using selected gate voltages V g3 , V g4 respectively, acts to limit current through the device 230 to ensure low-power operation.
  • the process of forming the active layer itself causes traps to be formed in the active layer.
  • the active layers are undoped in the sense that they are formed with the intention of being undoped, and that introduction of dopants is not necessary for practice of the invention. It will be seen that herein is provided an approach wherein a memory device may be switched from one state to another in a very rapid manner, with very low power. Using this approach, the memory device is capable of maintaining its selected state in a stable manner for a very long period of time.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

La présente invention concerne un procédé pour la programmation d'un dispositif de mémoire résistive (130, 230), le dispositif de mémoire résistive (130, 230) comprenant une première électrode (132, 232), une seconde électrode (138, 236), et une couche active (136, 234) entre les première et seconde électrodes (132, 138 ou 232, 236). Dans le procédé de programmation, un potentiel électrique est appliqué à travers les première et seconde électrodes (132, 138 ou 232, 236) de sorte que les porteurs de charge électronique pénètrent la couche active (136, 234) et y sont retenus par des pièges. En effaçant le dispositif de mémoire (130, 230), un potentiel électrique est appliqué à travers les première et seconde électrodes (132, 138 ou 232, 236) de sorte que les porteurs de charge électronique sont éloignés de la couche active (136, 234).
PCT/US2006/016185 2005-05-11 2006-04-26 Dispositif de memoire resistive avec retention amelioree des donnees et consommation electrique reduite WO2006124235A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP06758720A EP1883930A1 (fr) 2005-05-11 2006-04-26 Dispositif de memoire resistive avec retention amelioree des donnees et consommation electrique reduite
JP2008511151A JP4731601B2 (ja) 2005-05-11 2006-04-26 データ保持および省電力が向上した抵抗メモリ装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/126,800 US20060256608A1 (en) 2005-05-11 2005-05-11 Resistive memory device with improved data retention and reduced power
US11/126,800 2005-05-11

Publications (1)

Publication Number Publication Date
WO2006124235A1 true WO2006124235A1 (fr) 2006-11-23

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Country Status (7)

Country Link
US (1) US20060256608A1 (fr)
EP (1) EP1883930A1 (fr)
JP (1) JP4731601B2 (fr)
KR (1) KR100925255B1 (fr)
CN (1) CN101171643A (fr)
TW (1) TW200703621A (fr)
WO (1) WO2006124235A1 (fr)

Cited By (2)

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WO2008054572A1 (fr) * 2006-10-31 2008-05-08 Spansion Llc Procédé de sélection des caractéristiques d'exploitation d'un dispositif de mémoire résistive
JP2008112945A (ja) * 2006-10-31 2008-05-15 Sony Corp 記憶装置

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US7830015B2 (en) * 2005-03-25 2010-11-09 Spansion Llc Memory device with improved data retention
US7286388B1 (en) * 2005-06-23 2007-10-23 Spansion Llc Resistive memory device with improved data retention
US8030637B2 (en) * 2006-08-25 2011-10-04 Qimonda Ag Memory element using reversible switching between SP2 and SP3 hybridized carbon
US7915603B2 (en) * 2006-10-27 2011-03-29 Qimonda Ag Modifiable gate stack memory element
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US8077495B2 (en) * 2006-12-05 2011-12-13 Spansion Llc Method of programming, erasing and repairing a memory device
US7599211B2 (en) * 2007-04-10 2009-10-06 Infineon Technologies Ag Integrated circuit, resistivity changing memory device, memory module and method of fabricating an integrated circuit
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US8995167B1 (en) * 2013-02-01 2015-03-31 Adesto Technologies Corporation Reverse program and erase cycling algorithms
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JP2008112945A (ja) * 2006-10-31 2008-05-15 Sony Corp 記憶装置
US7646624B2 (en) 2006-10-31 2010-01-12 Spansion Llc Method of selecting operating characteristics of a resistive memory device

Also Published As

Publication number Publication date
KR20080009302A (ko) 2008-01-28
CN101171643A (zh) 2008-04-30
JP4731601B2 (ja) 2011-07-27
KR100925255B1 (ko) 2009-11-05
EP1883930A1 (fr) 2008-02-06
TW200703621A (en) 2007-01-16
US20060256608A1 (en) 2006-11-16
JP2008541448A (ja) 2008-11-20

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