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WO2006115819A1 - Bus differentiel electronique utilisant un etat nul pour le transfert des donnees - Google Patents

Bus differentiel electronique utilisant un etat nul pour le transfert des donnees Download PDF

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Publication number
WO2006115819A1
WO2006115819A1 PCT/US2006/014017 US2006014017W WO2006115819A1 WO 2006115819 A1 WO2006115819 A1 WO 2006115819A1 US 2006014017 W US2006014017 W US 2006014017W WO 2006115819 A1 WO2006115819 A1 WO 2006115819A1
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WO
WIPO (PCT)
Prior art keywords
data
buses
data system
electronic
bus
Prior art date
Application number
PCT/US2006/014017
Other languages
English (en)
Inventor
Iu-Meng Tom Ho
Original Assignee
Iota Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Iota Technology, Inc. filed Critical Iota Technology, Inc.
Publication of WO2006115819A1 publication Critical patent/WO2006115819A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers

Definitions

  • the invention in general relates to electronic signal transfer which can be used for differential data bus transfer or differential control signal transfer, and in particular such signals are capable of transferring data in a plurality of binary states.
  • Electronic signal buses comprising pairs of differential signal wires are well known. Most or all of such differential wire pairs are capable of transferring a single bit of data in each transfer or symbol which is apparent from the transmission Eye- diagram of the respective system.
  • differential signal buses are used to transfer the true and complementary data at the same time, where normally just one of the single signal wire is enough to transfer the data for a single-ended wire at a lower performance requirement; e.g.
  • CML bus CML bus, XDR from Rambus, LVDS, BLVDS, M- LVDS, LVDM, SERDES, etc.
  • Each of these differential signals consists of two signal wires and they are all transmitting one bit of data per symbol or per transfer. It seems a little wasteful in a system with a lot of parallel communications between components and modules; e.g. Network switches, Multi-core CPUs, graphic processors etc. to use two signal wires to transfer 1-bit of data or V ⁇ bit of data per signal wire.
  • Vdiff the "01" (-Vdiff) and "10" (+Vdiff) states are used to represent a robust Logic-0, or a robust Logic-1.
  • the "00" and “11” states, which can be both represented by “Vdiff 0" are not being use to represent data. Herein, this state is called the NULL state.
  • the voltage level of Vdiff is determined by the bus system specification. It is normally set to the smallest possible for the target system and technology. It is a huge challenge to circuit designers to utilize fractions of Vdiff to transmit more data on the differential bus especially at high speed.
  • the invention provides a solution to the above problems by utilizing the NULL state of a differential signal bus to transmit more data on a differential bus pair.
  • All the Current Mode Logic CML buses, ECL buses, Low-Voltage- Differential-Signaling LVDS type buses, etc. can be easily converted to support the three states transmission.
  • These differential buses include; e.g. XDR from Rambus, BLVDS, M-LVDS, LVDM, SERDES, differential HSTL, differential SSTL, ECL, PECL, LVECL, etc.
  • the differential buses can be used to transmit data and control signals on chip or off chip. They can also be point-to-point, multi-drops or multi- points.
  • the differential buses can be of type fiber Optical, Capacitive Coupled, Inductive MC, Pulse Charged, Open-drain, Open-collector, Directly Driven, DC coupled, AC coupled etc.
  • SDR Single-Data-Rate
  • DDR Double- Data-Rate
  • QDR Quart-Data-Rate
  • ODR or XDR by Rambus etc.
  • NULL state of a differential bus to transmit data or control signals. All the differential buses described above can all take advantage of the NULL state. With e.g. +Vdiff "1 state” and -Vdiff "0 state”, and the NULL state, there are three states available for each differential bus transfer or symbol. Since data or control signal streams can be transmitted in serial or in parrallel, both can be used for three states data transfer.
  • each data transfer or symbol will have three states. Two related data symbols or data transfers, adjacent or not depending on the implementation architecture, can be combined together to produce nine states which would be enough to represent three bits of data with an extra state e.g. NULL-NULL left to be used for e.g. Un-driven, Violation, No-data etc.
  • serial transfer throughput can be improved by as much as 1.5x at the same power consumption or lower depending on the specific implementation.
  • the 8B/10B type encoding/decoding algorithms to avoid run length problem can be avoided which further improve the data transmission efficiency.
  • the three states differential bus could increase the data transfer rate by 1.667x for a byte oriented serial data stream.
  • two differential buses can be used to transmit three bits of data with an extra state e.g. NULL-NULL left to be used for e.g. Un-driven, Violation, No-data etc.
  • Up to one third of the physical bus wires can be saved, and at least one third to one half of the data transmission power consumption depending on how the NULL state is being generated can be saved.
  • a free parity is available when three pairs of three states differential buses are used or the extra bit can be used for the adjacent buses. Because of the additional NULL-NULL state available which normally can be used when the bus is not driven or no-data, the state of NOT(NULL-NULL) can always represent valid data or bus is driven.
  • the NULL state is the state when the drivers on the two ends of the transmitting antenna are not being driven to transmit a Logic 0 or 1 , i.e. a ⁇ Vdiff or -Vdiff at the receiving antenna and receiver circuit. They could be not driven or just slightly driven in a way to cancel out the neighboring inductive noise during the NULL state.
  • This same technique is also applicable to CML type bus, LVDS bus, ECL bus, Capacitive Pulsed Charged bus, etc.
  • the invention provides a solution to the above problems by utilizing the NULL state of a differential signal bus to transmit more data on a differential bus pair, while each bus wire can be transmitting 3 A bit of data rather than Y ⁇ bit of data.
  • FIG. 1 shows two data eye patterns of Return-to-NULL differential bus for regular two states data transfer and the new three states data transfer;
  • FIG. 2 is a block circuit diagram illustrating the architecture of a parallel
  • FIG. 3 shows two sets of data eye patterns for transferring three bits serial data stream using Non-Return-to-Zero and Return-to-NULL modes
  • FIG. 4 shows the waveforms of a Retum-to-NULL Three States Differential Bus Pair in all nine states
  • FIG. 5 shows the waveforms of a Return-to-NULL Three States Differential Bus transferring different eight bits data streams
  • FIG. 6 is a sample architecture of a Three States Differential Bus SerDes circuit for serial data transmitting and receiving
  • FIG. 7 is a sample architecture of a Three States Differential Bus Pair circuit for transmitting and receiving three bits width data stream;
  • FIG. 8 is a sample architecture of a Three States Differential Bus Pair circuit for receiving eight bits width data stream.
  • FIG. 9 is a sample architecture of a Three States Differential Bus Pair circuit for transmitting eight bits width data stream.
  • the invention relates to electronic differential buses. These differential buses can be used for both data and control signal transfer.
  • the signal streams can be serial or parallel.
  • These differential buses include differential True and Complement bus wires and components which can be direct drive, inductive coupled, AC coupled etc. These bus wires and components connect the corresponding drivers, receivers, and associated circuitries for transmitting and receiving data.
  • FIG. 1 shows two Retum-to-NULL (RN) data eye patterns (101 ) and (102).
  • the data eye pattern (101 ) is the existing RN differential bus eye pattern with two states.
  • the data eye pattern (102) shows how the NULL state (103) can be added onto the existing two states data eye pattern to become a three states data eye pattern.
  • the 8B/10B type encoding/decoding algorithms to avoid run length problem can be avoided which further improve the data transmission efficiency.
  • the three states differential bus could increase the data transfer rate by 1.667x for a byte oriented serial data stream.
  • For a parallel differential bus system upto one third of the physical bus wires can be saved, and at least one third to one half of the data transmission power consumption depending on how the NULL state is being generated can be saved.
  • On a 8 bit parallel differential bus system a free parity is available when three pairs of three states differential buses are used or the extra bit can be used for the adjacent buses. Because of the additional NULL-NULL state available which normally can be used when the bus is not driven or no-data, the state of NOT(NULL-NULL) can always represent valid data or bus is driven.
  • FIG. 2 is a differential bus system like the LVDS buses.
  • the NULL state for a differential bus can be slightly driven, "Undriven”, driven to a Vt er m voltage by the drivers or by the corresponding termination resistive network (203).
  • both True and Complement outputs can be driven to the same voltage with both of the output drivers being on at the same drawing the same amount of current.
  • the NULL state is the state when the drivers on the two ends of the transmitting antenna are not being driven to transmit a Logic 0 or 1 , i.e. a +Vdiff or -Vdiff at the receiving antenna and receiver circuit. They could be not driven or just slightly driven in a way to cancel out the neighboring inductive noise during the NULL state.
  • This same technique is also applicable to CML type bus, LVDS bus, ECL bus, Capacitive Pulsed Charged bus, etc. when the NULL state can be that the two different bus wires are in the same voltage or slightly different to cancel out neighboring and reflected noise. The idea is to achieve a close to zero Vdiff or VID at the input of the receiver circuit.
  • the bus driver (201) is open-drain or open-collector style, LogicO can be Open, Logid can be full strength Pulldown, and the NULL state can be both Open which is driven by the termination network or both Pulldown.
  • the bus pair (204) are being sampled by the TSBR "Three States Bus Receiver” (202) controlled by some enable signals "en” (211 ).
  • the "en” signals are synchronized with the "Send CNTL” (210) signals from the driving side through some internal circuits, e.g. CDR "Clock and Date Recovery", PLL “Phase Lock Loop” or DLL “Delay Lock Loop” circuits.
  • Each TSBR (202) would normally generate two output SO and S1 representing the states on the BUS1 or BUS2, which will in turn be optionally decoded by the Three State Differential Bus Pair TSDBP Decoder (205) to generate the corresponding three data bits Y ⁇ 0,1 ,2 ⁇ (207).
  • a parallel data bus with bit width e.g. 8 or 9
  • three pairs of TLBP circuits are needed.
  • the ninth bit can be used as parity bit or other applications depending on the implementation details. Since the bit width for a parallel bus system may not always be divisible by three, e.g. 8, 16, 32, 64, etc. it is always possible that a pair of TSDBP circuit is taking care of only two bits of data.
  • the Three States encoder and decoder circuitry can be simplified. For parallel bus system with bit width, e.g. 9, 18, 24, 36, 48, 54, 66, 72 etc., the TSDBP will provide the maximum savings of bus wire reduction.
  • the TSDBP can also be used to convert single-ended full swing signals to low swing high speed differential signals to improve speed and save power; e.g. three full swing signals with three individual signal wires can be converted to TSDBP three states differential bus pair with four signal wires. The cost is one wire out of every three signal. It would have taken six wires if the TSDBP is not used.
  • the Three States Bus Receiver TSBR (202) consists of differential sense amplifiers outputing two signals SO and S1. Two pairs of such signals S01 , S11 , S02, S12 (212) are driven onto the TSDSP Decoder (205). An example of how the two output signals SO and S1 mapped for the decoder is shown in Table 1 :
  • FIG. 3 shows two sets of data eye patterns for transferring three bits serial data stream.
  • the vertical lines (301 ) represent the clock ticks.
  • the Three States Differential Bus Data Pair TSDP versions on the right side are significantly different from the (Prior Art) binary versions on the left.
  • the TSDP needs two clock ticks to transfer three data bits while the regular differential bus would need all three clock ticks.
  • the NULL state is shown in the middle of VIH, and V
  • L representing Vdiff 0.
  • Vdiff 0.
  • Return-to-Null RN mode (304) and (305) at the bottom the differential buses are returned to NULL state after every transfer or clock tick.
  • FIG. 4 shows a parallel Three States Differential Bus Pair waveform with nine clock ticks.
  • the first clock tick (405) shows the NULL-NULL state which could represent No-data on the bus in this case.
  • Clock ticks 2 to 9 (403) represent the eight different states (404) of the three data bits represented in Table 3 above.
  • FIG. 5 shows how four different serial eight bit data streams can be transmitting using the Three States Differential Bus Data Pair in Retum-to-NULL mode.
  • the first two clock ticks transmit a NULL-NULL pair.
  • the third clock tick can be the start of data if NULL state is not used.
  • the beginning of data can be signaled by the logic state of NOT(NULL).
  • the first two data bits on clock ticks 3 and 4 are transmitted without the NULL state.
  • the rest of clock ticks would transmit with NULL states.
  • a NULL-NULL state is used and it also signals the END of the serial data transfer.
  • FIG. 6 shows a sample architecture of a Three States Differential Bus SerDes circuit for serial data transmitting and receiving.
  • the top row of circuits (916) are for transmitting and the bottom row of circuits (915) are for receiving.
  • Circuits (913)(911 ) is for receiving parallel data (DIN) to be sent out to the TSDB channel (901 ).
  • Circuit (909) is an alignment FIFO to prepare the parallel data (R) for the serializer register (920).
  • Circuit (907) is the TSDBP Encoder to generate two sets of SO and S1 from the data bits YO, Y1 , Y2 for the synchronization Flip-flops (905) to be driven out by the Three States Differential Bus Driver TSD (903).
  • circuits (902) (904) are the Clock and Data recovery circuit and differential sense amplifiers to amplify and receive the high speed data stream.
  • Circuit (906) decodes the SO, S1 signal pair to generate YO, Y1 , Y2 to the deserializer register (908).
  • Circuit (910) is an alignment FIFO for the (PO) data for parallel transfer through the Output Register (912) and Parallel data out drivers (914).
  • FIG. 7 shows a sample architecture of a Three States Differential Bus Pair for a three bit data width data stream.
  • the top row of circuits (1016) are for transmitting and the bottom row of circuits (1015) are for receiving.
  • Circuits (1013)(1011 ) is for receiving parallel data (DIN) to be sent out to the TSDB channel (1001 ).
  • Circuit (1009) is an alignment FIFO to prepare the parallel data (R) for the serializer register (1020).
  • Circuit (1007) is the TSDBP Encoder to generate two sets of SO and S1 from the data bits YO, Y1 , Y2 for the synchronization Flip-flops (1005) to be driven out by the Three States Differential Bus Driver TSD (1003).
  • circuits (1002) (1004) are the Clock and Data recovery circuit and differential sense amplifiers to amplify and receive the high speed data stream.
  • Circuit (1006) decodes the SO, S1 signal pair to generate YO, Y1 , Y2 to the deserializer register (1008).
  • Circuit (1010) is an alignment FIFO for the (PO) data for parallel transfer through the Output Register (1012) and Parallel data out drivers (1014).
  • FIG. 8 and 9 show a sample architecture of a Three States Differential Bus Pair system for transmitting and receiving eight bit parallel data stream.
  • Circuits on FIG. 9 (1216) are for transmitting and circuits on FIG. 8 (1115) are for receiving.
  • Circuits (1213)(1211 ) is for receiving parallel data (DIN) to be sent out to the TSDB channel (1201 ).
  • Circuit (1209) is an alignment FIFO to prepare the parallel data (R) for the serializer register (1220).
  • Circuit (1207) is the TSDBP Encoder to generate two sets of SO and S1 from the data bits YO, Y1 , Y2 for the synchronization Flip- flops (1205) to be driven out by the Three States Differential Bus Driver TSD (1203).
  • circuits (1102) (1104) are the Clock and Data recovery circuit and differential sense amplifiers to amplify and receive the high speed data stream.
  • Circuit (1106) decodes the SO, S1 signal pair to generate YO, Y1 , Y2 to the deserializer register (1108).
  • Circuit (1110) is an alignment FIFO for the (PO) data for parallel transfer through the Output Register (1112) and Parallel data out drivers (1114).

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Dc Digital Transmission (AREA)

Abstract

L'invention concerne un système de données électroniques comprenant: un bus système de données différentiels comprenant des fils de signaux vrais et de complément; un circuit d'écriture destiné à écrire une logique 0, une logique 1 et un état nul vers le bus système de données différentielles. Cet état nul consistant en un état dans lequel Vdiff = 0; et un circuit de lecture destiné à lire la logique 0, la logique 1 et l'état nul à partir du bus système de données différentielles. Dans l'un des modes de réalisation, il existe deux bus de données différentielles formant une paire de bus de données, et au moins un train de données est déterminé par un état électronique du premier bus et un état électronique du second bus. Dans ce mode de réalisation, le circuit d'écriture permet de placer chacune des première et seconde paires de bus de données en trois états électroniques pour un total de neuf combinaisons d'état électronique possibles.
PCT/US2006/014017 2005-04-21 2006-04-14 Bus differentiel electronique utilisant un etat nul pour le transfert des donnees WO2006115819A1 (fr)

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US67339905P 2005-04-21 2005-04-21
US60/673,399 2005-04-21

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0256935A2 (fr) * 1986-08-06 1988-02-24 Fujitsu Limited Mémoire morte comprenant des cellules de mémoire emmagasinant chacune un état parmi trois
WO2005088465A1 (fr) * 2004-03-03 2005-09-22 Koninklijke Philips Electronics N.V. Communication de donnees effectuee au moyen de codes de correction d'erreur insensibles aux defaillances et a rebondissement reduit sur la plaque de masse
WO2005088467A1 (fr) * 2004-03-03 2005-09-22 Koninklijke Philips Electronics N.V. Module de communication de données assurant la résistance aux pannes et une meilleure stabilité

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0256935A2 (fr) * 1986-08-06 1988-02-24 Fujitsu Limited Mémoire morte comprenant des cellules de mémoire emmagasinant chacune un état parmi trois
WO2005088465A1 (fr) * 2004-03-03 2005-09-22 Koninklijke Philips Electronics N.V. Communication de donnees effectuee au moyen de codes de correction d'erreur insensibles aux defaillances et a rebondissement reduit sur la plaque de masse
WO2005088467A1 (fr) * 2004-03-03 2005-09-22 Koninklijke Philips Electronics N.V. Module de communication de données assurant la résistance aux pannes et une meilleure stabilité

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
CHRISTER SVENSSON AND JIREN YUAN: "A 3-Level Asynchronous Protocol for a Differential Two- Wire Communication Link", IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 29, 29 September 1994 (1994-09-29), pages 1129 - 1132, XP002394768 *
PEDRO A. MOLINA P. Y. K. CHEUNG DAVID S. BORMANN: "QUASI DELAY-INSENSITIVE BUS FOR FULLY ASYNCHRONOUS SYSTEMS", CIRCUITS AND SYSTEMS, 1996. ISCAS '96., 'CONNECTING THE WORLD'., 1996 IEEE INTERNATIONAL SYMPOSIUM ON, vol. 4, 15 May 1996 (1996-05-15), pages 189 - 192, XP002394767 *
TAKAHIRO HANYU, TOMOHIRO TAKAHASHI, MICHITAKA KAMEYAMA: "Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current Mode Logic", PROCEEDINGS OF THE 33RD INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, no. 33, 2003, XP002394766 *

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