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WO2006106564A1 - Dispositif a semi-conducteurs et son procede de montage - Google Patents

Dispositif a semi-conducteurs et son procede de montage Download PDF

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Publication number
WO2006106564A1
WO2006106564A1 PCT/JP2005/005876 JP2005005876W WO2006106564A1 WO 2006106564 A1 WO2006106564 A1 WO 2006106564A1 JP 2005005876 W JP2005005876 W JP 2005005876W WO 2006106564 A1 WO2006106564 A1 WO 2006106564A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor device
wiring board
solder
terminals
corners
Prior art date
Application number
PCT/JP2005/005876
Other languages
English (en)
Japanese (ja)
Inventor
Takashi Emata
Toshihiro Tsuboi
Original Assignee
Hitachi Ulsi Systems Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ulsi Systems Co., Ltd. filed Critical Hitachi Ulsi Systems Co., Ltd.
Priority to PCT/JP2005/005876 priority Critical patent/WO2006106564A1/fr
Publication of WO2006106564A1 publication Critical patent/WO2006106564A1/fr

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
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    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H05K3/3457—Solder materials or compositions; Methods of application thereof
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
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Definitions

  • the present invention relates to a semiconductor device mounting method and a semiconductor device, and more particularly, to a technique for mounting a semiconductor device in the form of a semiconductor package on a wiring board via solder, and to a solder-mounted semiconductor device. It relates to effective technology.
  • a semiconductor chip is mounted on a wiring board, the electrodes of the semiconductor chip and the connection terminals of the wiring board are electrically connected by bonding wires, the semiconductor chip and the bonding wires are sealed with resin, and the back surface of the wiring board is sealed.
  • a semiconductor device in the form of a semiconductor package is manufactured.
  • semiconductor devices include, for example, a chip size called a CSP (Chip Size Package) or a small semiconductor package slightly larger than a semiconductor chip.
  • the semiconductor device can be mounted on the substrate by supplying solder onto the terminals of the substrate and mounting the semiconductor device with force, and performing solder reflow.
  • Patent Document 1 discloses that each end portion in the longitudinal direction of the opening of the metal mask is formed wider than the center portion of the opening, thereby providing cream solder at both ends. The technology that can suppress the residual of the resin and obtain a stable printability is described.
  • Patent Document 2 describes a technique for partially adjusting the amount of cream solder supplied on a substrate pattern by partially changing the thickness (wall thickness) of a metal mask. It has been.
  • JP-A-8-97545 (Patent Document 3) describes the inner diameter of a hole for solder printing provided in a metal mask used for solder printing on a land on a printed circuit board as the outer diameter of the land. It describes a technology that suppresses the generation of solder balls when mounting a surface-mounted highly integrated multi-terminal LSI package.
  • Patent Document 4 discloses a printed wiring mounted with a semiconductor chip.
  • a substrate is prepared, and a mask is prepared by attaching an opening and a stretchable film that closes the opening to the semiconductor chip portion.
  • the mask is brought into close contact with the substrate, and the semiconductor chip portion is stretched by stretching the film.
  • a technique is described in which a solder cream is applied to the soldered portion of the substrate through the opening of the mask using a squeegee having a large number of slits.
  • Patent Document 5 a fine pitch is obtained by changing the amount of solder to be printed on a printed wiring board by providing a recess on the side of the metal mask that does not contact the printed wiring board.
  • the technology to prevent loose soldering on a surface-mounted substrate that contains a large number of ICs and large components is described.
  • Patent Document 6 uses two metal masks with different thicknesses to divide the supply of cream solder into two steps, and allows an arbitrary amount per unit area. It describes a technology related to a cream solder supply method that can supply tarim solder.
  • Japanese Patent Laid-Open No. 5-318696 discloses a thick metal mask in which contact with cream solder formed with the thin metal mask is avoided by a no fetching portion in the process after cream solder printing with a thin metal mask.
  • cream solder fine parts with small terminal spacing were soldered with thin cream solder printed with a thin metal mask, and large parts with large terminal float were printed with a thick metal mask. Describes the technology of soldering with thick Tarim solder.
  • Patent Document 1 Japanese Patent Laid-Open No. 2001-212928
  • Patent Document 2 JP-A-11-74638
  • Patent Document 3 JP-A-8-97545
  • Patent Document 4 JP-A-10-24552
  • Patent Document 5 Japanese Patent Laid-Open No. 5-112083
  • Patent Document 6 JP-A-5-212852
  • Patent Document 7 JP-A-5-318696
  • Warping of the semiconductor device occurs before and after the semiconductor device is mounted on the wiring board. This warpage of the semiconductor device is mainly caused by a difference in thermal expansion coefficient between the wiring board constituting the semiconductor device and the sealing resin. When a semiconductor device warps, the semiconductor device tends to warp along a diagonal direction. For this reason, the amount of warpage of the semiconductor device is greatest near the four corners (corners). Under a high temperature environment such as during solder reflow, the semiconductor device tends to warp in an upwardly convex state (that is, a state where the four corners of the lower surface of the semiconductor device are below the center side).
  • the molten solder ball is present in the vicinity of the four corners where the warpage is the largest. Will be crushed by the warped semiconductor device.
  • the crushed solder flows out and reaches the adjacent solder ball, solidifies after solder reflow, and the adjacent solder balls may come into contact with each other to cause a short circuit. There is sex. If a short circuit occurs between the solder balls, the wiring board on which the semiconductor device is mounted must be selected and removed as defective. Therefore, such a poor solder flow or short circuit failure reduces the mounting yield of the semiconductor device. As a result, the cost of the electronic device manufactured by mounting the semiconductor device on the mounting substrate is increased.
  • An object of the present invention is to provide a technique capable of improving the mounting yield of a semiconductor device.
  • a semiconductor device having external terminals arranged on the lower surface is mounted on the wiring board, and solder reflow processing is performed to externally attach the semiconductor device.
  • solder reflow processing is performed to externally attach the semiconductor device.
  • the present invention is a semiconductor device having a plurality of bump electrodes with soldering power arranged on the main surface, and among the plurality of bump electrodes, bump electrodes at four corners or bump electrodes at and around the four corners are provided. It is smaller than the other bump electrodes.
  • a semiconductor device having a plurality of bump electrodes with solder force arranged on the lower surface is mounted on a wiring board, and a solder reflow process is performed to electrically connect the bump electrodes of the semiconductor device to terminals of the wiring board.
  • the bump electrodes at the four corners or the bump electrodes at the four corners and the vicinity of the bump electrodes among the plurality of bump electrodes of the semiconductor device are / J more than the other bump electrodes.
  • the present invention is a semiconductor device having a plurality of bump electrodes with soldering power arranged in an array on the main surface, wherein the bump electrodes are not provided at the four corners of the array. .
  • a semiconductor device having a plurality of bump electrodes with solder force arranged in an array on the lower surface is mounted on a wiring board, and a solder reflow process is performed to form bump electrodes of the semiconductor device.
  • the bump electrodes are not provided at the four corners of the array arrangement when electrically connected to the terminals of the wiring board.
  • the mounting yield of the semiconductor device can be improved.
  • FIG. 1 is a top view of a semiconductor device according to an embodiment of the present invention.
  • FIG. 2 is a bottom view of the semiconductor device of FIG.
  • FIG. 3 is a side view of the semiconductor device of FIG. 1.
  • FIG. 4 is a cross-sectional view of the semiconductor device of FIG.
  • FIG. 5 is a cross-sectional view of the semiconductor device of FIG.
  • FIG. 6 is a cross-sectional view of the semiconductor device as an embodiment of the present invention during the manufacturing process thereof.
  • FIG. 7 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 6.
  • FIG. 8 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.
  • FIG. 9 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.
  • FIG. 10 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 9;
  • FIG. 11 is a process flow diagram showing a mounting process of a semiconductor device according to an embodiment of the present invention.
  • FIG. 13 is a plan view of the same semiconductor device as in FIG. 12 during the mounting process.
  • FIG. 13 is a sectional view of the semiconductor device during the mounting process following FIG.
  • FIG. 16 is a cross-sectional view of the semiconductor device during the mounting process following that of FIG. 15;
  • FIG. 17 is a cross-sectional view of the semiconductor device during the mounting process following that of FIG. 16;
  • FIG. 18 is a cross-sectional view of the semiconductor device during the mounting process following that of FIG. 17;
  • FIG. 19 is a cross-sectional view of the semiconductor device during a mounting step following that of FIG. 18;
  • FIG. 20 is a cross-sectional view showing a mounting process of a semiconductor device of a comparative example.
  • FIG. 21 is a cross-sectional view of the semiconductor device of the comparative example subsequent to FIG. 20 during the mounting process.
  • FIG. 22 is a cross-sectional view of the semiconductor device of the comparative example subsequent to FIG. 21 during the mounting process.
  • FIG. 23 is a cross-sectional view of the semiconductor device of the comparative example subsequent to FIG. 22 during the mounting process.
  • FIG. 25 is a cross-sectional view showing a state in which solder paste is supplied onto the terminals of the wiring board using the mask of FIG.
  • FIG. 26 is a plan view of a mask used in a mounting process of a semiconductor device according to another embodiment of the present invention.
  • FIG. 27 is a cross-sectional view showing a state in which solder paste is supplied onto the terminals of the wiring board using the mask of FIG.
  • FIG. 28 is a bottom view of a semiconductor device according to another embodiment of the present invention.
  • FIG. 29 is a cross-sectional view of the semiconductor device of FIG. 28.
  • 30 is a cross-sectional view of the semiconductor device of FIG. 28.
  • FIG. 31 A sectional view of the semiconductor device in another embodiment of the present invention during the manufacturing process.
  • FIG. 32] is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 31;
  • FIG. 33 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 31;
  • FIG. 32 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.
  • FIG. 35 is a bottom view of a semiconductor device in another embodiment of the present invention.
  • FIG. 36 is a top view of a wiring board for mounting the semiconductor device of FIG.
  • FIG. 37 is a plan view of a solder printing mask used in the process of mounting the semiconductor device on the wiring board of FIG. 36.
  • FIG. 38 is a cross-sectional view showing a state in which solder paste is supplied onto the terminals of the wiring board using the mask of FIG.
  • FIG. 39 A plan view of a solder printing mask used in the mounting process of the semiconductor device according to another embodiment of the present invention.
  • FIG. 40 A sectional view of the semiconductor device in another embodiment of the present invention during the mounting process. 41] FIG. 41 is a cross-sectional view of the semiconductor device during a mounting step following that of FIG. 40.
  • FIG. 42 is a cross-sectional view of the semiconductor device during a mounting step following that of FIG. 41;
  • FIG. 43 A bottom view of a semiconductor device in another embodiment of the present invention.
  • FIG. 44 is a cross-sectional view of the semiconductor device of FIG. 43.
  • FIG. 44 is a cross-sectional view of the semiconductor device of FIG. 43.
  • FIG. 45 is a cross-sectional view of the semiconductor device of FIG. 43 during the process of mounting it on the wiring board.
  • FIG. 45 is a cross-sectional view of the semiconductor device during the mounting process following FIG. 44;
  • FIG. 47 A bottom view of a semiconductor device in another embodiment of the present invention.
  • FIG. 48 is a cross-sectional view of the semiconductor device of FIG. 47 during the mounting process on the wiring board.
  • FIG. 49 is a cross-sectional view of the semiconductor device during a mounting step following that of FIG. 48;
  • FIG. 50 is a process flow diagram showing a mounting process of a semiconductor device in another embodiment of the invention.
  • hatching may be omitted even in a cross-sectional view in order to make the drawings easy to see. Even a plan view may be hatched to make the drawing easier to see.
  • FIG. 1 is a top view (plan view) of a semiconductor device 1 according to an embodiment of the present invention
  • FIG. 2 is a bottom view (bottom view, back view, plan view)
  • FIG. A side view, FIG. 4 and FIG. 5 are sectional views (side sectional views).
  • the cross section taken along line A—A in FIGS. 1 and 2 substantially corresponds to FIG. 4, and the cross section taken along line B—B in FIGS. 1 and 2 substantially corresponds to FIG.
  • a semiconductor device 1 includes a semiconductor chip 2, a wiring board 3 that supports or mounts the semiconductor chip 2, and a plurality of electrodes (bonding) on the surface of the semiconductor chip 2.
  • a sealing resin (sealing resin part, sealing part, sealing body) 5 covering the upper surface (surface, main surface) 3a of the wiring board 3 including the semiconductor chip 2 and the bonding wire 4 and the wiring board 3 has a plurality of solder balls (solder bumps, bump electrodes, protruding electrodes) 6 provided in an area array arrangement as external terminals on the lower surface (back surface, main surface opposite to the upper surface 3a) 3b.
  • the semiconductor chip 2 is formed by forming various semiconductor elements or semiconductor integrated circuits on the main surface of a semiconductor substrate (semiconductor wafer) such as single crystal silicon, and then grinding the back surface of the semiconductor substrate as necessary. Then, the semiconductor substrate is separated into each semiconductor chip 2 by dicing or the like.
  • the semiconductor chip 2 has a front surface (main surface on the semiconductor element formation side) and a back surface (main surface opposite to the main surface on the semiconductor element formation side) facing each other, and wiring is performed so that the surface faces upward.
  • an adhesive 8 ing Placed on the upper surface (chip support surface) 3a of the substrate 3 and the back surface of the semiconductor chip 2 is bonded and fixed to the upper surface 3a of the wiring substrate 3 via an adhesive (die bond material, bonding material, adhesive) 8 ing.
  • the adhesive 8 for example, an insulating or conductive paste material can be used.
  • a plurality of electrodes 2a are formed on the surface of the semiconductor chip 2, and the electrodes 2a are electrically connected to a semiconductor element or a semiconductor integrated circuit formed in the semiconductor chip 2 or on the surface layer portion.
  • the wiring substrate 3 includes an insulating base layer (insulating substrate, core material) 11, and conductor layers (conductor pattern, conductor film pattern, wiring layer) formed on the top and bottom surfaces of the base layer 11.
  • the wiring board 3 may be a board in which a conductor layer is formed on the upper and lower surfaces of one insulating layer (base material layer 11), or a plurality of insulating layers (base material layers) and a plurality of conductor layers (wiring layers). ) Can be used as well.
  • the conductor layers on the upper surface and the lower surface of the base material layer 11 are patterned, and can be formed of, for example, a conductive material such as a copper thin film formed by a plating method.
  • a plurality of connection terminals (electrodes, bonding pads, node electrodes) 14 for connecting the bonding wires 4 and wirings 15 connected thereto are formed on the upper surface 3 a of the wiring board 3.
  • a plurality of conductive lands (electrodes, pads, terminals) 16 for connecting the solder balls 6 are formed on the lower surface 3 b of the wiring board 3 by the conductor layer on the lower surface of the base material layer 11.
  • a solder resist layer (not shown) can be formed on the upper surface 3a and the lower surface 3b of the wiring board 3. In this case, the connection terminals 14 and lands 16 are formed from the solder resist layer. Exposed.
  • the wiring 15 on the upper surface 3a of the wiring board 3 and the land 16 on the lower surface 3b are not shown in the drawing formed on the wiring board 3 (base material layer 11), through holes (conductors in the through holes), etc. It is electrically connected via. Therefore, the plurality of electrodes 2a of the semiconductor chip 2 are electrically connected to the plurality of connection terminals 14 of the wiring board 3 through the plurality of bonding wires 4, and further the wiring 15 and through holes (not shown) of the wiring board 3. ) It is electrically connected to multiple lands 16 on the wiring board 3 through conductors inside.
  • the bonding wire 4 has a fine metal wire force such as a gold wire.
  • the plurality of lands 16 are arranged in an array on the lower surface 3 b of the wiring board 3, and solder balls (bump electrodes, solder bumps) 6 are connected to the lands 16. Therefore, a plurality of solder balls 6 are arranged in an array on the lower surface 3b of the wiring board 3, that is, the lower surface (main surface) 12 of the semiconductor device 1.
  • the lower surface 12 of the semiconductor device 1 on which the solder balls 6 are arranged serves as a mounting surface of the semiconductor device 1 (the main surface on the side mounted on the mounting substrate). Therefore, the semiconductor device 1 of the present embodiment is a semiconductor device of BGA (Ball Grid Array package) type.
  • the solder ball 6 serves as a solder material force and functions as a bump electrode (projection electrode) 1 of the semiconductor device and can function as an external terminal of the semiconductor device 1.
  • the plurality of electrodes 2a of the semiconductor chip 2 are electrically connected to the plurality of connection terminals 14 of the wiring board 3 through the plurality of bonding wires 4, and further inside the wiring 15 and through holes (not shown) of the wiring board 3.
  • the plurality of lands 16 of the wiring board 3 and the plurality of solder balls 6 connected to the plurality of lands 16 are electrically connected to each other via the conductors of the wiring board 3. Further, the solder ball 6 that is electrically connected to the electrode 2a of the semiconductor chip 2 and is V can also be used for heat dissipation.
  • solder balls 6 are arranged in an array on the lower surface 3b of the wiring board 3, V, in this case, a plurality of solders are used as in Embodiment 3 (FIG. 35) described later.
  • the balls 6 (land 16) are arranged in a matrix over almost the entire lower surface 3b of the wiring board 3, as well as the central portion of the lower surface 3b of the wiring board 3 as in the present embodiment (FIG. 2). This includes the case where the solder balls 6 (land 16) are not arranged in the (center portion of the matrix arrangement) but are arranged in an array on the outer peripheral portion of the lower surface 3b of the wiring board 3.
  • a plurality of lands 16 and a plurality of solder balls 6 connected thereto Force arranged in the form of an array on the outer periphery of the lower surface 3b of the 1S wiring board 3
  • the number of solder balls 6 in the semiconductor device 1 and the number of rows of the solder balls 6 can be variously changed as necessary.
  • the force in which the solder balls 6 are arranged in two rows on the lower surface 12 of the semiconductor device 1 (the lower surface 3b of the wiring board 3), and the solder balls 6 are semi-conductive in an arrangement of one row or more.
  • the lower surface 12 of the body device 1 (the lower surface 3b of the wiring board 3) can also be arranged.
  • the sealing resin 5 is made of a resin material such as a thermosetting resin material, and may contain a filler.
  • the sealing resin 5 can be formed using an epoxy resin containing a filler.
  • the sealing resin 5 is formed on the upper surface 3a of the wiring board 3 so as to cover the semiconductor chip 2 and the bonding wire 4, and the semiconductor chip 2 and the bonding wire 4 are sealed by the sealing resin 5. And protected.
  • the semiconductor chip 2 is mounted on the wiring board 3, and the solder balls 6 are joined to the wiring board 3 as external terminals.
  • the semiconductor device is a semiconductor device (semiconductor package).
  • the semiconductor device i is, for example, a semiconductor device in the form of a CSP (Chip Size Package), which is a small semiconductor package having a chip size or slightly larger than the semiconductor chip 2.
  • the planar shape of the semiconductor device 1 (wiring board 3) can be, for example, a square shape with a side of about 5 mm.
  • the semiconductor device 1 has solder balls 6 arranged in an array, and can function as a semiconductor device in the form of a BGA package.
  • FIG. 6 to 10 are cross-sectional views in the manufacturing process of the semiconductor device 1 of the present embodiment.
  • wiring board base 21 formed by connecting a plurality of wiring boards 3 in an array is used to manufacture individual semiconductor devices 1. The case will be described.
  • a wiring board 21 is prepared.
  • the wiring board 21 is a base body of the wiring board 3, and the wiring board 21 is cut in a cutting process described later and separated into each semiconductor device region (substrate region, unit substrate region) 22.
  • a wiring board of 3 mm is supported.
  • the wiring board 21 has a configuration in which a plurality of semiconductor device regions 22 from which one semiconductor device 1 is formed are arranged in a matrix. Therefore, the wiring board
  • the connection terminals 14 and wirings 15 are formed in each semiconductor device region 22 on the upper surface 21a of the 21, and the lands 16 are formed in each semiconductor device region 22 on the lower surface 21b of the wiring substrate 21.
  • the semiconductor chip 2 is bonded (die bonding, chip mounting) to each semiconductor device region 22 on the upper surface 21a of the wiring substrate 21 via an adhesive material 8.
  • an adhesive material 8 for example, a conductive adhesive such as force silver paste which is an insulating adhesive can be used.
  • the adhesive 8 is applied to substantially the center of each semiconductor device region 22 on the upper surface 21a of the wiring board 21 to form an adhesive layer for fixing the chip, and the semiconductor chip 2 is placed on the adhesive 8 And power!
  • the top surface 21a of the wiring board 21 and the back surface 2c of the semiconductor chip 2 can be bonded via the adhesive 8 by heating or the like.
  • a wire bonding step is performed to connect each electrode 2a of the semiconductor chip 2 and the corresponding connection terminal 14 formed on the wiring board 21 to the bonding wire 4 Electrical connection through That is, a plurality of connection terminals 14 on each semiconductor device region 22 on the upper surface 21a of the wiring board 21 and a plurality of electrodes 2a of the semiconductor chip 2 bonded on the semiconductor device region 22 are connected via a plurality of bonding wires 4. Connect them electrically.
  • resin sealing is performed by a molding process (for example, transfer molding process) to form a sealing resin 5a (sealing portion), and a semiconductor chip 2 and the bonding wire 4 are sealed with a sealing resin 5a.
  • a molding process for example, transfer molding process
  • collective sealing is performed in which a plurality of semiconductor device regions 22 on the upper surface 21a of the wiring substrate 21 are collectively sealed with a sealing resin 5a. That is, the sealing resin 5 a is formed on the plurality of semiconductor device regions 22 on the upper surface 21 a of the wiring substrate 21 so as to cover the semiconductor chip 2 and the bonding wires 4.
  • the sealing resin 5a is formed so as to cover the plurality of semiconductor device regions 22 on the upper surface 21a of the wiring board 21.
  • the sealing resin 5a also has a power such as a resin material such as a thermosetting resin material, and can include a filler.
  • the sealing resin 5a can be formed using an epoxy resin containing a filler.
  • the sealing resin 5a can be formed by injecting a sealing resin material into the mold cavity disposed on the wiring substrate 21 and curing the sealing resin material by heating. Next, as shown in FIG. 10, solder balls 6 are connected (bonded) to the lands 16 on the lower surface 21b of the wiring board 21.
  • solder balls 6 are disposed on a plurality of lands 16 on the lower surface 21b of the wiring board 21 with the lower surface 21b of the wiring board 21 facing upward, and temporarily fixed with flux or the like, and solder reflow processing (reflow processing,
  • the solder balls 6 and the lands 16 on the lower surface 21b of the wiring board 21 can be joined and electrically connected by melting the solder by heat treatment. Thereafter, if necessary, a cleaning process can be performed to remove the flux attached to the surface of the solder ball 6. In this way, the solder balls 6 as the external terminals of the semiconductor device 1 are joined.
  • the force described in the case where the solder ball 6 is bonded to the land 16 as an external terminal of the semiconductor device 1 is not limited to this.
  • a bump electrode (solder bump) as an external terminal of the semiconductor device 1 can be formed on the land 16 by supplying solder onto the land 16.
  • the material of the external terminal of the semiconductor device 1 in this case, the solder ball 6) may be a lead-free solder or lead-free solder that does not contain lead, but it does not contain lead-free solder. Is more preferable.
  • the wiring substrate 21 and the sealing resin 5a formed thereon are cut (diced) into the semiconductor device regions 22 and separated (divided).
  • the semiconductor device 1 as shown in FIGS. 1 to 5 can be manufactured by cutting and dividing into pieces.
  • the wiring substrate 21 cut and separated (divided) into each semiconductor device region 22 corresponds to the wiring substrate 3, and the sealing resin 5a cut and separated (separated) into each semiconductor device region 22 is the sealing resin. Corresponds to 5.
  • FIG. 11 is a process flowchart showing the mounting process of the semiconductor device 1.
  • FIG. 13, and FIGS. 15 to 19 are cross-sectional views (main part cross-sectional views) or plan views (main part plan views) of the semiconductor device according to the present embodiment during the mounting process.
  • FIG. 14 is a plan view (main part plan view) of a mask 42 for solder printing used in the mounting process of the semiconductor device of the present embodiment.
  • 12 and 15 to 19 are sectional views
  • FIGS. 13 and 14 are plan views.
  • step S1 the semiconductor device 1 is prepared as described above (step S1), and the wiring board 31 that is a mounting board for mounting the semiconductor device 1 is prepared (step S2).
  • Preparation (manufacturing) of wiring board 31 in step S2 is performed before preparation (manufacturing) of semiconductor device 1 in step S1. It can be done at a later time or at the same time.
  • the wiring board 31 has a plurality of solder balls 6 of the semiconductor device 1 on the upper surface (surface, main surface) 31a that is a mounting surface on which the semiconductor device 1 is mounted.
  • a plurality of terminals (electrodes, pad electrodes, conductive lands) 32 for connection are provided.
  • FIG. 13 shows a plan view of a region in which the semiconductor device 1 is to be mounted on the wiring board 31, and a cross section taken along the line CC in FIG. 13 corresponds to FIG.
  • the wiring board 31 includes an insulating base material layer (insulating layer, resin material portion) 33 made of, for example, a resin material, and a plurality of terminals 32 are provided on the main surface of the base material layer 33. Is formed.
  • the terminal 32 is a terminal for connecting a solder ball 6 (bump electrode) which is an external terminal of the semiconductor device 1.
  • the solder ball 6 The terminal 32 is arranged at a position facing (overlap in plan).
  • a plurality of terminals 32 are formed in a region in which the semiconductor device 1 is to be mounted on the upper surface 31a of the wiring board 31, and the arrangement of the plurality of terminals 32 corresponds to the arrangement of the solder balls 6 on the lower surface 12 of the semiconductor device 1. . That is, the plurality of terminals 32 of the wiring board 31 have an arrangement corresponding to the arrangement of the solder balls 6 (bump electrodes) that are the external terminals of the semiconductor device 1, and the semiconductor device 1 mounted on the upper surface 31a of the wiring board 31 is provided. Multiple terminals 32 are arranged in an array in the planned area.
  • terminals other than the terminal 32 can be formed in an area other than the area where the semiconductor device 1 is planned to be mounted on the upper surface 31a of the wiring board 31, and an electronic component other than the semiconductor device 1 can be formed there. It can also be installed.
  • the terminals 32 on the upper surface 31a of the wiring board 31 and other terminals (not shown) are formed by a patterned conductor layer formed on the base material layer 33.
  • a solder resist layer (not shown) can be formed on the base material layer 33 so as to expose each terminal 32 and cover other regions.
  • wiring that connects between the terminals 32 and between the terminals 32 and the other terminals of the wiring board 31 is formed on the upper surface 31a, rear surface, or inside of the wiring board 31 as necessary.
  • the wiring board 31 a multilayer wiring board in which a plurality of insulating layers and a plurality of wiring layers are laminated can be used.
  • solder paste 41 is supplied (printed, applied, applied, and arranged) onto the plurality of terminals 32 of the wiring board 31 (step S3).
  • a plurality of terminals 32 of the wiring board 31 are printed by a printing method using a solder printing mask (metal mask, solder printing mask) 42.
  • Solder paste 41 can be supplied on top.
  • FIG. 14 is a plan view of a principal part of the mask 42
  • FIG. 15 is a cross-sectional view showing a state in which the mask 42 is disposed on the upper surface 3la of the wiring board 31, and a cross section in the same region as FIG. It is shown.
  • the cross section of the mask 42 in FIG. 15 corresponds to the cross section along the line DD in FIG. 16 to 19 also show cross sections in the same region as in FIGS.
  • a mask 42 is placed (covered) on the upper surface 3la of the wiring board 31.
  • the mask 42 is a powerful metal mask such as a metal plate, and has a plurality of openings 43 for exposing the terminals 32 of the wiring board 31 and supplying the solder paste 41 onto the terminals 32.
  • the arrangement of the openings 43 in the mask 42 corresponds to the arrangement of the terminals 32 in the wiring board 31. That is, the arrangement of the openings 43 in the mask 42 also corresponds to the arrangement of the solder balls 6 in the semiconductor device 1. Therefore, in the mask 42, a plurality of openings 43 are arranged in an array.
  • the mask 42 has a substantially uniform thickness, and can be, for example, about 0.1 mm thick.
  • the shape of the opening 43 of the mask 42 can be, for example, substantially the same as the shape of the terminal 32 in the wiring board 31 (for example, circular), and the dimension of the opening 43 of the mask 42 is It can be made to be the same as or smaller than the dimension of the terminal 32 on the wiring board 31. As a result, it is possible to prevent the solder paste 41 from being printed in a region other than the terminals of the wiring board 31.
  • the mask 42 includes the openings 43a arranged at the four corners (corners) and the openings in the vicinity thereof (near the openings 43a) among the plurality of openings 43 arranged in an array.
  • the portion 43b is smaller than the other opening 43c (that is, the opening 43c other than the openings 43a and 43b in the opening 43).
  • the opening 43b whose size (area) is reduced together with the opening 43a at the four corners is the opening 43 located in the vicinity of the opening 43a, for example, the opening 43b adjacent to the opening 43a. Therefore, in FIG. 14, among the opening 43, the four openings 43a at the four corners and the 12 openings 43b adjacent to the opening 43a have a total of 16 openings 43a and 43b. (Area) can be made smaller than other openings 43c.
  • the opening 43 of the mask 42 may have a circular shape or the like.
  • the diameter R of the opening 43a and the diameter R of the opening 43b adjacent to the opening 43a are set to the diameter R of the opening 43c.
  • the diameter R of the opening 43a is about 0.18 mm
  • the diameter R of the opening 43b is about 0.24 mm.
  • the arrangement of the openings 43 in the mask 42 corresponds to the arrangement of the terminals 32 on the wiring board 31, and the arrangement of the terminals 32 on the wiring board 31 corresponds to the arrangement of the solder balls 6 in the semiconductor device 1. It corresponds. Therefore, the openings 43a of the mask 42 are the terminals 32a arranged at the four corners (corner portions) of the plurality of terminals 32 arranged in an array in the semiconductor device 1 mounting region on the upper surface 31a of the wiring board 31. This is an opening for supplying the solder paste 41 on the top.
  • the terminals 32a of the wiring board 31 are terminals to which the solder balls 6a arranged at the four corners (corner portions) of the plurality of solder balls 6 arranged in an array on the lower surface 12 of the semiconductor device 1 are to be connected. . Further, the solder balls 6a are joined to lands 16a arranged at four corners (corner portions) of the plurality of lands 16 arranged in an array on the lower surface 3b of the wiring board 3 of the semiconductor device 1. Similarly, the opening 43b of the mask 42 is an opening for supplying the solder paste 41 onto the terminal 32b in the vicinity of the terminal 32a among the plurality of terminals 32.
  • the terminal 32b of the wiring board 31 is a terminal to which the solder ball 6b in the vicinity of the solder ball 6a among the plurality of solder balls 6 of the semiconductor device 1 is to be connected.
  • the solder ball 6b is joined to a land 16b in the vicinity of the land 16a among the plurality of lands 16 on the lower surface 3b of the wiring board 3 of the semiconductor device 1.
  • the opening 43c of the mask 42 is an opening for supplying the solder paste 41 on the terminals 32c other than the terminals 32a and 32b of the plurality of terminals 32. .
  • the terminal 32c of the wiring board 31 is a terminal to which a solder ball 6c other than the solder balls 6a and 6b among the plurality of solder balls 6 of the semiconductor device 1 is to be connected. Further, the solder ball 6 c is bonded to the lands 16 c other than the lands 16 a and 16 b among the plurality of lands 16 on the lower surface 3 b of the wiring substrate 3 of the semiconductor device 1.
  • the terminals 32 of the wiring board 31 are positioned below the openings 43 as shown in FIG.
  • the opening 43 force also exposes terminal 32.
  • solder paste 41 is supplied (applied or printed) selectively onto the main surface of the wiring board 31 and selectively onto the terminals 32 through the openings 43 of the mask 42.
  • the upper surface of the wiring board 31 also removes the mask 42.
  • solder paste 41 is supplied onto the plurality of terminals 32 of the wiring board 31 using a printing method.
  • the solder paste 41 may contain flux or the like.
  • the amount of the solder paste 41 supplied onto each terminal 32 is approximately equal to the area of each opening 43 of the mask 42. It is proportional and is also approximately proportional to the thickness of the mask 42. That is, the planar shape of the solder paste 41 supplied onto each terminal 32 of the wiring board 31 substantially corresponds to the planar shape of the opening 43 of the mask 42, and the solder paste supplied onto each terminal 32 of the wiring board 31.
  • the thickness of 41 roughly corresponds to the thickness of mask 42. For example, when each opening 43 of the mask 42 is circular, the planar shape of the solder paste 41 supplied onto each terminal 32 is almost circular, and the circular solder paste 41 supplied onto the terminal 32a The diameter R of the opening 43a of the mask 42
  • the diameter R of 1 is about the same as the diameter R of the opening 43b of the mask 42 (R R), and the terminal 32c
  • the diameter R of the circular solder paste 41 supplied on the top is the diameter of the opening 43c of the mask 42.
  • the mask 42 has a substantially uniform thickness, and the openings 43a and 43b of the openings 43 are smaller than the other openings 43c (R 1, R 2 ⁇ R). . Therefore, on each terminal 32 The thickness of the solder paste 41 supplied to each terminal 32 is almost the same thickness. The area of the solder paste 41 supplied on each terminal 32 is smaller than the other terminals 32c of the terminals 32a and 32b. (Ie R, R ⁇ R). Therefore, as shown in Figure 17, the wiring
  • the terminal 32a arranged at the four corners (corner) and its vicinity (near the terminal 32a) 32b
  • the amount of solder paste 41 supplied above is smaller than the amount of solder paste 41 supplied onto the other terminal 32c (that is, the terminal 32c of the terminal 32 other than the terminals 32a and 32b).
  • the opening 43 of the mask 42 has a circular shape
  • the diameter R of the opening 43a is about 60% of the diameter R of the opening 43c
  • the diameter R of the opening 43b is the diameter R of the opening 43c.
  • the amount of solder paste 41 supplied on the terminal 32a of the wiring board 31 is about 36% of the amount of solder paste 41 supplied on the terminal 3 2c, and the terminal adjacent to the terminal 32a.
  • the amount of solder paste 41 supplied onto 32b is about 64% of the amount of solder paste 41 supplied onto terminal 32c.
  • solder paste 41 is printed on the wiring board 31 in this way and the solder (solder paste 41) is supplied onto the terminals 32 of the wiring board 31, as shown in FIG. Mount (place) semiconductor device 1 (step S4).
  • the main surface (ie, the lower surface 12) of the semiconductor device 1 on the side where the solder balls 6 are formed 1S wiring board 31 The semiconductor device 1 is arranged on the upper surface 31a of the wiring board 31 so as to face the main surface (that is, the upper surface 3la) on the side where the terminals 32 are formed.
  • the plurality of terminals 32 of the wiring board 31 and the plurality of solder balls 6 of the semiconductor device 1 are opposed to each other through the solder (solder paste 41) supplied onto the terminals 32 in the solder printing process of step S3.
  • the semiconductor device 1 is aligned and mounted (arranged) on the upper surface 31a of the wiring board 31.
  • each solder ball 6 of the semiconductor device 1 and each terminal 32 of the wiring board 31 are opposed to each other with the solder paste 41 interposed therebetween, so that they substantially overlap in a plane.
  • the solder balls 6 of the semiconductor device 1 can be temporarily fixed to the terminals 32 of the wiring board 31 due to the adhesiveness of the solder paste 41 on the terminals 32 of the wiring board 31.
  • the wiring board 31 on which the semiconductor device 1 is mounted as described above is passed through a reflow furnace (not shown) or the like, thereby heating and melting the solder (solder paste 41 and solder balls 6). Then, the terminal 32 of the wiring board 31 and the solder ball 6 of the semiconductor device 1 are joined.
  • the solder ball 6 of the semiconductor device 1 is integrated with the solder paste 41 supplied onto the terminal 32 to which the solder ball 6 is to be connected, and the solder ball 6 after mounting the semiconductor device 1 is mounted.
  • each solder ball 56 of the semiconductor device 1 is joined to each terminal 32 of the wiring board 31 and electrically connected thereto.
  • the semiconductor device 1 is mounted (solder mounted) on the wiring board 31.
  • the semiconductor device 1 is fixed to the wiring board 31 and a plurality of solder balls 56 (solder balls 6) as external terminals of the semiconductor device 1 are electrically connected to the plurality of terminals 32 of the wiring board 31, respectively.
  • the plurality of electrodes 2a of the semiconductor chip 2 include the plurality of bonding wires 4, the plurality of connection terminals 14, the wiring 15, the conductors and lands 16 in the through holes, and the plurality of solder balls 56 of the wiring board 3. And electrically connected to a plurality of terminals 32 of the wiring board 31.
  • 20 to 23 are cross-sectional views (main-part cross-sectional views) illustrating the mounting process of the semiconductor device of the comparative example, and correspond to FIGS. 15 and 17 to 19 of the present embodiment. .
  • a mask 142 for solder printing is arranged on the wiring board 31.
  • the mask 142 is formed of the same material as the mask 42, and has a plurality of openings 143 for exposing the terminals 32 of the wiring board 31 and supplying the solder paste 41 onto the terminals 32. Yes. Accordingly, the arrangement of the openings 143 in the mask 142 corresponds to the arrangement of the terminals 32 on the wiring board 31 as in the arrangement of the openings 43 in the mask 42.
  • the plurality of openings 143 of the mask 142 used in the solder printing process of the comparative example are all the same in size and have the same area. Are all the same. Such ma
  • the terminals 142 of the wiring board 31 are positioned under the respective openings 143 by arranging the disks 142 on the wiring board 31 so as to be aligned.
  • solder paste 41 is applied on the mask 142 and is stretched by moving the squeegee 144. As a result, the solder paste 41 is collectively supplied onto the main surface of the wiring board 31 and selectively onto the terminals 32 through the openings 143 of the mask 142. Thereafter, as shown in FIG. 21, the force on the wiring board 31 also removes the mask 142. As described above, since the plurality of openings 43 of the mask 142 all have the same size, the solder paste supplied onto the plurality of terminals 32 of the wiring board 31 as shown in FIG. The amount of 41 is the same for all terminals 32.
  • the semiconductor device is placed on the wiring board 31 as shown in FIG. 1 is installed. At this time, the upper surface of the wiring board 31 is opposed to the plurality of terminals 32 of the wiring board 31 and the plurality of solder balls 6 of the semiconductor device 1 via the solder paste 41 supplied onto the terminals 32 in the solder printing process.
  • the semiconductor device 1 is mounted on 31a.
  • FIG. 23 shows the state after the solder reflow process.
  • the solder ball 6 of the semiconductor device 1 is integrated with the solder paste 41 supplied onto the terminal 32 to which the solder ball 6 is to be connected, and the solder after the semiconductor device 1 is mounted.
  • each solder ball 56 of the semiconductor device 1 is joined to each terminal 32 of the wiring board 31 and electrically connected thereto. In this way, the semiconductor device 1 is mounted on the wiring board 31.
  • the semiconductor device 1 is warped before and after being mounted on the wiring board 31. This warpage of the semiconductor device 1 is mainly caused by a difference in thermal expansion coefficient between the wiring board 3 and the sealing resin 5.
  • the semiconductor device 1 When the semiconductor device 1 is warped, the semiconductor device tends to warp in a concave or convex shape along the diagonal directions 51a and 51b of the wiring board 3 shown in FIG. For this reason, the amount of warpage of the wiring board 3 of the semiconductor device 1 is greatest near the four corners (corner portions) of the wiring board 3.
  • the semiconductor device 1 Under a temperature environment of about room temperature, as shown schematically in FIG. 22 (FIG. 18), the semiconductor device 1 has a downwardly convex state (that is, the central portion side of the lower surface 3b of the wiring board 3 is Below the four corners Tend to occur). On the other hand, under a high temperature environment such as during solder reflow, as schematically shown in FIG. 23 (FIG. 19), the semiconductor device 1 is projected upward (that is, the four corners of the lower surface 3b of the wiring board 3 are centered). Tend to occur).
  • the sealing resin 5a and the wiring board 3 are held by a mold when the sealing resin material for forming the sealing resin 5a is cured.
  • the sealing resin 5a is cured without warping.
  • Fig. 22 Fig. 18
  • the semiconductor device 1 is warped in a downwardly convex state.
  • the temperature is increased to a high temperature (higher than the curing temperature of the sealing resin material), which is caused by the difference in the thermal expansion coefficient between the wiring board 3 and the sealing resin 5.
  • FIG. 23 FIG. 19
  • the semiconductor device 1 is warped in a convex state.
  • the semiconductor device 1 when the semiconductor device 1 is mounted on the wiring substrate 31, the semiconductor device 1 is warped in a convex downward state.
  • the semiconductor device 1 warps upward in a convex state.
  • a molten solder ball 56 that is, a solder ball that has been melted and integrated together
  • the solder balls 56) composed of 6 and the solder paste 41 are crushed by the wiring board 3 of the semiconductor device 1 which has warped.
  • the crushed solder flows out and reaches the adjacent solder ball 56, and as shown in FIG. 23, the adjacent solder ball 56 solidified after solder reflow, as shown in FIG.
  • a short (short circuit) point 52 will come into contact with each other. Since the semiconductor device 1 and the wiring board 31 in which the shorted portion 52 is generated need to be selected and removed as defective, such a solder flow failure or short-circuit failure reduces the mounting yield of the semiconductor device.
  • the semiconductor device 1 that has been warped upward during solder reflow is fixed to the wiring board 31 when the solder ball 56 is solidified below the solder melting point after solder reflow. Therefore, after the solder reflow (after the solidification of the solder balls 56), as shown in FIG. 23, the semiconductor device 1 is fixed to the wiring board 31 while being warped upward. That is, the semiconductor device 1 is mounted on the wiring board 31 in a state where the four corners (corner portions) are warped closer to the wiring board 31 than the center side of the lower face 12 (the lower face 3b of the wiring board 3) of the semiconductor device 1. Is done.
  • the openings 43a arranged at the four corners (corners) and the vicinity thereof.
  • the side opening 43b is made smaller than the other openings 43c, so that, among the plurality of terminals 32 of the wiring board 31, the terminal 32a arranged at the four corners (corners) and the terminal 3 in the vicinity thereof are arranged.
  • the amount of the solder paste 41 supplied on 2b is made smaller than the amount of the solder paste 41 supplied on the other terminals 32c.
  • the total amount of solder of the solder paste 41 supplied onto each terminal 32 and the solder ball 6 connected to the terminal 32 is smaller in the terminals 32a and 32b than in the terminal 32c. Therefore, among the solder balls 56 consisting of the solder ball 6 and the solder paste 41 which are melted and integrated during the solder reflow in step S5, the solder ball 56a on the terminal 32a (the solder paste 41 and the solder ball on the terminal 32a) 6a) and the solder ball 56b on the terminal 32b (the solder paste 41 on the terminal 32b and the solder ball 6b are combined together) from the solder ball 56c on the other terminal 32c. However, the size and volume with a small amount of solder become small.
  • the semiconductor device 1 is warped upward during the solder reflow in step S5, and after the solder reflow, the solder ball 56 is solidified to become below the solder melting point, and the semiconductor is formed on the wiring board 31.
  • Device 1 is fixed. For this reason, as shown in FIG. 19, the semiconductor device 1 tends to be mounted and fixed on the wiring board 31 in a state of being warped upward. In other words, the semiconductor device 1 is warped so that the four corners (corner portions) of the lower surface 12 of the semiconductor device 1 (the lower surface 3b of the wiring substrate 3) are closer to the wiring substrate 31 than the central side. Is implemented.
  • the amount of solder paste 41 supplied onto each terminal 32 of the wiring board 31 is reduced at the four corners and the terminals 32a and 32b in the vicinity thereof than the other terminals 32c.
  • the total amount of solder of 41 and solder ball 6 is reduced at the terminals 32a and 32b at the four corners and in the vicinity thereof, and the solder amount of the solder balls 56a and 56b at the four corners and in the vicinity thereof is reduced.
  • Even if warping occurs it is possible to suppress or prevent the solder balls 56a and 56b in the four corners and the vicinity thereof from being crushed by the wiring board 3 (semiconductor device 1) that is warped near the corner of the wiring board 3.
  • the mounting yield of equipment can be improved.
  • the cost of the electronic device manufactured by mounting the semiconductor device 1 on the wiring board 31 can be reduced.
  • the semiconductor device 1 warps, the semiconductor device 1 warps in a direction along the diagonal line of the wiring board 3, and therefore, the warpage amount of the wiring board 3 of the semiconductor device 1 has four corners (corners). Part) neighborhood is the largest. Therefore, the solder ball 56 that is most affected by the warp of the semiconductor device 1 during solder reflow (is easily crushed) is connected to the land 16a of the wiring board 3 and the terminal 32a of the wiring board 31 among the solder balls 56.
  • the solder balls 56a that is, the solder balls 56a at the four corners of the array arrangement. Therefore, control of the solder amount of the solder ball 56a is important to prevent problems due to warpage of the semiconductor device 1 during solder reflow.
  • the size of the opening 43a in the opening 42 of the solder printing mask 42 is 80% or less of the size of the opening 43c, more preferably 60% or less.
  • the opening 43 of the mask 42 can be formed into, for example, a circular shape. In this case, when the opening 42 is circular, the size of the opening 43 can be defined by the diameter. If the diameter of the opening 4 3c is 80% or less of the R dimension (R ⁇ 0. 8R), 60% or less (R ⁇ 0.8R) is more preferable. This warps the semiconductor device 1 during solder reflow.
  • the molten solder ball 56 (especially the solder ball 56a) is more accurately pushed by the wiring substrate 3 of the semiconductor device 1 warped in the vicinity of the corner of the wiring substrate 3 of the semiconductor device 1. This can be suppressed or prevented, and the mounting yield of semiconductor devices can be further improved.
  • the dimensions of the openings 43a and 43b with the smaller dimensions be 10% or more of the dimensions of the other openings 43c.
  • the diameters R and R of the openings 43a and 43b are 0.03 mm or more.
  • the opening 43 can be easily formed in the mask 42 by etching or the like.
  • the solder paste 41 can be accurately supplied onto the terminals 32a and 32b of the wiring board 31.
  • the amount of the solder paste 41 supplied onto each terminal 32 of the wiring board 31 is controlled, and accordingly, the wiring The amount of solder paste 41 supplied onto each terminal 32 of the substrate 31 is reduced at the terminals 32a and 32b.
  • the opening 43 of the mask 42 can be formed by etching or the like, and the size (dimension) of the opening 43 of the mask 42 can be adjusted relatively easily and accurately, so that the solder supplied to each terminal 32 of the wiring board 31
  • the amount of paste 41 can be controlled easily and accurately. Further, since the amount of solder paste 41 supplied onto each terminal 32 of the wiring board 31 can be adjusted simply by preparing the mask 42 with the dimension of the opening 43 adjusted, an increase in the number of processes can be prevented. Further, since the thickness of the mask 42 is almost uniform, the solder printing process using the mask 42 is easy.
  • the openings 43 of the mask 42 are the smallest, so that the amount of the solder paste 41 supplied onto each terminal 32 of the wiring board 31 has four corners. Of terminal 32a. For this reason, among the solder balls 56, the amount of solder ball 56a that is most affected (easily crushed) by the warp of the semiconductor device 1 during solder reflow can be minimized, and the warped semiconductor device 1
  • the wiring board 3 can suppress or prevent the molten solder balls 56a from being crushed.
  • the openings 43b near the openings 43a are referred to as the openings 43a.
  • the amount of solder paste 41 supplied onto the terminal 32b of the wiring board 31 is larger than the amount of solder paste 41 on the terminal 32a and the terminals 32a, Less than the amount of solder paste 41 on the terminals 32c other than 32b.
  • the solder ball 56a has the least amount of solder and is susceptible to warpage of the semiconductor device 1 during solder reflow after the solder balls 56a.
  • the amount of solder of the solder ball 56b can be made larger than the solder ball 56a and smaller than the solder balls 56c other than the solder balls 56a and 56b.
  • solder amount of the solder ball 56 is adjusted in accordance with the susceptibility (easiness of being crushed) of the warp of the semiconductor device 1 during the solder reflow, it is melted by the wiring board 3 of the warped semiconductor device 1.
  • the solder ball 56 (56a, 56b) in the state can be more accurately suppressed or prevented, and the reliability of the electrical connection between the semiconductor device 1 and the wiring board 31 by the solder ball 56 can be further improved.
  • the mounting yield can be further improved.
  • the solder ball 6 and the solder paste 41 can be made of either lead (Pb) -containing solder or lead-free solder that does not contain lead (Pb). 230 ° C) has a higher melting point than lead-containing solder (for example, melting point 190 ° C). For this reason, when lead-free solder is used for at least one of the solder ball 6 and the solder paste 41, the solder reflow in step S5 is compared to when lead-containing solder is used for both the solder ball 6 and the solder paste 41. It is necessary to raise the temperature.
  • step S5 The higher the temperature of the solder reflow process in step S5, the greater the warp of the semiconductor device 1 during the solder reflow, and the solder balls 56 are more likely to be crushed by the wiring substrate 3 of the warped semiconductor device 1. Therefore, when the temperature of the solder reflow in step S5 is high, for example, when lead-free solder is used for at least one of the solder ball 6 or the solder paste 41, the semiconductor device during the solder reflow can be obtained by applying this embodiment. Since the problem due to the warp of 1 can be prevented, it is more effective.
  • the warp of the semiconductor device 1 during the solder reflow in step S5 becomes larger, and the solder balls 56 are more easily crushed by the wiring substrate 3 of the warped semiconductor device 1. . Therefore, when this embodiment is applied when the thickness of the semiconductor device 1 is relatively small, for example, when the thickness T of the semiconductor device 1 is 0.6 mm or less, solder Since the problem due to the warp of the semiconductor device in the flow can be prevented, the effect is greater.
  • the planar dimension of the semiconductor device 1 is larger, the warp of the semiconductor device 1 during the solder reflow in step S5 becomes larger, and the semiconductor in which the solder balls 56 (56a, 56b) in the four corners and the vicinity thereof are warped. It becomes easy to be crushed by the wiring board 3 of the device 1. Therefore, when the planar dimension of the semiconductor device 1 is relatively large, for example, when the length L of the diagonal line of the semiconductor device 1 is about 7 mm or more, the semiconductor device 1 during solder reflow can be applied by applying this embodiment. Since the problem caused by warping can be prevented, it is more effective.
  • the wiring substrate 3 of the semiconductor device 1 when a resin substrate using a resin material for the force-insulating base material layer 11 in which various materials can be used is used as the wiring substrate 3.
  • the warp of the semiconductor device 1 and the warp of the wiring board 3 tend to be particularly large during the solder reflow in step S5.
  • this embodiment when a resin substrate is used for the wiring substrate 3 of the semiconductor device 1, if this embodiment is applied, it is possible to prevent defects caused by the warp of the semiconductor device 1 during solder reflow, and therefore, more effective. large.
  • the semiconductor chip 2 is face-up bonded on the wiring board 3, and the electrode 2 a of the semiconductor chip 2 and the connection terminal 14 of the wiring board 3 are electrically connected by the bonding wire 4.
  • the semiconductor device 1 of the present embodiment is not limited to this, and any semiconductor device can be used as long as it is a semiconductor device that can be mounted (solder mounted) on the wiring board 31 via solder. 1 can be used as the mounting step of the semiconductor device of this embodiment mode.
  • the semiconductor chip 2 is face-down bonded on the wiring board 3 and the bump electrodes of the semiconductor chip 2 are electrically connected to the connection terminals 14 of the wiring board 3 so that the semiconductor device (corresponding to the semiconductor device 1) is obtained. It can also be formed.
  • a part of the semiconductor chip 2 that preferably seals the connection part between the bump electrode of the semiconductor chip 2 and the connection terminal 14 of the wiring board 3 with a sealing resin such as underfill resin is used. ⁇ Sealed with grease.
  • the wiring board 3 of the semiconductor device may be warped during the solder reflow process in step S5. Therefore, the semiconductor device mounting process as in this embodiment is applied. The above effects can be obtained.
  • one of the main causes of the warpage of the semiconductor device (wiring board 3) during solder reflow is the difference in thermal expansion coefficient between the wiring board 3 and the sealing resin 5.
  • the sealing resin 5 is formed on almost the entire upper surface 3a of the board 3 and the entire semiconductor chip 2 is sealed with the resin, warping of the semiconductor device during solder reflow tends to be particularly large. For this reason, if the semiconductor device mounting process of the present embodiment is applied to a semiconductor device in which the semiconductor chip 2 is disposed on the wiring board 3 and at least a part of the semiconductor chip 2 is sealed with resin, the process of step S5 is performed. Although it is possible to improve the mounting yield by preventing problems caused by warpage of the semiconductor device during solder reflow, it is sealed on almost the entire upper surface 3a of the wiring board 3 as in the case of the semiconductor device 1 described above.
  • the semiconductor chip 2 is face-up bonded on the wiring board 3 and the semiconductor chip 2 and the wiring board 3 are connected by the bonding wire 4, and then the semiconductor chip 2 and the bonding wire 4 are connected. If the sealing resin 5 is formed so as to cover the entire semiconductor chip 2 and then the semiconductor device mounting process of this embodiment is applied, the solder reflow in step S5 The semiconductor failure by equipment 1 warpage can more accurately prevented, greater the effect of implementation improvement in yield
  • the shorted portion 52 as shown in FIG. 23 is likely to occur when the pitch of the solder balls 6 of the semiconductor device 1 is small, for example, when the semiconductor device 1 is a CSP type semiconductor device, Since the pitch tends to be small, a short point 52 as shown in FIG. 23 is likely to occur. For this reason, for example, when the semiconductor device 1 with a small pitch of the solder balls 6 is mounted on the wiring board 31 as in the CSP type semiconductor device, if the mounting process of the semiconductor device of the present embodiment is applied, It is possible to prevent problems caused by warping of the semiconductor device 1 during solder reflow, so that the effect is greater.
  • FIG. 24 is a plan view of another form of mask 42a (corresponding to mask 42) and corresponds to FIG.
  • FIG. 25 shows a state in which the solder paste 41 is supplied (printed) onto the terminal 32 of the wiring board 31 using the mask 42a of FIG.
  • FIG. 18 is a cross-sectional view (main part cross-sectional view) corresponding to FIG.
  • the opening 43a at the four corners and the opening 43b in the vicinity thereof have the same size (size, area). Except this, it has the same configuration as the mask 42. Therefore, among the plurality of openings 43 of the mask mask 42a, the openings 43a and 43b are smaller than the openings 43c other than the openings 43a and 43b, but the openings 43a and 43b are substantially the same size. It has become.
  • the opening 43c has a diameter of 0.3 mm
  • the diameter of the opening 43a and the opening 43b can be, for example, about 0.24 mm.
  • the solder paste 41 is supplied onto each terminal 32 of the wiring board 31 using the mask 42a as described above, as in the case where the mask 42 is used.
  • the amount of the solder paste 41 supplied onto the terminals 32a and 32b of the wiring board 31 was made smaller than the amount of the solder paste 41 supplied onto the other terminals 32c, and supplied to the terminals 32a.
  • the amount of the solder paste 41 and the amount of the solder paste 41 supplied onto the terminal 32b can be made substantially the same. Therefore, when the semiconductor device 1 is mounted on the wiring board 31 as described above, the total solder amount of the solder paste 41 and the solder ball 6 can be reduced at the terminals 32a and 32b. Even if warpage occurs, the wiring board 3 of the semiconductor device 1 warped in the vicinity of the corner of the wiring board 3 can suppress or prevent the solder balls 56a and 56b in the four corners and the vicinity thereof from being crushed. Yield can be improved.
  • the openings 43b in the vicinity of the openings 43a formed by only the openings 43a at the four corners (for example, the openings 43b adjacent to the openings 43a) ) was also smaller than the openings 43c other than the openings 43a and 43b.
  • Figure 2 6 is a plan view of still another form of mask 42b (corresponding to mask 42), and corresponds to FIG.
  • FIG. 27 is a cross-sectional view (main cross-sectional view) showing a state in which the solder paste 41 is supplied (printed) onto the terminal 32 of the wiring board 31 using the mask 42b of FIG. Corresponding.
  • the mask 42b shown in FIG. 26 has an opening 43b in the vicinity of the opening 43a at the four corners (here, the opening 43b adjacent to the opening 43a) has the same size as the opening 43c.
  • the configuration is the same as that of the mask 42. Accordingly, among the plurality of openings 43 of the mask 42b, only the opening 43a at the four corners is smaller than the openings 43b and 43c other than the opening 43a, and the sizes of the openings 43b and 43c other than the opening 43a are substantially the same. It is.
  • the opening 43 of the mask 42b can have a circular shape or the like.
  • the diameter R of the opening 43a at the four corners is set to the opening 43b, 43c other than the opening 43a.
  • the openings 43b and 43c are substantially the same.
  • the diameter of the opening 43a can be about 0.18 mm, for example.
  • the size of the opening 43a (corresponding to the diameter when the opening 43 is circular) should be 80% or less of the size of the openings 43b and 43c. More preferably 60% or less is even more preferable.
  • the semiconductor device 1 when the semiconductor device 1 is mounted on the wiring board 31 as described above, the total solder amount of the solder paste 41 and the solder ball 6 can be reduced by the terminals 32a at the four corners. Even if warpage occurs, it is possible to suppress or prevent the solder balls 56a at the four corners from being pushed by the wiring board 3 of the semiconductor device 1 that has warped in the vicinity of the corners of the wiring board 3, thereby improving the mounting yield of the semiconductor device. Can be made.
  • the corners (four corners) of the openings 43a are relatively reduced in size.
  • the amount of the solder paste 41 supplied onto the terminals 32a at the corners (four corners) is relatively small, as described above. It is possible to prevent the solder balls from being crushed by warping of the semiconductor device 1 during reflow, and to improve the mounting yield of the semiconductor device. That is, even when the size (area) of the opening 43b adjacent to the opening 43a is substantially the same as that of the opening 43c, as in the mask 42b in FIG.
  • the solder ball due to warpage of the semiconductor device 1 during solder reflow It is possible to obtain the effect of preventing crushing and improving the mounting yield of the semiconductor device.
  • the dimensions (area) of the opening 43b adjacent to the opening 43a that is formed only by the opening 43a, such as the masks 42 and 42a are also relatively reduced, so that the terminal 32a is formed by using only the terminal 32a.
  • the amount of the solder paste 41 supplied onto the adjacent terminal 32b is also reduced.
  • the solder balls are crushed by the wiring board 3 of the semiconductor device 1 warped in the vicinity of the corner of the wiring board 3. Can be prevented more accurately, and the mounting yield of semiconductor devices can be further improved.
  • the four corner terminals 32a or the four corners and the neighboring terminals 32a and 32b Supply a smaller amount of solder (solder paste 41) than the other terminals.
  • FIG. 28 is a bottom view of a semiconductor device la according to another embodiment of the present invention
  • FIGS. 29 and 30 are cross-sectional views thereof.
  • FIGS. 28 to 30 correspond to FIGS. 2, 4 and 5 of the first embodiment, respectively
  • FIGS. 31 to 34 correspond to FIGS. 6 and 8 to 10 of the first embodiment, respectively. To do.
  • the power of semiconductor device 1 of the first embodiment in which semiconductor chip 2 is placed (mounted) on wiring board 3 is the same as that of semiconductor device la of the present embodiment. Then, the semiconductor chip 2 is disposed in the opening 61 of the wiring board 3, and the back surface of the semiconductor chip 2 is exposed from the lower surface 12 of the semiconductor device la. Also in the semiconductor device la, the electrode 2a of the semiconductor chip 2 is electrically connected to the connection terminal 14 of the wiring board 3 through the bonding wire 4.
  • the sealing resin 5 is formed on the wiring board 3 so as to cover the semiconductor chip 2 and the bonding wires 4, and the solder balls 6 are arranged in an array on the lower surface 3b of the wiring board 3.
  • the space between the side wall of the opening 61 of the wiring board 3 and the semiconductor chip 2 is also filled with the sealing resin 5. Accordingly, the semiconductor chip 2 is sealed with the sealing resin 5 except for the back surface. Since the other configuration of the semiconductor device la is almost the same as that of the semiconductor device 1 of the first embodiment, the description thereof is omitted here.
  • the semiconductor device la having such a configuration can be manufactured, for example, as follows.
  • a wiring board 21c having the same configuration as that of the wiring board 21 of the first embodiment is prepared except that the opening 61 is provided at the center of each semiconductor device region 22. To do. Then, a film member (adhesive film) 62 is attached to the lower surface 21b of the wiring board 21c so as to close the opening 61.
  • the semiconductor chip 2 is mounted on the film member 62 in the opening 61 of each semiconductor device region 22 of the wiring board 21c (from the upper surface 21a side of the wiring board 21c). Bonding). If one main surface of the film member 62 is adhesive, the adhesive surface of the film member 62 causes the film member 62 to adhere to the lower surface 21b of the wiring board 21c and the semiconductor to the film member 62. Chip 2 can be bonded.
  • each electrode 2 a of the semiconductor chip 2 and the connection terminal 14 formed on the corresponding wiring board 21 c are electrically connected via the bonding wire 4.
  • resin sealing is performed by a molding process to form a sealing resin 5a, and the semiconductor chip 2 and the bonding wire 4 are sealed with the sealing resin 5a.
  • a sealing resin 5 is formed on the wiring board 3 so as to cover the semiconductor chip 2 and the bonding wires 4, and the gap between the side wall of the opening 61 of the wiring board 3 and the semiconductor chip 2 is also sealed. Filled with fat 5.
  • solder balls 6 are connected (joined) to the lands 16 on the lower surface 21b of the wiring board 21c.
  • the wiring substrate 21c and the sealing resin 5a formed thereon are cut (diced) into the respective semiconductor device regions 22 to be separated (divided) into individual pieces. Then, by peeling off the film member 62, the semiconductor device la as shown in FIGS. 28 to 30 can be manufactured. .
  • the wiring substrate 21c cut and separated (divided) into each semiconductor device region 22 corresponds to the wiring substrate 3 of the semiconductor device 1a, and the sealing resin 5a cut and separated (separated) into each semiconductor device region 22 is formed. Corresponds to sealing resin 5.
  • Such a semiconductor device la can also be mounted on the wiring board 31 in the same manner as the semiconductor device 1 of the first embodiment, but the description thereof is omitted here.
  • the thickness of the semiconductor device la is made thinner than when the semiconductor chip 2 is mounted on the wiring board 3. can do.
  • the warp of the semiconductor device la during solder reflow during mounting on the wiring board 31 tends to increase. For this reason, in the semiconductor device la of the present embodiment, if the mounting process as in the first embodiment is applied, problems due to warpage of the semiconductor device la during solder reflow can be prevented, and thus the effect is greater.
  • the semiconductor chip 2 is arranged on the wiring board 3, and at least a part of the semiconductor device 1 is sealed with the sealing resin portion 5 and the semiconductor device 1 is used.
  • the semiconductor device la in which the semiconductor chip 2 is arranged in the opening 61 of the wiring board 3 and at least a part is sealed with the sealing resin portion 5 as in the embodiment is described in the following Embodiments 4 to 4. It can also be applied to 7.
  • FIG. 35 is a bottom view of a semiconductor device lb according to another embodiment of the present invention and corresponds to FIG. 2 of the first embodiment.
  • FIG. 36 is a top view (main part plan view) of a wiring board (mounting board) 31b for mounting the semiconductor device lb, and corresponds to FIG. 13 of the first embodiment.
  • FIG. 37 is a plan view (principal part plan view) of a mask 42c used in the process of mounting the semiconductor device lb on the wiring board 31b, and corresponds to FIG. 14 of the first embodiment.
  • FIG. 38 is a cross-sectional view (main cross-sectional view) showing a state in which the solder paste 41 is supplied (printed) onto the terminals 32 of the wiring board 31b of FIG. 36 using the mask 42c of FIG. 37. It corresponds to 17.
  • the semiconductor device lb of the present embodiment shown in FIG. 35 has a wiring board in which a plurality of solder balls 6 are arranged in an array (area array) over almost the entire bottom surface 3b of the wiring board 3. Three The land 16 is joined. Since the other configuration of the semiconductor device lb is substantially the same as that of the semiconductor device 1 of the first embodiment, the description thereof is omitted here.
  • the wiring board 31b is a mounting board for mounting the semiconductor device lb, and the terminal 32 of the wiring board 31b faces the solder ball 6 when the semiconductor device lb is mounted on the wiring board 31b ( (Overlapping in a plane) is arranged. Therefore, when the solder balls 6 are arranged in an array on the entire bottom surface 3b of the wiring board 3 of the semiconductor device lb as shown in FIG. 35, the semiconductor device lb of the wiring board 31b is mounted as shown in FIG.
  • the arrangement of the terminals 32 in the planned area corresponds to the arrangement of the solder balls 6 in the semiconductor device lb, and is arranged in an array (in an area array). Since the other configuration of the wiring board 3 lb is almost the same as that of the wiring board 31 of the first embodiment, the description thereof is omitted here.
  • the mask 42c shown in FIG. 37 has a plurality of openings 43 for supplying the solder paste 41 on the terminals 32 of the wiring board 31b of FIG. 36, and the openings 42 in the mask 42c
  • the arrangement corresponds to the arrangement of the terminals 32 on 3 lb of the wiring board, and is arranged in an array (area array).
  • Other configurations of the mask 41c are substantially the same as the masks 42, 42a, and 42b of the first embodiment.
  • the mask 42c of the present embodiment is also arranged at the four corners among the plurality of openings 43 arranged in an array.
  • the opening 43a and the opening 43b in the vicinity thereof are made smaller than the openings 43c other than the openings 43a and 43b.
  • the semiconductor device lb can be mounted on the wiring board 31b in the same manner as in the first embodiment. That is, the solder paste 41 is supplied onto the plurality of terminals 32 of the wiring board 31b using the mask 42c.
  • the mask 42c As shown in FIG. 38, as in the first embodiment, among the terminals 32 of the wiring board 31b, they are supplied onto the terminal 32a at the four corners and the terminal 32b in the vicinity thereof.
  • the amount of solder paste 41 is smaller than the amount of solder paste 41 supplied on the other terminal 32c.
  • the semiconductor device lb can be mounted on the wiring board 31b (solder mounting). Since these mounting processes are the same as those in the first embodiment, they are illustrated and described here. Detailed description is omitted.
  • substantially the same effect as in the first embodiment can be obtained. That is, as in the first embodiment, in the present embodiment, among the opening 43 of the mask 42c, the openings 43a and 43b are made smaller than the opening 43c.
  • the amount of the solder paste 41 supplied above can be made smaller at the terminal 32a at the four corners and at the terminal 32b in the vicinity thereof than at the other terminals 32c.
  • wiring is performed as in the present embodiment in which only the semiconductor device 1 provided with the solder balls 6 arranged in an array on the outer peripheral portion of the lower surface 3b of the wiring board 3 is used.
  • a semiconductor device lb in which solder balls 6 are arranged in an array on almost the entire outer periphery of the lower surface 3b of the substrate 3 can also be applied to Embodiments 4 to 7 described later.
  • FIG. 39 is a plan view (top view) of the mask 42d used in the process of mounting the conductor device 1 of this embodiment on the wiring board 31.
  • FIG. 40 to 42 are cross-sectional views (main-part cross-sectional views) illustrating the mounting process of the semiconductor device 1 of the present embodiment onto the wiring board 31.
  • FIG. 39 to 42 correspond to FIG. 14, FIG. 15, FIG. 17, and FIG. 19 of the first embodiment, respectively.
  • the cross section of the mask 42 in FIG. 40 corresponds to the cross section of the GG line in FIG.
  • the semiconductor device 1 similar to that of the above-described first embodiment is mounted on the wiring board 31 similar to that of the above-described first embodiment, but is used for solder printing in step S3 during this mounting.
  • the mask (metal mask, solder printing mask) 42d is different from the masks 42, 42a, 42b of the first embodiment!
  • the masks 42, 42a, 42b of the first embodiment have a substantially uniform thickness, and the size (planar dimensions, area) of the opening 43 is small at the four corners (corner portions) and in the vicinity thereof. And then.
  • the thickness of the mask 42d is not uniform.
  • the thickness of the mask 42d is relatively thin at 43a and the opening 43b in the vicinity thereof, and the thickness of the mask 42d is relatively thick at the openings 43c other than the openings 43 and 43b.
  • Other configurations of the mask 41d are substantially the same as the mask 42 of the first embodiment.
  • the mask 42d can be prepared, for example, by forming the opening 43 by etching or the like after the metal plate is subjected to the no fetching to partially reduce the thickness. At this time, the half etching is performed so that the thickness of the metal plate in the regions where the openings 43a and 43b are to be formed becomes thinner than the thickness of the metal plate in the region where the openings 43c are to be formed.
  • the mask 42d has the thin film portion 71a having a relatively small thickness and the thick film portion 71b having a relatively large thickness.
  • the thickness of the thin film portion 71a of the mask 42d is thinner than the thickness of the thick film portion 71b.
  • Openings 43a and 43b are formed in the thin film portion 71a of the mask 42d, and openings 43c are formed in the thick film portion 71b of the mask 42d.
  • the mask 42d has four corner openings 43a compared to the thickness of the mask 42d (thickness of the thick film portion 71b) t in the opening 43c other than the openings 43a and 43b where the thickness is not uniform.
  • the thickness of the mask 42d at the opening 43b in the vicinity thereof (thickness of the thin film portion 71a) t is relatively thin (t ⁇ t).
  • the thickness t of the mask 42d at the opening 43a is t at the opening 43c. trout
  • the thickness of 42d is less than 80% of the thickness t (t ⁇ 0.8t), 60% or less (t ⁇ 0.6t)
  • the thickness t of the mask 42d at the opening 43a is 10% or more of the thickness t of the mask 42d at the opening 43c (t ⁇ 0
  • the semiconductor device 1 is mounted on the wiring board 31 in substantially the same manner as in the first embodiment except that the mask 42d having such a configuration is used. That is, as shown in FIG. 40, a mask 42d is arranged on a wiring board 31d, and as shown in FIG. 41, a solder paste 41 is applied onto a plurality of terminals 32 of the wiring board 31 by a printing method using the mask 42d. As shown in FIG. 42, the semiconductor device 1 is mounted on the wiring board 31 and solder reflow processing is performed, so that the semiconductor device 1 can be mounted on the wiring board 31 (solder mounting).
  • the amount of the solder paste 41 supplied onto each terminal 32 is proportional to the area of each opening 43 of the mask 42d. It is also proportional to the thickness of the mask 42d. That is, the planar shape of the solder paste 41 supplied onto each terminal 32 of the wiring board 31 substantially corresponds to the planar shape of the opening 43 that has passed through, and the solder paste supplied onto each terminal 32 of the wiring board 31. The thickness of 41 substantially corresponds to the thickness of the mask 42d at the opening 43 that has passed through.
  • the size (planar dimension, area) of the opening 43 is made uniform, and the thickness thereof is reduced (t ⁇ t) by the openings 43a and 43b. For this reason, it is shown in Figure 40.
  • the plurality of terminals 32 of the wiring board 31 are arranged at the four corners (corner portions) as shown in FIG. Thickness of solder paste 41 supplied on terminal 32a and its neighboring terminal 32b (here, terminal 32b adjacent to terminal 32a) t 1S supplied on terminal 32c other than terminals 32a and 32b
  • the thickness of the solder paste 41 is smaller than the thickness t (t ⁇ t). For this reason, on terminals 32a and 32b
  • the amount of solder paste 41 supplied to the terminal is smaller than the amount of solder paste 41 supplied onto the terminals 32c other than the terminals 32a and 32b.
  • the total solder amount of the solder paste 41 supplied onto each terminal 32 and the solder ball 6 connected thereto is the terminal 32a, 32b is the terminal.
  • the present embodiment it is possible to obtain substantially the same effect as in the first embodiment. That is, it is possible to suppress or prevent the molten solder balls 56a and 56b from being crushed by the wiring board 3 of the semiconductor device 1 that has warped in the vicinity of the corner of the wiring board 3 having the largest amount of warping. For this reason, it is possible to suppress or prevent the collapsed solder from flowing out and reaching the adjacent solder balls 56 and shorting between the adjacent solder balls 56 solidified after the solder reflow. Thereby, the mounting yield of the semiconductor device can be improved.
  • the force with which the openings 43 arranged in an array are formed in the mask 42d At least the thickness of the mask 42d at the openings 43a at the corners (four corners) is relatively thinned. Arrangement If the amount of the solder paste 41 supplied to at least the corners (four corners) of the terminals 32 formed on the wire substrate 31 and regularly arranged is reduced, as described above, The mounting yield of the semiconductor device can be improved by preventing the solder ball from being crushed by the warp of the semiconductor device 1.
  • the warp of the semiconductor device 1 during solder reflow causes soldering. It is possible to obtain the effect of preventing the balls from being crushed and improving the mounting yield of the semiconductor device.
  • the thickness of the mask 42d at the opening 43b adjacent to the opening 43a which is not only the thickness of the mask 42d at the opening 43a, is also relatively reduced, so that only the terminal 32a is obtained. If the amount of the solder paste 41 supplied on the terminal 32b adjacent to the terminal 32a is reduced, it is more preferable. As a result, the wiring board of the semiconductor device 1 is warped near the corner of the wiring board 3. 3 can prevent the solder balls from being crushed more accurately, and can further improve the mounting yield of the semiconductor device.
  • the amount of the solder paste 41 supplied onto each terminal 32 of the wiring board 31 is adjusted to prevent a problem due to the warp of the semiconductor device 1 during the solder reflow.
  • the solder amount of the solder balls 6 of the semiconductor device lc problems due to warpage of the semiconductor device lc during solder reflow are prevented.
  • FIG. 43 is a bottom view of a semiconductor device lc according to another embodiment of the present invention
  • FIG. 44 is a cross-sectional view thereof.
  • the cross section taken along the line H—H in FIG. 43 almost corresponds to FIG. 45 and 46 are cross-sectional views (main-part cross-sectional views) showing the mounting process of the semiconductor device lc on the wiring board 31.
  • FIG. 43 to 46 correspond to FIG. 2, FIG. 5, FIG. 18, and FIG. 19 of the first embodiment, respectively.
  • solder balls 6 are joined to the lower surface 3b of the wiring board 3, and the solder balls (bump electrodes) 6 have substantially uniform dimensions (solder amount).
  • the size (solder amount) of the plurality of solder balls (bump electrodes) 6 is not uniform.
  • the solder balls 6a arranged at the four corners (corner portions) and the vicinity thereof (near the solder balls 6a) of the solder balls 6b
  • the size (dimension) is made smaller than the size (dimension) of the solder ball 6c other than the solder balls 6a and 6b, so that the solder amount of the solder balls 6a and 6b is larger than the solder amount of the solder ball 6c. It is also less. Since the other configuration of the semiconductor device lc is almost the same as that of the semiconductor device 1 of the first embodiment, the description thereof is omitted here.
  • a plurality of solder balls 6 are arranged on the outer peripheral portion of the lower surface 12 of the semiconductor device lc (the lower surface 3b of the wiring board 3).
  • a plurality of solder balls 6 are arranged on the entire surface of the lower surface 12 of the semiconductor device 1c (the lower surface 3b of the wiring board 3). Can also be arranged.
  • solder balls 6a arranged at the four corners (corner portions) and the solder balls 6b in the vicinity thereof are connected to the solder balls 6a.
  • Smaller than 6b solder balls other than 6b (less solder amount).
  • the diameter (dimension) of the solder ball 6a is 80 of the diameter (dimension) B of the solder ball 6c. % Or less (B ⁇ 0.8B) 60% or less (B ⁇ 0.6B)
  • the wiring board is used.
  • solder balls 6a and 6b having relatively small diameters (dimensions) are arranged on the land 16a at the four corners and the land 16b in the vicinity thereof.
  • Solder balls 6c having a relatively large diameter (dimensions) are placed on the lands 16c other than 16a and 16b, solder is reflowed to melt the solder, and the solder balls 6 and the land on the lower surface 21b of the wiring board 21 are disposed. 16 is joined and electrically connected. Since other manufacturing processes of the semiconductor device lc are almost the same as those of the first embodiment, description thereof is omitted here.
  • the manufacturing processes of the semiconductor device lc are almost the same as those of the first embodiment, description thereof is omitted here.
  • the semiconductor device lc can be mounted on the wiring board 31 in substantially the same manner as in the first embodiment.
  • the size of the opening 43 of the mask 42 for solder printing on the wiring board 31 is large.
  • the thickness of the mask 42 can be made uniform.
  • the amount of the solder paste 41 supplied onto each terminal 32 of the wiring board 31 is almost the same in any terminal 32.
  • the solder balls 6a and 6b are made smaller than the solder balls 6c other than the solder balls 6a and 6b to reduce the amount of solder, the solder balls 6a and 6b are supplied onto the terminals 32.
  • the total solder amount of the solder paste 41 and the solder ball 6 connected thereto is smaller at the terminals 32a and 32b than at the terminal 32c.
  • solder balls 56a and 56b that is, fused and integrated on the terminals 32a arranged at the four corners and the terminals 32b in the vicinity thereof
  • Solder paste 41 and solder balls 6a and 6b and solder balls 56a and 56b which are powerful, reduce the amount of solder and reduce the size. Therefore, as shown in FIG. 46, even if the semiconductor device lc warps upward during solder reflow, the solder ball 56a at the four corners of the plurality of solder balls 56 and the vicinity thereof are positioned.
  • Solder balls 56b to be placed have a small amount of solder and are small in size, so that the solder balls 56a and 56b in the molten state are crushed by the wiring board 3 of the semiconductor device 1 that has warped in the vicinity of the corner of the wiring board 3 with the largest amount of warping. Can be suppressed or prevented. As a result, the crushed solder flows out to reach the adjacent solder ball 56, and it is possible to suppress or prevent short-circuiting (short circuit) between the adjacent solder balls 56 solidified after the solder reflow.
  • the mounting yield of the apparatus can be improved.
  • solder balls 6 bonded to the semiconductor device lc and arranged in an array the solder balls 6a at least at the corners (four corners) are relatively small, so that the solder reflow is performed as described above. It is possible to improve the mounting yield of the semiconductor device by preventing the solder balls from being crushed by the warp of the semiconductor device lc. That is, in the semiconductor device lc, even when the solder ball 6b adjacent to the solder ball 6a is approximately the same size as the solder ball 6c, the solder ball is crushed by the warp of the semiconductor device lc during solder reflow. It is possible to obtain the effect of preventing and improving the mounting yield of the semiconductor device.
  • solder ball 6b adjacent to the solder ball 6a that is connected only by the corner (four corners) solder ball 6a is also smaller than the solder ball 6c. It is possible to more accurately prevent the solder balls from being pushed by the wiring substrate 3 of the warped semiconductor device lc, and to improve the mounting yield of the semiconductor device.
  • FIG. 47 is a bottom view of a semiconductor device Id according to another embodiment of the present invention, and corresponds to FIG. 2 of the first embodiment.
  • 48 and 49 are cross-sectional views (main-part cross-sectional views) showing the process of mounting the semiconductor device Id on the wiring board 31 and correspond to FIGS. 18 and 19 of the first embodiment. .
  • the semiconductor device 1 according to the first embodiment described above has a force for arranging a plurality of solder balls 6 in an array on the lower surface 12 of the semiconductor device 1 (the lower surface 3 b of the wiring board 3).
  • Part No.) of the solder ball 6a is the semiconductor device Id of the present embodiment. That is, as shown in FIG. 47, the semiconductor device Id of the present embodiment has a force array arrangement in which a plurality of solder balls 6 are arranged on the lower surface 12 of the semiconductor device Id (the lower surface 3b of the wiring board 3). Solder balls 6 are not provided at the four corners (corners). Since the other configuration of the semiconductor device Id is substantially the same as that of the semiconductor device 1 of the first embodiment, the description thereof is omitted here.
  • the semiconductor device Id can be mounted on the wiring board 31 in substantially the same manner as in the first embodiment.
  • the size of the opening 43 of the mask 42 for solder printing on the wiring board 31 is large.
  • the thickness of the mask 42 can be made uniform.
  • the amount of the solder paste 41 supplied onto each terminal 32 of the wiring board 31 is almost the same in any terminal 32.
  • the semiconductor device Id is mounted on the wiring board 31 as shown in FIG. 48, and the semiconductor device Id is mounted on the wiring board 31 by performing the solder reflow process as shown in FIG. be able to.
  • solder balls 56 in the molten state of the wiring board 3 of the warped semiconductor device 1 try to crush, but the semiconductor of this embodiment
  • the solder balls 6 since the solder balls 6 are not provided at the four corners (corners) of the array arrangement, the solder balls 6 (solder balls 56) that are easily crushed in the vicinity of the corners of the wiring board 3 having the largest warping amount are provided. not exist. For this reason, it is possible to suppress or prevent short-circuiting between adjacent solder balls 56 solidified after solder reflow by flowing out of the crushed solder and reaching the adjacent solder balls 56, thereby reducing the semiconductor device.
  • the mounting yield can be improved.
  • terminals 32 are arranged in an array on the wiring board 31 shown in FIGS. 48 and 49, but the four corner solder balls 6 in the array are not provided in the semiconductor device Id.
  • V that is, eliminate the terminal 32a
  • the terminals 32 of the wiring board 31 are not provided at the four corners (corners) of the array arrangement.
  • the semiconductor device Id in FIG. 47 corresponds to the semiconductor device 1 of the first embodiment in which the solder balls 6a are eliminated, but the semiconductor device Id is replaced with the semiconductor device 1 of the first embodiment.
  • the solder balls 6a and 6b can be eliminated.
  • the total number of solder balls 6 that are external terminals of the semiconductor device Id is reduced (decreased by the solder balls 6a and 6b). Do not provide solder balls only at the four corners (corners) of the array as shown in Figure 4-7! / It is effective to do so.
  • FIG. 50 is a process flow diagram showing another mounting process of the semiconductor device 1 and corresponds to FIG. 11 of the first embodiment.
  • Embodiments 1 to 6 it is possible to suppress or prevent problems caused by warpage of semiconductor device 1 during solder reflow in step S5, but warpage of semiconductor device 1 during solder reflow is too large. If it is too much, this defect cannot be completely prevented, and after mounting on the wiring board 31, it is necessary to select and remove it as a defective mounting product. This is because not only the semiconductor device 1 but also the wiring board 31 on which the semiconductor device 1 is mounted becomes a defective product, so that the cost of the electronic device manufactured by mounting the semiconductor device 1 on the wiring board 31 is increased.
  • the semiconductor device 1 warps downward in a temperature environment of about room temperature, and the semiconductor device 1 in a high temperature environment such as during solder reflow.
  • the warp of the semiconductor device 1 in a temperature environment of about room temperature increases, the warp of the semiconductor device 1 in a high temperature environment such as during solder reflow (convex upward)
  • the warpage amount of semiconductor device 1 is measured (step S1). Step Sl l).
  • the amount of warpage of the semiconductor device 1 can be measured, for example, by laser measurement. Then, the semiconductor device 1 having a large warp amount is selected and removed, and the semiconductor device 1 having a warp amount equal to or less than a reference value is used for mounting on the wiring board 31. That is, in step S4, the semiconductor device 1 having a warpage amount equal to or less than the reference value is mounted on the wiring board 31.
  • the other steps can be performed in substantially the same manner as in the first to sixth embodiments, and the description thereof is omitted here.
  • the semiconductor device 1 after the semiconductor device 1 is manufactured, before the semiconductor device 1 is mounted on the wiring board 31, the amount of warpage of the semiconductor device 1 is measured, and only the semiconductor device 1 whose warpage amount is equal to or less than the quasi-value Is mounted on the wiring board 31. For this reason, the semiconductor device 1 that may greatly warp during the solder reflow in step S5 can be excluded in advance, and the warpage of the semiconductor device 1 during the solder reflow in step S5 can be suppressed. Therefore, the effects obtained in Embodiments 1 to 6 can be further enhanced. Thereby, the mounting yield of the semiconductor device can be further improved.
  • the present invention is suitable for application to, for example, a technique for mounting a semiconductor device in the form of a semiconductor package on a wiring board via solder, a solder-mounted semiconductor device, or the like.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

La présente invention décrit un dispositif à semi-conducteurs (1) disposant de billes de soudure (6) agencées sur sa face inférieure et qui est fixé sur un substrat de câblage (31), il est soumis à un traitement de reflux de soudure afin de connecter électriquement les billes de soudure (6) aux bornes (32) du substrat de câblage (31). Avant que le dispositif à semi-conducteurs (1) ne soit monté, une pâte de soudure (41) est envoyée sur les bornes (32) du substrat de câblage (31). Parmi les bornes en réseau (32) du substrat de câblage (31), les bornes à quatre coins (32a) ou les bornes à quatre coins et adjacentes (32a, 32b) reçoivent moins de pâte de soudure (41) que les autres bornes (32c).
PCT/JP2005/005876 2005-03-29 2005-03-29 Dispositif a semi-conducteurs et son procede de montage WO2006106564A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2005/005876 WO2006106564A1 (fr) 2005-03-29 2005-03-29 Dispositif a semi-conducteurs et son procede de montage

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PCT/JP2005/005876 WO2006106564A1 (fr) 2005-03-29 2005-03-29 Dispositif a semi-conducteurs et son procede de montage

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102034779A (zh) * 2009-10-08 2011-04-27 台湾积体电路制造股份有限公司 具有坚固的拐角凸块的芯片设计
JP2011192852A (ja) * 2010-03-16 2011-09-29 Casio Computer Co Ltd 半導体装置の製造方法及び半導体装置の実装方法
CN110326101A (zh) * 2017-02-21 2019-10-11 京瓷株式会社 布线基板、电子装置及电子模块

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005011921A (ja) * 2003-06-18 2005-01-13 Toshiba Corp 電子装置、プリント基板、印刷マスクおよび電子装置の製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005011921A (ja) * 2003-06-18 2005-01-13 Toshiba Corp 電子装置、プリント基板、印刷マスクおよび電子装置の製造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102034779A (zh) * 2009-10-08 2011-04-27 台湾积体电路制造股份有限公司 具有坚固的拐角凸块的芯片设计
JP2011192852A (ja) * 2010-03-16 2011-09-29 Casio Computer Co Ltd 半導体装置の製造方法及び半導体装置の実装方法
CN110326101A (zh) * 2017-02-21 2019-10-11 京瓷株式会社 布线基板、电子装置及电子模块
EP3588548A4 (fr) * 2017-02-21 2021-01-06 Kyocera Corporation Substrat de câblage, dispositif électronique et module électronique
US11024554B2 (en) 2017-02-21 2021-06-01 Kyocera Corporation Wiring substrate, electronic device, and electronic module
CN110326101B (zh) * 2017-02-21 2024-02-02 京瓷株式会社 布线基板、电子装置及电子模块

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