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WO2006038991A3 - Systeme, appareil et procede pour predire differents types d'acces a une memoire et pour gerer des predictions associees a une memoire cache - Google Patents

Systeme, appareil et procede pour predire differents types d'acces a une memoire et pour gerer des predictions associees a une memoire cache Download PDF

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Publication number
WO2006038991A3
WO2006038991A3 PCT/US2005/029135 US2005029135W WO2006038991A3 WO 2006038991 A3 WO2006038991 A3 WO 2006038991A3 US 2005029135 W US2005029135 W US 2005029135W WO 2006038991 A3 WO2006038991 A3 WO 2006038991A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory
cache
speculator
program instructions
processor
Prior art date
Application number
PCT/US2005/029135
Other languages
English (en)
Other versions
WO2006038991A2 (fr
Inventor
Ziyad S Hakura
Radoslav Danilak
Brad W Simeral
Brian Keith Langendorf
Stefano A Pescador
Dmitry Vyshetsky
Original Assignee
Nvidia Corp
Ziyad S Hakura
Radoslav Danilak
Brad W Simeral
Brian Keith Langendorf
Stefano A Pescador
Dmitry Vyshetsky
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/921,026 external-priority patent/US7206902B2/en
Priority claimed from US10/920,610 external-priority patent/US7441087B2/en
Priority claimed from US10/920,682 external-priority patent/US7461211B2/en
Priority claimed from US10/920,995 external-priority patent/US7260686B2/en
Application filed by Nvidia Corp, Ziyad S Hakura, Radoslav Danilak, Brad W Simeral, Brian Keith Langendorf, Stefano A Pescador, Dmitry Vyshetsky filed Critical Nvidia Corp
Priority to CN2005800270828A priority Critical patent/CN101002178B/zh
Priority to JP2007527950A priority patent/JP5059609B2/ja
Publication of WO2006038991A2 publication Critical patent/WO2006038991A2/fr
Publication of WO2006038991A3 publication Critical patent/WO2006038991A3/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G06F9/3832—Value prediction for operands; operand history buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Debugging And Monitoring (AREA)

Abstract

L'invention concerne un système, un appareil et un procédé pour prédire des accès à une mémoire. Selon un mode de réalisation, un appareil présenté à titre d'exemple comprend un processeur configuré pour exécuter des instructions de programme et des données de programme de processus, une mémoire contenant ces instructions et données de programme ainsi qu'un processeur de mémoire. Ce processeur de mémoire peut comporter un spéculateur configuré pour recevoir une adresse contenant les instructions de programme ou les données de programme. Ce spéculateur peut comporter un prédicteur séquentiel et un prédicteur non séquentiel servant à générer, respectivement, un nombre configurable d'adresses séquentielles et non séquentielles. Selon un autre mode de réalisation, un prélecteur met en oeuvre l'appareil. Selon divers modes de réalisation, le spéculateur peut également comporter n'importe quel élément parmi un expéditeur, un suppresseur, un inventaire, un filtre d'inventaire, un filtre post-inventaire et une mémoire cache à retour de données comprenant, notamment, une mémoire cache à court terme et une à long terme.
PCT/US2005/029135 2004-08-17 2005-08-16 Systeme, appareil et procede pour predire differents types d'acces a une memoire et pour gerer des predictions associees a une memoire cache WO2006038991A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN2005800270828A CN101002178B (zh) 2004-08-17 2005-08-16 用于对存储器的各种访问类型进行预测的预取器
JP2007527950A JP5059609B2 (ja) 2004-08-17 2005-08-16 メモリへの様々なタイプのアクセスを予測するため、およびキャッシュメモリに関連付けられた予測を管理するための、システム、装置、および方法

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US10/921,026 US7206902B2 (en) 2004-08-17 2004-08-17 System, apparatus and method for predicting accesses to a memory
US10/921,026 2004-08-17
US10/920,610 2004-08-17
US10/920,610 US7441087B2 (en) 2004-08-17 2004-08-17 System, apparatus and method for issuing predictions from an inventory to access a memory
US10/920,682 2004-08-17
US10/920,682 US7461211B2 (en) 2004-08-17 2004-08-17 System, apparatus and method for generating nonsequential predictions to access a memory
US10/920,995 US7260686B2 (en) 2004-08-17 2004-08-17 System, apparatus and method for performing look-ahead lookup on predictive information in a cache memory
US10/920,995 2004-08-17

Publications (2)

Publication Number Publication Date
WO2006038991A2 WO2006038991A2 (fr) 2006-04-13
WO2006038991A3 true WO2006038991A3 (fr) 2006-08-03

Family

ID=36142947

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/029135 WO2006038991A2 (fr) 2004-08-17 2005-08-16 Systeme, appareil et procede pour predire differents types d'acces a une memoire et pour gerer des predictions associees a une memoire cache

Country Status (4)

Country Link
JP (1) JP5059609B2 (fr)
KR (1) KR100987832B1 (fr)
TW (1) TWI348097B (fr)
WO (1) WO2006038991A2 (fr)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7636813B2 (en) * 2006-05-22 2009-12-22 International Business Machines Corporation Systems and methods for providing remote pre-fetch buffers
JP6252348B2 (ja) * 2014-05-14 2017-12-27 富士通株式会社 演算処理装置および演算処理装置の制御方法
US9817764B2 (en) 2014-12-14 2017-11-14 Via Alliance Semiconductor Co., Ltd Multiple data prefetchers that defer to one another based on prefetch effectiveness by memory access type
US10387318B2 (en) 2014-12-14 2019-08-20 Via Alliance Semiconductor Co., Ltd Prefetching with level of aggressiveness based on effectiveness by memory access type
JP2017072929A (ja) 2015-10-06 2017-04-13 富士通株式会社 データ管理プログラム、データ管理装置、およびデータ管理方法
US10509726B2 (en) * 2015-12-20 2019-12-17 Intel Corporation Instructions and logic for load-indices-and-prefetch-scatters operations
US20170177349A1 (en) * 2015-12-21 2017-06-22 Intel Corporation Instructions and Logic for Load-Indices-and-Prefetch-Gathers Operations
KR102696971B1 (ko) * 2016-09-06 2024-08-21 삼성전자주식회사 불휘발성 메모리 장치를 포함하는 스토리지 장치 및 불휘발성 메모리 장치의 액세스 방법
US10579531B2 (en) * 2017-08-30 2020-03-03 Oracle International Corporation Multi-line data prefetching using dynamic prefetch depth
US11281589B2 (en) * 2018-08-30 2022-03-22 Micron Technology, Inc. Asynchronous forward caching memory systems and methods
KR102142498B1 (ko) * 2018-10-05 2020-08-10 성균관대학교산학협력단 Gpu 커널 정적 분석을 통해 gpu 프리패치를 수행하기 위한 gpu 메모리 제어장치 및 제어방법
KR102238383B1 (ko) * 2019-10-30 2021-04-09 주식회사 엠투아이코퍼레이션 통신 최적화기능이 내장된 hmi
KR20210077923A (ko) * 2019-12-18 2021-06-28 에스케이하이닉스 주식회사 전력사용량을 관리하기 위해 인공지능을 사용하는 데이터 처리 시스템

Citations (3)

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Publication number Priority date Publication date Assignee Title
US5561782A (en) * 1994-06-30 1996-10-01 Intel Corporation Pipelined cache system having low effective latency for nonsequential accesses
US5623608A (en) * 1994-11-14 1997-04-22 International Business Machines Corporation Method and apparatus for adaptive circular predictive buffer management
US6789171B2 (en) * 2002-05-31 2004-09-07 Veritas Operating Corporation Computer system implementing a multi-threaded stride prediction read ahead algorithm

Family Cites Families (3)

* Cited by examiner, † Cited by third party
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JPH06103169A (ja) * 1992-09-18 1994-04-15 Nec Corp 中央演算処理装置のリードデータプリフェッチ機構
US5426764A (en) * 1993-08-24 1995-06-20 Ryan; Charles P. Cache miss prediction apparatus with priority encoder for multiple prediction matches and method therefor
JP3741945B2 (ja) * 1999-09-30 2006-02-01 富士通株式会社 命令フェッチ制御装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5561782A (en) * 1994-06-30 1996-10-01 Intel Corporation Pipelined cache system having low effective latency for nonsequential accesses
US5623608A (en) * 1994-11-14 1997-04-22 International Business Machines Corporation Method and apparatus for adaptive circular predictive buffer management
US6789171B2 (en) * 2002-05-31 2004-09-07 Veritas Operating Corporation Computer system implementing a multi-threaded stride prediction read ahead algorithm

Also Published As

Publication number Publication date
TW200619937A (en) 2006-06-16
KR20070050443A (ko) 2007-05-15
JP2008510258A (ja) 2008-04-03
KR100987832B1 (ko) 2010-10-13
WO2006038991A2 (fr) 2006-04-13
TWI348097B (en) 2011-09-01
JP5059609B2 (ja) 2012-10-24

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