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WO2006030409A2 - Systeme, circuit et procede permettant d'utiliser une memoire numerique associee a un dispositif hote pour des donnees reçues - Google Patents

Systeme, circuit et procede permettant d'utiliser une memoire numerique associee a un dispositif hote pour des donnees reçues Download PDF

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Publication number
WO2006030409A2
WO2006030409A2 PCT/IL2004/001082 IL2004001082W WO2006030409A2 WO 2006030409 A2 WO2006030409 A2 WO 2006030409A2 IL 2004001082 W IL2004001082 W IL 2004001082W WO 2006030409 A2 WO2006030409 A2 WO 2006030409A2
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WO
WIPO (PCT)
Prior art keywords
data
host device
digital memory
memory
buffer
Prior art date
Application number
PCT/IL2004/001082
Other languages
English (en)
Other versions
WO2006030409A3 (fr
Inventor
Alon Ironi
Dror Meiri
Original Assignee
Siano Mobile Silicon Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siano Mobile Silicon Ltd. filed Critical Siano Mobile Silicon Ltd.
Publication of WO2006030409A2 publication Critical patent/WO2006030409A2/fr
Priority to GB0704409A priority Critical patent/GB2432243A/en
Priority to US11/662,548 priority patent/US20070296873A1/en
Priority to IL181871A priority patent/IL181871A0/en
Publication of WO2006030409A3 publication Critical patent/WO2006030409A3/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41—Structure of client; Structure of client peripherals
    • H04N21/414—Specialised client platforms, e.g. receiver in car or embedded in a mobile appliance
    • H04N21/41407—Specialised client platforms, e.g. receiver in car or embedded in a mobile appliance embedded in a portable device, e.g. video client on a mobile phone, PDA, laptop
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41—Structure of client; Structure of client peripherals
    • H04N21/414—Specialised client platforms, e.g. receiver in car or embedded in a mobile appliance
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/443—OS processes, e.g. booting an STB, implementing a Java virtual machine in an STB or power management in an STB
    • H04N21/4435—Memory management
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/443—OS processes, e.g. booting an STB, implementing a Java virtual machine in an STB or power management in an STB
    • H04N21/4436—Power management, e.g. shutting down unused components of the receiver
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41—Structure of client; Structure of client peripherals
    • H04N21/426—Internal components of the client ; Characteristics thereof

Definitions

  • the present invention relates generally to the field of communications.
  • the present invention relates to a system, circuit and method for storing, retrieving and otherwise utilizing received data in digital memory associated with a computing and/or communication device to which a receiver may be connected.
  • handheld computing, entertainment and communication devices Over the past decade, the proliferation of handheld computing, entertainment and communication devices has been enormous. Many handheld devices include digital telecommunication and/or multimedia systems and require audio, video and graphics capabilities, and some even include television reception capabilities and wireless modem capabilities. Cellular phones, Palm- PCs, portable media players, digital video cameras and digital still cameras are examples of such systems. Although each new generation of handheld devices tends to introduce new and innovative functionality, these devices are still required to be relatively small in size and economic considerations require their manufacturing cost to be as low as possible. Furthermore, since handheld devices must usually be battery- operated, there is also at times a strict requirement for the device to consume a small amount of power as possible. Low power consumption may allow for a relatively long operation time without having to replace or re-charge the batteries.
  • Fig. 1 shows a block diagram of an exemplary handheld device, the core of which device is a processor or microcontroller (host CPU) that may control the operation of the device and may execute many of the device's system tasks. It is interfaced with the applicative entities which may compose the device's system and various sub-systems. Among those entities there may be user interfaces, memories, multi-media encoders and decoders, graphic processors, mobile TV receivers, modems, other application specific processors, and a battery. Sometimes the host processor may also be responsible for performing application specific functions. For example, modern-day handheld devices are typically based on a strong host CPU with MPEG decoding and graphics control capabilities. Not all the blocks shown in Fig. 1 are mandatory for each type of device, however, a typical handheld device may be composed of some or all of the entities shown in the block diagram of Fig. 1.
  • host CPU microcontroller
  • User interface entities may include a color graphic display, an image sensor, a keypad, a speakerphone, a microphone or any other user input device known today or to be devised in the future.
  • Modems can be cellular modems, wireless-LAN, Bluetooth, Mobile Digital Television (“MDTV”) demodulators or any other modems used today or to be devised in the future.
  • Digital memories used with a handheld device may include DRAM, FLASH, EPROM, SIM card and hard disk.
  • the DRAM is the most commonly used memory of host CPUs today, and will be abbreviated here as "HDRAM” (Host DRAM) for convenience.
  • the HDRAM is almost always a very large memory. In fact, modern handheld systems have HDRAM of size 256Mbits to 1024Mbits.
  • engines which engines engage in extensive data manipulation. These operations or data manipulation may vary with the application and functionality of the engine in terms of processing method, data rates, signal bandwidth, data precision and more.
  • one of the common properties for the majority of those engines is that they are all required to store data and/or parameters as well as to buffer or manipulate it through processing and/or changing its order, insert or extract information from the data structure. Hence, they can all be considered RAM users or consumers.
  • the present invention is a system, circuit and method of utilizing digital memory associated with a computing and/or communication device (e.g. mobile or handheld phone or video based communication and presentation device).
  • a sub-system functionally associated with the computing and/or communication device e.g. a data receiving circuit, sub-system or module
  • the sub-system may include a receiver and may store data received from outside the device, either in a processed or in an unprocessed state, where the term processed may include functions like demodulated, decoded, error detected and/or error corrected.
  • preprocessed data stored by the sub-system on the digital memory may be read back by the sub-system and processed.
  • Processed data stored by the sub-system on the digital memory may be read or transmitted to other sub-systems functionally associated with the device. Once unprocessed data is read back to the sub-system and processed, it may either be transferred back to the digital memory functionally associated with the device or to another sub-system functionally associated with the device.
  • the sub-system receiving data from outside the device may include a controller, which controller may communicate with a controller or a processor on the device in order to facilitate the transfer of data to and from the digital memory functionally associated with the device.
  • the sub-system may also include a digital memory buffer, which buffer may store data received from outside the device.
  • the sub- system controller may facilitate data transfers between the sub-system's digital memory buffer and the digital memory associated with the device.
  • the sub-system controller may facilitate the transfer of data stored by the sub-system in the digital memory functionally associated with the device back to the sub-system.
  • the sub-system controller may facilitate the transfer of received data to the digital memory functionally associated with the device prior to the data being processed or decoded.
  • the sub-system controller may facilitate the transfer of the unprocessed or un-decoded data back to the sub-subsystem for processing or decoding.
  • the controller may facilitate the transfer of processed or decoded data either to the digital memory functionally associated with the device or to another sub-system functionally associated with the device.
  • the digital memory functionally associated with the device may be a Random Access Memory ("RAM"), either W 'S" or "D" type, connected to a controller of the device.
  • RAM Random Access Memory
  • the device controller may either be a multifunction or general purpose microprocessor, or the controller may be a dedicated memory access controller (e.g. Dynamic Memory Access unit "DMA").
  • DMA Dynamic Memory Access unit
  • the sub-system may include a receiver or a modem, which is wireless, wired, optical, or of any other type known today or to be developed in the future.
  • the sub-system may also include a decoder (e.g. turbo decoder) and/or an encoder.
  • the sub-system and/or the decoder may include error detection and/or error correction functionality and logic circuits.
  • the sub-system may also include data security (e.g. encryption and decryption) functionality and logical circuits.
  • Fig. 1 is a block diagram depicting various components and sub-systems which may be functionally associated with a mobile or handheld communication and/or computation device;
  • Fig. 2 is a block diagram of an exemplary arrangement of components and functional blocks of a mobile phone including a digital TV receiver according to some embodiments of the present invention
  • Fig. 3 is a block diagram of an exemplary arrangement of components and functional blocks of a media player including a digital TV receiver according to some embodiments of the present invention
  • Fig. 4 is block diagram of a data receiving circuit, including a host memory access controller or unit, according to some embodiments of the present invention.
  • Fig. 5 is a block diagram of a data receiving circuit interconnected with a digital memory associated with a host device, according to some embodiments of the present invention.
  • Embodiments of the present invention may include apparatuses for performing the operations herein.
  • This apparatus may be specially constructed for the desired purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer.
  • a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, magnetic- optical disks, read-only memories (ROMs), random access memories (RAMs) electrically programmable read-only memories (EPROMs), electrically erasable and programmable read only memories (EEPROMs), magnetic or optical cards, or any other type of media suitable for storing electronic instructions, and capable of being coupled to a computer system bus.
  • the present invention is a system, circuit and method of utilizing digital memory associated with a computing and/or communication device (e.g. mobile or handheld phone or video based communication and presentation device).
  • a sub-system functionally associated with the computing and/or communication device e.g. a data receiving circuit, sub-system or module
  • the sub-system may include a receiver and may store data received from outside the device, either in a processed or in an unprocessed state, where the term processed may include functions like demodulated, decoded, error detected and/or error corrected.
  • preprocessed data stored by the sub-system on the digital memory may be read back by the sub-system and processed.
  • Processed data stored by the sub-system on the digital memory may be read or transmitted to other sub-systems functionally associated with the device. Once unprocessed data is read back to the sub-system and processed, it may either be transferred back to the digital memory functionally associated with the device or to another sub-system functionally associated with the device.
  • the sub-system receiving data from outside the device may include a controller, which controller may communicate with a controller or a processor on the device in order to facilitate the transfer of data to and from the digital memory functionally associated with the device.
  • the sub-system may also include a digital memory buffer, which buffer may store data received from outside the device.
  • the sub ⁇ system controller may facilitate data transfers between the sub-system's digital memory buffer and the digital memory associated with the device.
  • the sub-system controller may facilitate the transfer of data stored by the sub-system in the digital memory functionally associated with the device back to the sub-system.
  • the sub-system controller may facilitate the transfer of received data to the digital memory functionally associated with the device prior to the data being processed or decoded.
  • the sub-system controller may facilitate the transfer of the unprocessed or un-decoded data back to the sub-subsystem for processing or decoding.
  • the controller may facilitate the transfer of processed or decoded data either to the digital memory functionally associated with the device or to another sub-system functionally associated with the device.
  • the digital memory functionally associated with the device may be a Random Access Memory ("RAM"), either "S” or “D” type, connected to a controller of the device.
  • the device controller may either be a multifunction or general purpose microprocessor, or the controller may be a dedicated memory access controller (e.g. Dynamic Memory Access unit "DMA").
  • the sub-system may include a receiver or a modem, which is wireless, wired, optical, or of any other type known today or to be developed in the future.
  • the sub-system may also include a decoder (e.g. turbo decoder) and/or an encoder.
  • the sub-system and/or the decoder may include error detection and/or error correction functionality and logic circuits.
  • the sub-system may also include data security (e.g. encryption and decryption) functionality and logical circuits.
  • video signal may include a video data stream or data, or any other media related data stream or data.
  • video signal may also include an analog electromagnetic signal which has been modulated with video, sound and/or image related information.
  • FIGs. 2 and 3 Block diagrams of implementations of a MDTV receiver/demodulators within a (1) mobile phone 1000 A, and a (2) Portable Media Player (“PMP") system 100OB, are shown in Figs. 2 and 3, respectively.
  • a cellular handset IOOOA may also include a second RF receiver 100 with a second RF chipset 110 and a second demodulator 120.
  • RF radio frequency
  • the second receiver 100 may be designed to receive data also containing video information, for example a data signal compliant with one or more of the standards associated with MDTV.
  • the Portable Media Player IOOOB shown in Fig. 3 does not include a first or conventional receiver as shown in Fig. 2.
  • both the cellular handset IOOOA and the PMP IOOOB according to the present invention may include digital memory 410 functionally associated or substantially integrally associated with a processor 400 or some other digital controller capable of managing access to a digital memory.
  • Integration of a MDTV receiver in a handheld device or terminal may result in additional power consumption.
  • the budget for additional power consumption due to the additional MDTV receiver may be limited by specification, sometimes to as little as 10% of the expected power consumption of a standard Digital TV receiver (composed of RF tuner and a baseband demodulator).
  • the DVB-H (H stands for handheld device) standard, may be used by a handheld demodulators, usually for mobile TV reception and may significantly reduce the average power consumption of a DVB receiver by introducing a scheme based on time division multiplexing (TDM).
  • TDM time division multiplexing
  • This scheme is called Time-Slicing.
  • the concept of time-slicing is to send data in bursts using a significantly higher bit rate compared to the bit rate required if the data was transmitted continuously. Within a burst, the time to the beginning of the next burst (delta-t) may be indicated. This may enable a demodulator to stay active for only a fraction of a second, each second data is being transmitted, while receiving bursts of a requested service.
  • the burst bit rate may be about 10 times the constant bit rate of a delivered service. In case of a 350 Kbps streaming services, this indicates a requirement of 4 Mbps bit rate for the bursts.
  • US Patent Application Publication No. 20030152107 teaches: "In a digital broadband broadcasting system, in which information is transmitted and received periodically in bursts to reduce receiver power consumption, time-slice information is provided from the transmitter to the receiver.
  • the time-slice information can include information from which the receiver can determine when a subsequent transmission burst will be transmitted.
  • the time-slice information can include a burst duration, an amount of time between original bursts, the time between an original burst and a copy of the burst, and numbering of original bursts. This type of time-slice information can be placed into packet headers, such as one or more bytes reserved, but not used, for media access control addressing. " (Publication Abstract).
  • a receiver may take advantage of the time-slicing mechanism and may shut down as many functions as possible - essentially the entire receiver, and for the longest possible time - essentially the entire "silence" time.
  • Data received from a burst of data may, according to the DVB-H standard, may be used to produce a data structure called the MPE-FEC (Multi Protocol Encapsulation - Forward Error Correction) table.
  • MPE-FEC Multi Protocol Encapsulation - Forward Error Correction
  • the size of this table may be about 2Mbits, or up to 2.25Mbits if it may support extended FEC capabilities, i.e. erasures handling.
  • a demodulator which does not require having MPE-FEC capabilities may need a table of up to 1.5Mbits.
  • an MDTV demodulator may be required to utilize at least 1.5 Mbits of memory, and also to access the memory and process data in the memory during time slots when the demodulator may otherwise be inactive.
  • an MDTV may include embedded dynamic random-access memory ("DRAM"). Embedding logic/processing functions on the same semiconductor die as digital memory is well known.
  • an MDTV demodulator may have its own digital memory, on a different die, but both packaged together.
  • the MDTV demodulator may be connected to external and dedicated digital memory.
  • the addition of 1.5 to 2.5 Mbits of digital memory to the die of a receiver or to the package within which the deceiver die resides may lead to substantial size, fabrication complexity, and cost increases for the receiver.
  • a 2 Mbit memory cell array including its controller, fabricated using 1.3 micrometer technology, may require more than 6.2 mm of space on a die.
  • data received by a receiver 100 may be stored outside the receiver and in a digital memory 410 which is functionally associated with a general purpose host processor 400 or functionally associated with a dedicated memory controller (not shown) on a host device to which the receiver is connected.
  • Received data may be stored on the digital memory 410 in accordance with a service protocol between the receiver 100 and the processor 400, by which protocol the receiver 100 may request from the processor 400 accesses to a portion of the digital memory 410. Storing received data on a digital memory outside the receiver die and/or package, and avoiding the need for an integrated memory buffer of approximately 2 Mbits, may substantial reduce the size, fabrication complexity, and cost of a receiver according to some embodiments of the present invention.
  • An exemplary service protocol may be unified for all types of communications (except for configuration, which is done through the I2C-like port).
  • Any data, control or payload, provided by the engine to the host may be structured as a packet with a packet header of 3 bytes. The following is the organization of the bits of a 3 byte, 24-bit, packet header. Note that bit 23 is the first one sent, bit 0 is the last one. • Bits 23 - 22 - Message type o 00 - Service write request o 01 - Service read request o 10 - Service write response o 11 - Service read response
  • Bits 15-0 packet size in Bytes (excluding the three header bytes)
  • Field 1 Address of the first data byte in the HDRAM
  • Field 2 Size (in bytes) of the data, starting at the address given in field 1.
  • Field 3 The data payload which is requested to be written to the continuous address space starting in the address given in field 1 and ending after "field 2" bytes.
  • the payload has only two fields: Field 1 : Address of the first data byte in the HDRAM Field 2: Size (in bytes) of the data, starting at the address given in field 1.
  • Field 1 Address of the first data byte in the HDRAM.
  • Field 2 Size (in bytes) of the data, starting at the address given in field 1.
  • Field3 The data payload which is requested to be read from the continuous address space starting in the address given in field 1 and ending after "field 2" bytes. In case the service is of type write response, it has the pure meaning of acknowledge, hence all the rest of the header bits are ignored and no payload data is sent from the HDRAM to the engine.
  • Continuous payload packet - is a packet whose payload data is continuous. This means that the address space into which the host is expected to write or to read from is continuous for the entire packet.
  • Sparse payload packet is a packet whose payload data is not continuous, and can contain multiple addresses into which the host is expected to write or to read from during the same packet.
  • Example 1 continuous payload packet
  • the engine sends to the host a write request (i.e. he wishes to write data to the HDRAM) for purpose 1.
  • the data is continuous (one chunk of data) and it is the middle packet of the current procedure.
  • the data is of size of 64Kbytes, and the first data byte is written to address OxA in the HDRAM.
  • Example 2 sparse payload packet 0
  • the engine sends to the host a read request (i.e. he wishes to read data from the HDRAM) for purpose 3.
  • the data is sparse (more than one chunk of data) and it is the first packet of the current procedure.
  • the data is of size of 2Bytes, and is read from addresses OxOOF2 and OxFFOO.
  • data received by a receiver such as the MDTV receivers in Figs. 2 and 3, may be temporarily and/or partially stored in a digital memory 410 associated with a host processor 400 during periods when the receiver is at least partially shut down.
  • a receiver may be able to shut down, at least partially, by first transferring some or all of the data received during a previous duty cycle to a digital memory 410 functionally associated with a host processor. Included in the data which may be transferred to or from the receiver to the digital memory is: (1) received data which has not yet been demodulated; (2) data which has not yet been error checked or error corrected; (3) any other data which requires additional processing within the receiver before being usable to a client application, (4) data associated with the physical operating parameters of the receiver (e.g.
  • data requiring further processing may be retrieved back into the receiver 100, once the receiver is turn back on.
  • data stored on the digital memory associated with the host, the host processor, or some other controller associated with the host may be data-rate equalized in accordance with data rate requirements of a given application, when the processor or controller is providing the data to the given application.
  • FIG. 4 there is shown a block diagram of an exemplary receiver 100, according to some embodiments of the present invention, including a Signal Acquisition and Preprocessing Module 110 (e.g. filters, amplifiers, analog to digital converters, etc.).
  • a Data Demodulation & Error Detection/Correction Processing Module 120 e.g. demodulator with error detection/correction logic
  • a Memory Access Control Unit 130 may facilitate the transfer of all or a portion of the received that to a digital memory 410 functionally associated with a processor 400, or memory controller, of a host device (also see Fig. 5).
  • the Memory Access Control Unit 130 may communicate with the host processor 400, or host controller, using a service protocol, through a Host Memory Access Unit 150 and a Host Data Bus Interface 160.
  • the receiver 100 may not be integrally connected to the host, but may be a separate and removable device which may be connected to the host through one of the host's external or peripheral interface ports or connection points, such as a Universal Serial Bus (“USB”), or through any other external/peripheral communication ports known today or to be devised in the future.
  • the receiver's Host Data Bus Interface 160 may be a communication module such as a USB communication module or circuit adapted to interface and communicate with the host device through the host's external communication port.
  • the Memory Access Control Unit 130 may facilitate retrieval back into the receiver 100 of received data stored on the digital memory 410 associated with a host processor 400. Once retrieved into the receiver, data which has not been sufficiently demodulated or otherwise processed, may be further demodulate or processed by the Data Demodulation & Error Detection/Correction Processing Module 120.
  • the writing and reading of data to and from the digital memory facilitate the rearrangement of data. For example, righting received data to the digital memory in a first order and reading it back in a second order may facilitate the interleaving or de- interleaving of the data.
  • Various data manipulations are possible using read and write operations to the digital memory associated with the horst device and/or host processor. Although data interleaving and de-interleaving were the two examples of data manipulation given as part of this application, any data manipulation known today or to be devised in the future may be applicable to the present invention.
  • data exchange between the receiver (and/or any other data engine) and the digital memory may utilize data bufferization in order to accommodate for delays imposed by processing and responses times in the processor or controller with which the digital memory is associated.
  • THR Home Response Time
  • a common practice value for THR is 1 ms.
  • a common practice values for RHDD are 8Mbps, 20Mbps and over 160 Mbps for USB 1.1, SPI and fast parallel interface of 16 bits width, respectively.
  • RID Incoming Data Rate
  • Typical values depend on the specific application of the receiver, as example the MDTV demodulator's data rate during a burst might be up to 32Mbps.
  • REP Receiveiver Processing Rate
  • B size in bytes of the internal buffer at the receiver.
  • the receiver may require an internal buffer to compensate for the latency in the host response. Assuming the policy is for the receiver to request host (memory) service when the buffer is half full (B/2), and deliver half a buffer each time, the following relations shall may exist: For HDRAM utilized as a data buffer: THR +B/(2 RHDD) ⁇ B/(2 RID)
  • the buffer may be sufficiently large such that once the receiver requests a service, there is enough time for the host to respond to the service request, and move data from the buffer to the HDRAM before the buffer is overflows because of fresh incoming data.
  • the buffer is sufficiently large such that once the receiver requests a service. There is enough time for the host to respond to the service request, send data from the HDRAM to the buffer for processing, move processed data back from the buffer to the HDRAM and all of this before the processing unit overflows the buffer with a new processed data.
  • the minimum buffer size is given by:

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Abstract

L'invention concerne un système, un circuit et un procédé permettant d'utiliser une mémoire numérique associée à un dispositif informatique et/ou de communication (par exemple, un téléphone mobile ou portable ou un dispositif de communication et présentation vidéo). Selon certains modes de réalisation, un récepteur ou un sous-système de récepteur fonctionnellement associés au dispositif informatique et/ou de communication (par exemple, un circuit récepteur de données, un sous-système ou un module) peuvent stocker des données sur une mémoire numérique également fonctionnellement associée au dispositif. Selon certains modes de réalisation, le sous-système peut comprendre un démodulateur de récepteur et peut stocker des données reçues de l'extérieur du dispositif, soit dans un état traité, soit dans un état non traité, dans lesquels le terme traité peut comporter des fonctions tels que démodulé, décodé, erreur détectée et/ou erreur corrigée. Selon certains modes de réalisation, les données prétraitées stockées par le sous-système sur la mémoire numérique peuvent être relues par le sous-système et traitées.
PCT/IL2004/001082 2004-09-16 2004-11-25 Systeme, circuit et procede permettant d'utiliser une memoire numerique associee a un dispositif hote pour des donnees reçues WO2006030409A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
GB0704409A GB2432243A (en) 2004-09-16 2007-03-07 A system circuit and method for utilizing digital memory associated with a host device for received data
US11/662,548 US20070296873A1 (en) 2004-09-16 2007-03-12 System Circuit Method for Utilizing Digital Memory Associated with a Host Device for Received Data
IL181871A IL181871A0 (en) 2004-09-16 2007-03-12 A system, circuit and method for utilizing digital memory associated with a host device for received data

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US61020104P 2004-09-16 2004-09-16
US60/610,201 2004-09-16

Publications (2)

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WO2006030409A2 true WO2006030409A2 (fr) 2006-03-23
WO2006030409A3 WO2006030409A3 (fr) 2007-05-18

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US (1) US20070296873A1 (fr)
GB (1) GB2432243A (fr)
WO (1) WO2006030409A2 (fr)

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Also Published As

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US20070296873A1 (en) 2007-12-27
GB2432243A (en) 2007-05-16
GB0704409D0 (en) 2007-04-18
GB2432243A8 (en) 2007-05-18
WO2006030409A3 (fr) 2007-05-18

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