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WO2006028673A1 - Gravure avec controle d'uniformite - Google Patents

Gravure avec controle d'uniformite Download PDF

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Publication number
WO2006028673A1
WO2006028673A1 PCT/US2005/029308 US2005029308W WO2006028673A1 WO 2006028673 A1 WO2006028673 A1 WO 2006028673A1 US 2005029308 W US2005029308 W US 2005029308W WO 2006028673 A1 WO2006028673 A1 WO 2006028673A1
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WO
WIPO (PCT)
Prior art keywords
wafer
etch
outer edge
around
recited
Prior art date
Application number
PCT/US2005/029308
Other languages
English (en)
Inventor
Seiji Kawaguchi
Kenji Takeshita
Original Assignee
Lam Research Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lam Research Corporation filed Critical Lam Research Corporation
Priority to JP2007529970A priority Critical patent/JP2008512853A/ja
Priority to KR1020077007645A priority patent/KR101155843B1/ko
Publication of WO2006028673A1 publication Critical patent/WO2006028673A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

Definitions

  • the present invention relates to the fabrication of semiconductor-based devices. More particularly, the present invention relates to improved techniques for fabricating semiconductor-based devices with an etched layer.
  • features of the semiconductor device are defined in the wafer using well-known patterning and etching processes. In these processes, a photoresist (PR) material is deposited on the wafer and then is exposed to light filtered by a reticle.
  • PR photoresist
  • the reticle is generally a glass plate that is patterned with exemplary feature geometries that block light from propagating through the reticle.
  • the light After passing through the reticle, the light contacts the surface of the photoresist material.
  • the light changes the chemical composition of the photoresist material such that a developer can remove a portion of the photoresist material.
  • the exposed regions are removed, and in the case of negative photoresist materials, the unexposed regions are removed.
  • the wafer is etched to remove the underlying material from the areas that are no longer protected by the photoresist material, and thereby define the desired features in the wafer.
  • a method of forming semiconductor devices on a wafer is provided.
  • An etch layer is formed over a wafer.
  • a photoresist mask is formed over the etch layer. The photoresist mask is removed only around an outer edge of the wafer to expose the etch layer around the outer edge of the wafer.
  • a deposition gas is provided comprising carbon and hydrogen containing species.
  • a plasma is formed from the deposition gas.
  • a polymer layer is deposited on the exposed etch layer around the outer edge of the wafer, wherein the polymer is formed from the plasma from the deposition gas.
  • the etch layer is etched through i the photoresist mask, while consuming the photoresist mask and the polymer deposited on the exposed etch layer around the outer edge of the wafer.
  • FIG. 1 is a flow chart of a process used in an embodiment of the invention.
  • FIG. 's 2A-D are schematic side views of a wafer processed according to the process of FIG. 1.
  • FIG. 3 is a schematic view of a process chamber that may be used in an embodiment of the invention.
  • FIG.'s 4A-B are schematic views of a computer system that may be used as a controller.
  • FIG. 5 is a top view of the wafer with the photoresist mask removed around the outer edge of the wafer to expose the etch layer.
  • FIG. 1 is a high level flow chart of a process used in an embodiment of the invention. An etch layer is formed over a wafer (step 104). FIG.
  • FIG. 2 A is a cross-sectional view of a wafer 204 at an outer edge 206 of the wafer 204.
  • An etch layer 208 is formed over the wafer 204 (step 104).
  • the etch layer may be a conductive layer or a dielectric layer.
  • a photoresist mask 212 is formed over the etch layer (208) (step 108).
  • an antireflective coating (ARC) 210 such as BARC, is placed over the etch layer 208 before the photoresist mask 212 is formed, so that the ARC 214 is between the etch layer 208 and the photoresist mask 212.
  • Other layers may be disposed between the etch layer 208 and the photoresist mask 212.
  • the photoresist mask around the other edge of the wafer is removed (step 112), as shown in FIG. 2B to expose the etch layer around the outer edge of the wafer.
  • all organic material above the etch layer 216 around the outer edge of the wafer is removed, so that the organic BARC 210 is also removed.
  • FIG. 5 is a top view of the wafer 204 with the photoresist mask 212 removed around the outer edge of the wafer to expose the etch layer 208.
  • 2-3 mm of organic material such as photoresist and BARC are removed from around the outer edge of the wafer to eliminate a source of particles from peeling.
  • FIG. 3 is a schematic view of a plasma processing chamber 300 that may be used for depositing the layer, etching, and stripping that may be used in this example.
  • the plasma processing chamber 300 comprises confinement rings 302, an upper electrode 304, a lower electrode 308, a gas source 310, and an exhaust pump 320.
  • the wafer 204 is positioned upon the lower electrode 308.
  • the lower electrode 308 incorporates a suitable substrate chucking mechanism (e.g., electrostatic, mechanical clamping, or the like) for holding the wafer 204.
  • the reactor top 328 incorporates the upper electrode 304 disposed immediately opposite the lower electrode 308.
  • the upper electrode 304, lower electrode 308, and confinement rings 302 define the confined plasma volume. Gas is supplied to the confined plasma volume by the gas source 310 and is exhausted from the confined plasma volume through the confinement rings 302 and an exhaust port by the exhaust pump 320.
  • a first RF source 344 is electrically connected to the upper electrode 304.
  • a second RF source 348 is electrically connected to the lower electrode 308. Chamber walls 352 surround the confinement rings 302, the upper electrode 304, and the lower electrode 308. Both the first RF source 344 and the second RF source 348 may comprise a 27 MHz power source and a 2 MHz power source. Different combinations of connecting RF power to the electrode are possible.
  • FIG.'S 4A and 4B illustrate a computer system 800, which is suitable for implementing a controller 335 used in embodiments of the present invention.
  • FIG. 4 A shows one possible physical form of the computer system.
  • Computer system 800 includes a monitor 802, a display 804, a housing 806, a disk drive 808, a keyboard 810, and a mouse 812.
  • Disk 814 is a computer-readable medium used to transfer data to and from computer system 800.
  • FIG. 4B is an example of a block diagram for computer system 800. Attached to system bus 820 is a wide variety of subsystems. Processor(s) 822 (also referred to as central processing units, or CPUs) are coupled to storage devices, including memory 824. Memory 824 includes random access memory (RAM) and read-only memory (ROM).
  • RAM random access memory
  • ROM read-only memory
  • ROM acts to transfer data and instructions uni-directionally to the CPU and RAM is used typically to transfer data and instructions in a bi-directional manner. Both of these types of memories may include any suitable of the computer-readable media described below.
  • a fixed disk 826 is also coupled bi-directionally to CPU 822; it provides additional data storage capacity and may also include any of the computer-readable media described below.
  • Fixed disk 826 may be used to store programs, data, and the like and is typically a secondary storage medium (such as a hard disk) that is slower than primary storage. It will be appreciated that the information retained within fixed disk 826 may, in appropriate cases, be incorporated in standard fashion as virtual memory in memory 824.
  • Removable disk 814 may take the form of any of the computer-readable media described below.
  • CPU 822 is also coupled to a variety of input/output devices, such as display 804, keyboard 810, mouse 812 and speakers 830.
  • an input/output device may be any of: video displays, track balls, mice, keyboards, microphones, touch-sensitive displays, transducer card readers, magnetic or paper tape readers, tablets, styluses, voice or handwriting recognizers, biometrics readers, or other computers.
  • CPU 822 optionally may be coupled to another computer or telecommunications network using network interface 840. With such a network interface, it is contemplated that the CPU might receive information from the network, or might output information to the network in the course of performing the above-described method steps.
  • embodiments of the present invention may execute solely upon CPU 822 or may execute over a network such as the Internet in conjunction with a remote CPU that shares a portion of the processing.
  • embodiments of the present invention further relate to computer storage products with a computer-readable medium that have computer code thereon for performing various computer-implemented operations.
  • the media and computer code may be those specially designed and constructed for the purposes of the present invention, or they may be of the kind well known and available to those having skill in the computer software arts.
  • Examples of computer-readable media include, but are not limited to: flash memory cards, magnetic media such as hard disks, floppy disks, and magnetic tape; optical media such as CD-ROMs and holographic devices; magneto-optical media such as floptical disks; and hardware devices that are specially configured to store and execute program code, such as application-specific integrated circuits (ASICs), programmable logic devices (PLDs) and ROM and RAM devices.
  • Examples of computer code include machine code, such as produced by a compiler, and files containing higher level code that are executed by a computer using an interpreter.
  • Computer readable media may also be computer code transmitted by a computer data signal embodied in a carrier wave and representing a sequence of instructions that are executable by a processor.
  • a deposition gas is provided into the etch chamber (step 116).
  • the deposition gas comprises one or more (at least one) species that allows the formation of polymer. This would require carbon and hydrogen containing species. In addition, it is desirable that the deposition gas has a fluorine containing species.
  • a plasma is formed from the deposition gas (step 120). Power from the RF power sources is used to energize the deposition gas to form a plasma. A polymer layer is deposited on the exposed etch layer around the outer edge of the wafer, where the polymer is formed from the plasma from the deposition gas (step 124). FIG.
  • FIG. 2C is a cross-sectional view of part of the wafer 204 after the polymer 220 has been deposited on the exposed etch layer around the outer edge of the wafer 216.
  • the deposited polymer 220 is only shown as being deposited on the etch on the outer edge of the wafer 216, some deposition processes may deposit the polymer over the entire wafer surface. It is desirable to have as much control as possible to best limit the deposition of the polymer to the outer edge of the wafer 216.
  • the dielectric layer is etched (step 128).
  • FIG. 2D is a cross-sectional view of the wafer 204 after features 224 have been etched into the dielectric layer 208.
  • the presence of the polymer over the exposed dielectric layer on the outer edge of the wafer provides a more uniform etch across the wafer, with etch depth uniformity and profile variation uniformity. It is believed that without the deposited layer, the etch layer is directly exposed to plasma, which causes a greater consumption of etching ion and radical species during the etch process than consumption in other areas of the wafer, thus causing the etch rate nearer to the edge of the wafer to be slower than the etch rate closer to the middle of the wafer. In addition, the feature profile near the edge of the wafer tends to bow due to lack of polymer source for side protection supplied from the exposed areas at the outer edge of the wafer.
  • Providing the protective polymer layer over the exposed etch layer at the outer edge of the wafer both protects the etch layer at the outer edge to reduce the consumption of etching ions and radical species and provides a polymer source at the outer edge to provide a more uniform etch and reduce bowing.
  • providing a deposition gas with carbon, hydrogen, and fluorine species formed hydro-fluorocarboned polymer. It has been found that such polymers have provided the best results.
  • an etch layers of SiC, then SiCOH, and then TEOS are deposited on a silicon wafer (step 104).
  • An ARC layer of resist like organic material is formed over the etch layer.
  • a photoresist mask is formed on the ARC layer, which is over the etch layer (step 108).
  • the photoresist mask is made of preferably 248 nm photoresist, such as KrF, is used. In other embodiments, other photoresist materials such as i-line, and 193 nm and shorter wavelength photoresists, such as ArF, may be used.
  • Photoresist within 3 mm from the edge of the wafer is removed.
  • a wet stripping using a wet strip resist developer is used to remove the photoresist around the wafer edge (step 112).
  • the wafer is placed in an etch chamber (step 114), which in this example is a dual frequency etching reactor.
  • a deposition gas of 350 seem Ar, 3.5 seem O 2 , and 50 seem CH 3 F is provided into the etch chamber (step 116), where the chamber pressure is maintained at 60 mTorr.
  • a plasma is formed from the deposition gas (step 120).
  • the RP source provides 800 watts at 27 MHz and 200 watts at 2 MHz.
  • the lower electrode temperature is 20° C, and the helium back side pressure in the chuck is kept at 20 Torr.
  • a polymer layer is deposited on the exposed etch layer around the outer edge of the wafer, where the polymer is formed from the plasma from the deposition gas (step 124).
  • the polymer is a hydro- fluorocarboned polymer.
  • the polymer is deposited over the entire wafer surface, including the exposed etch layer around the outer edge of the wafer.
  • the deposition is provided for 8 seconds in this example.
  • the etch layer is then etched through the photoresist mask (step 128).
  • the etch recipe first provides a main etch. Pressure in the main etch is 70 mTorr. 1400 watts are provided at 27 MHz. 1500 watts are provided at 2 MHz. An etch gas flow of 500 seem Ar, 250 seem N 2 , 8 seem C 4 F 8 , 5 seem CH 2 F 2 , and 5 seem O 2 is provided which is converted to a plasma for the main etch. An over etch is then provided.
  • the pressure for the over etch is 70 mTorr. 1400 watts are provided at 27 MHz. 1800 watts are provided at 2 MHz. An etch gas flow of 500 seem Ar, 150 seem N 2 , 7 seem C 4 F 8 , 5 seem CH 2 F 2 , and 100 seem CO is provided which is converted to a plasma for the over etch.
  • the inventive etch which used an 8 second deposition, as described above and a 55 second main etch was compared with control etch with a 67 second main etch, using the same etch process.
  • the inventive etch provided features at the wafer center with etch depths of 659 A and at the wafer edge with an etch depth of 663 A and at 3 mm from the wafer edge with a depth of 672 A.
  • the control etch provided features at the wafer center with etch depths of 608 A and at the wafer edge with an etch depth of 580 A and at 3 mm from the wafer edge with a depth of 555 A.
  • the inventive etch provides an etch feature that is about 12% greater than the control etch, even though the control etch etched for a longer period.
  • the variance between the etch depth at the center versus 3 mm from the edge is less for the inventive etch than for the control etch.
  • comparison of the control etch with the inventive etch found that bowing of the features 3 mm from the wafer edge was reduced by the inventive etch.
  • the flow ratio of oxygen to carbon and hydrogen containing species gases is between and 0:100 and 1:1. Therefore, in some embodiments no oxygen is present in the deposition gas, so that oxygen is not present during the deposition.
  • the flow ratio of oxygen to carbon and hydrogen containing species gases is between 0:100 and 1 :2. It is most preferred that the flow ratio of oxygen to carbon and hydrogen containing species gases is between 0:100 and 1:10.
  • a low Carbon to Hydrogen ratio deposition gas could obtain polymer easily. For example, a 1 : 1 ratio may be obtained using CHF 3 , and a 1 :2 ratio may be obtained using CH 2 F 2 and a 1:3 ratio may be obtained using CH 3 F.
  • Other embodiments may use a 193 nm or small photoresist material.
  • the power supplied by the higher frequency source be between 50 and 3,000 watts.
  • the power supplied by the higher frequency source be between 100 and 2,000 watts. It is most preferable that the power supplied by the higher frequency source be between 500 and 1,000 watts.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Drying Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
  • Physical Vapour Deposition (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne un procédé destiné à la formation de dispositifs semi-conducteurs sur une plaquette. Ce procédé consiste à former une couche à graver sur une plaquette, à former un masque de résine photosensible sur la couche à graver, à retirer un partie du masque de résine photosensible située autour d'un bord externe de la plaquette pour exposer la couche à graver autour du bord externe de la plaquette, à fournir un gaz de dépôt comprenant des espèces contenant du carbone et de l'hydrogène, à former un plasma à partir du gaz de dépôt, à déposer une couche polymère sur la couche à graver exposée autour du bord externe de la plaquette, le polymère étant formé à partir du plasma du gaz de dépôt, puis, enfin, à graver la couche à graver à travers le masque de résine photosensible en consommant le masque de résine photosensible et le polymère déposé sur la couche à graver exposée autour du bord externe de la plaquette.
PCT/US2005/029308 2004-09-03 2005-08-17 Gravure avec controle d'uniformite WO2006028673A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007529970A JP2008512853A (ja) 2004-09-03 2005-08-17 均一性を制御したエッチング
KR1020077007645A KR101155843B1 (ko) 2004-09-03 2005-08-17 균일성 제어에 의한 에칭

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/934,324 US7090782B1 (en) 2004-09-03 2004-09-03 Etch with uniformity control
US10/934,324 2004-09-03

Publications (1)

Publication Number Publication Date
WO2006028673A1 true WO2006028673A1 (fr) 2006-03-16

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US (1) US7090782B1 (fr)
JP (2) JP2008512853A (fr)
KR (1) KR101155843B1 (fr)
CN (1) CN100487874C (fr)
TW (1) TWI405265B (fr)
WO (1) WO2006028673A1 (fr)

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US20130267097A1 (en) * 2012-04-05 2013-10-10 Lam Research Corporation Method and apparatus for forming features with plasma pre-etch treatment on photoresist
CN103456623A (zh) * 2012-05-29 2013-12-18 上海宏力半导体制造有限公司 减少晶圆边缘聚合物沉积的刻蚀控制方法
CN103000513B (zh) * 2012-12-19 2015-10-28 复旦大学 一种多孔低介电常数材料SiCOH薄膜的刻蚀方法
US10386829B2 (en) * 2015-09-18 2019-08-20 Kla-Tencor Corporation Systems and methods for controlling an etch process
CN109273358A (zh) * 2018-08-31 2019-01-25 上海华力集成电路制造有限公司 晶圆的侧墙刻蚀方法

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TW200618115A (en) 2006-06-01
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