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WO2006022036A1 - Semiconductor device, display device, and device manufacturing method - Google Patents

Semiconductor device, display device, and device manufacturing method Download PDF

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Publication number
WO2006022036A1
WO2006022036A1 PCT/JP2004/013773 JP2004013773W WO2006022036A1 WO 2006022036 A1 WO2006022036 A1 WO 2006022036A1 JP 2004013773 W JP2004013773 W JP 2004013773W WO 2006022036 A1 WO2006022036 A1 WO 2006022036A1
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WO
WIPO (PCT)
Prior art keywords
fiber
display device
substrate
light emitting
film
Prior art date
Application number
PCT/JP2004/013773
Other languages
French (fr)
Japanese (ja)
Inventor
Tsuneo Suzuki
Takeshi Hirayama
Hisashi Koaizawa
Kiyoshi Yase
Kenkichi Suzuki
Michio Kondo
Original Assignee
The Furukawa Electric Co., Ltd.
National Institute Of Advanced Industrial Scienceand Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by The Furukawa Electric Co., Ltd., National Institute Of Advanced Industrial Scienceand Technology filed Critical The Furukawa Electric Co., Ltd.
Priority to JP2006531230A priority Critical patent/JP4953365B2/en
Publication of WO2006022036A1 publication Critical patent/WO2006022036A1/en
Priority to US11/377,581 priority patent/US20060257074A1/en
Priority to US12/696,670 priority patent/US8029327B2/en

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6758Thin-film transistors [TFT] characterised by the insulating substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00Organic light-emitting devices
    • H10K50/10OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/182OLED comprising a fiber structure
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/127Active-matrix OLED [AMOLED] displays comprising two substrates, e.g. display comprising OLED array and TFT driving circuitry on different substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00Manufacture or treatment specially adapted for the organic devices covered by this subclass

Definitions

  • the present invention relates to a semiconductor device, a display device, and a device manufacturing method, and more particularly, to a semiconductor device that constitutes an organic EL display device and the like, and a method for manufacturing a device such as an organic EL display device.
  • a-Si TFT As a display medium, a-Si TFT (Amorphous-Silicon-TFT) is currently the mainstream as an active matrix. 10 "to 20" diagonal displays are mass-produced for PCs and monitors.
  • LCD Liquid Crystal Display
  • CRT Cathode Ray Tube
  • organic LEDs OLED: Organic Light-Emitting-Diode
  • TFT has recently been rapidly developed and commercialized for low-temperature process polycrystalline Si (low-temperature p-Si). This is because the TFT performance of p-Si is high and peripheral circuits can be built in. Therefore, there is a merit of cost reduction.
  • a-Si TFTs are difficult to drive organic LEDs from the viewpoint of drive current density, and TFTs, including application to LCDs, tend to move to low-temperature p-Si as a whole.
  • the low-temperature p-Si TFT-LCD has excellent TFT performance in principle and can be embedded in peripheral circuits, but there is a big problem in reality.
  • the substrate is glass
  • the process has a low temperature of 500 ° C or less, non-uniformity due to polycrystals, and lithography accuracy of 1 m or more.
  • the peripheral circuit it is necessary to achieve the same performance as Si LSI, but under these restrictions, it is difficult to achieve high image quality and low definition! It is applied to a part of the peripheral circuit of the display. This is the situation.
  • the display medium is an organic LED, that is, TFT-OLED (TFT-Organic Liquid-Emitting Diode)
  • TFT-OLED TFT-Organic Liquid-Emitting Diode
  • the pixel drive circuit is composed of several transistor modules that are not composed of a single transistor, like an LCD, for current drive.
  • p-Si TFTs must be used for large, high-definition displays.
  • the substrate is made of glass, which has a fundamental problem with the TFT itself as described above, and, like the a-SKTFT-LCD manufacturing technology, a large glass substrate is used for cost reduction. It must be used.
  • the organic LED is composed of 5-8 layers of organic thin film.
  • the total film thickness is about 100 to 500 nm, and the thickness of each component film must be formed with an accuracy of about 1 degree.
  • pixels corresponding to three colors must be formed separately over a large area.
  • the current consumption was 1 A / cm 2 when driven by voltage.
  • the current resistance is 10 ⁇ : L00mA / cm 2 which greatly improves the wiring resistance. Must be reduced by several orders of magnitude compared to LCD wiring. It is clear that these manufacturing problems become more difficult to resolve as the display becomes larger and more detailed.
  • p-Si TFT-LCDs based on the current a-Si TFT-LCD manufacturing equipment technology.
  • p-Si TFT-LCDs are in a more difficult situation where Si LSI processes must be realized at low temperatures. Cost reduction by built-in circuit is one of the advantages of p-Si TFT-LCD. This is true when high-performance circuits are realized. In practice, the larger the substrate, the more difficult it is to achieve the various requirements for high-performance devices, such as film quality, photolithography accuracy, and Si LSI-like processes. In this respect, p-Si TFT-OLED is exactly the same, and problems such as LED structure and wiring resistance are added as described above.
  • An object of the present invention is to provide a semiconductor device, a display device, and a device manufacturing method using a one-dimensional substrate that solve these various performance and manufacturing problems, and that further achieve low costs. .
  • a first aspect of the present invention is a semiconductor device having a semiconductor layer formed on a surface of a quartz fiber and an active element formed on the semiconductor layer.
  • a second aspect of the present invention is characterized by having a fiber that also becomes a transparent insulating material, an electrode film formed on the fiber, and a light emitting layer formed on the fiber. This is a display device.
  • a third aspect of the present invention includes a first fiber in which an active element is formed, a composite one-dimensional substrate coupled to the first fiber and the first fiber, and a plurality of regions. And a second fiber on which a light emitting layer is formed.
  • a fiber having a semiconductor layer or an insulating layer formed on a surface thereof and further covered with a protective film is drawn out from a winding jig force, and is pulled out from the winding jig.
  • the protective film is removed, and the portion of the fiber from which the protective film has been removed is cut into a required length to be divided into a plurality of pieces, and the plurality of fibers are attached to a fixed jig at intervals from each other. At least one of an active element and a passive element is formed on the fiber fixed to a fixing jig.
  • the present invention proposes a “one-dimensional substrate” t based on quartz fiber or the like with respect to a conventional two-dimensional substrate, and proposes the above-described display device. It is to solve these problems.
  • the one-dimensional substrate of the present invention corresponding to a conventional SOI (Silicon On Insulator) substrate is a silicon single crystal or polycrystalline thin film formed on a quartz fiber, and is hereinafter referred to as an SOI fiber.
  • This one-dimensional substrate manufacturing method is a high-temperature manufacturing technology for forming a silicon thin film crystal simultaneously with quartz fiber drawing. Further, a high-quality gate oxide film is obtained by thermally oxidizing the resulting silicon film. Can also be produced. This is hereinafter referred to as an oxide-coated SOI fiber. If these are used, the base material is quartz, so that the same process and process flow as the two-dimensional SOI substrate can be used in place of the low-temperature process of the glass substrate, and various high-performance semiconductor elements can be formed. .
  • ITO fiber corresponds to the two-dimensional ITO (Indium Tin Oxide) glass substrate used in organic LEDs! This also forms a capsule simultaneously with the drawing of the quartz fiber.
  • plastic fibers can be used because the film can be formed at a lower temperature than silicon thin film formation.
  • a so-called bottom emission type organic LED is formed with a process flow similar to that of two-dimensional. In this case, the three RGB colors are formed on separate fibers.
  • an active matrix TFT-OLED starting from an SOI fiber, a pixel driving circuit that also has MOS transistor element strength is formed.
  • the organic LED may be formed on the same fiber, or the organic LED may be formed on another fiber to combine both. Regardless of whether they are single or composite, pixels corresponding to the number of rows corresponding to the pixel pitch in the vertical direction of the screen are regularly arranged on one fiber to constitute one column of the display surface.
  • single fiber In this case, the OLED method is limited to the front emission. In the case of a compound compound, both the bottom and front methods can be used. Furthermore, in the case of a composite, it is advantageous that different technologies such as TFT and OLED can be independently developed and improved.
  • the “substrate” is a fiber and has a special shape. Conventional SOI process and organic LED process are applied as they are. However, in order to actually make this, two factors must be considered.
  • the first factor is the shape of the fiber.
  • a normal circular or elliptical cross section is advantageous for producing a light emitter such as an OLED.
  • a square shape is advantageous for SOI. In this way, the shape must be selected depending on the application.
  • the second factor is a fiber-specific manufacturing method, and two methods are conceivable.
  • a fiber having a required length is wound around a winding jig, and the fiber coming out of the fiber passes through a device corresponding to the process and is wound around another winding jig.
  • a basic production line configuration is possible.
  • Equipment installed between two winding jigs that is, the number of processes, the length of the equipment for one fiber, the number in parallel, whether it is intermittent or constant speed, etc.
  • the essential issue is throughput, and basically it is to run a single fiber at as high a speed as possible. This is because the conventional flat substrate has a force that allows the process to proceed over a large area, and in the case of quartz fiber, it basically proceeds in units of one pixel.
  • the process time per pixel becomes very short.
  • a 6-digit high-speed process is required.
  • the constant velocity is a device required to synchronize when a pattern is formed on a traveling substrate as in the exposure process, or to maintain uniformity in film formation and etching. It is a characteristic.
  • the manufacturing equipment is also “one-dimensional” so that it becomes very small, and it is thought that high-speed processing can be realized by changing to the gas phase process force liquid phase which is the base of the conventional flat substrate.
  • the one-dimensional substrate is cut into an appropriate length, and these are arranged and fixed on the surface of a cylinder or a polygonal column, and the force is used as a substrate, or a so-called interdigital shape.
  • This is a method of displacement, which is used as a roller method.
  • the former has a structure in which a flat substrate is rolled into a cylindrical shape, and the manufacturing apparatus is greatly reduced compared to a flat substrate.
  • the process area can be made into a linear shape corresponding to the fiber, and the process rate can be significantly increased at the same time as downsizing of the apparatus by the concentrated system of exposure, vapor deposition source, ion source, plasma source and the like.
  • FIGS. L (a), (b), and (c) are diagrams showing the concept of a one-dimensional substrate.
  • Fig. 1 (a) shows an SOI substrate with a Si thin film crystal formed on a quartz fiber with a square cross section (the corners are actually round) as a specific example
  • Fig. 1 (b) shows a specific example.
  • An ITO substrate with an ITO film formed on a quartz fiber with a circular cross section is shown
  • Fig. 1 (c) shows a structure in which a thermal oxide film is formed on S pus in Fig. 1 (a).
  • FIGS. 2 (a) and 2 (b) are diagrams showing a concept of a display device constituted by a one-dimensional substrate.
  • Fig. 2 (a) is a bird's-eye view of a form in which a square fiber in which pixel drive circuits and wiring are stacked and an OLED is formed and a round fiber is combined. A gate line is connected to the lower surface of the square fiber.
  • FIG. 2B shows the connection between the display surface and the external drive circuit.
  • FIGS. 3 (a), 3 (b), and 3 (c) are diagrams showing a pixel drive circuit and wiring arrangement on a square fiber.
  • Fig. 3 (a) is a diagram of the pixel drive circuit, OLED fiber connection pad, signal line, and current supply line from one side. The wiring is continuous on the fiber axis, and the pixel drive circuit and OLED fiber are connected. The same pattern is repeated at the pixel pitch on the connection pad to the bar.
  • Fig. 3 (b) is a cross-sectional view of a square fiber. The signal line and current supply line run on two sides orthogonal to the first side.
  • Fig. 3 (c) shows the signal line at the terminal and the terminal of the current supply line on the same side as Fig. 3 (a).
  • FIGS. 4 (a) and 4 (b) are diagrams showing the structure of a round OLED fiber.
  • Fig. 4 (a) is a cross-sectional view of the bottom emission type. The OLED is formed in the third and fourth quadrants, and light is emitted from the first and second quadrants.
  • Fig. 4 (b) is a plan view of the pad direction.
  • FIGS. 5 (a) and 5 (b) are diagrams showing the structure of a round front emission type OLED fiber.
  • Fig. 5 (a) is a cross-sectional view. OLEDs are formed in the first and second quadrants, and light is emitted from these forces.
  • FIG. 5 (b) is a plan view.
  • FIG. 6 is a pixel drive circuit diagram.
  • FIG. 7 is a view of a laminate structure of a display device constituted by a composite one-dimensional substrate, as viewed from a cross section perpendicular to the composite fiber.
  • FIG. 8 is a view of a laminate structure of a display device constituted by a composite one-dimensional substrate as seen from a cross section parallel to the composite fiber, and particularly shows a structure near a terminal.
  • FIGS. 9 (a) and 9 (b) are diagrams showing a TFT process flow that also starts the SOI substrate with an oxide film.
  • FIGS. 10 (a) and 10 (b) are diagrams showing a process flow of a bottom emission type OLED using an ITO substrate.
  • FIGS. L l (a) and l (b) are diagrams showing a process flow of a front emission type OLED starting from a fino with a metal film.
  • FIG. 12 is a diagram showing a manufacturing process of a one-dimensional substrate and a display device using the same.
  • FIG. 13 is a view showing the concept of an apparatus for producing a one-dimensional substrate such as an SOI fiber or an ITO fiber.
  • FIG. 14 is a diagram showing a concept of an apparatus for segmenting a one-dimensional substrate and arranging it on a substrate jig surface in order to use it as a process substrate.
  • FIGS. 15 (a), (b), and (c) are diagrams showing three types of configuration examples in which a segmented fiber is a “process substrate”.
  • the “substrate jig” is cylindrical or columnar, and the fibers are arranged and fixed on this surface.
  • Fig. 15 (b) shows the substrate jig with the middle part of the S-ring-shaped fixed part, and Fig. 15 (c) shows the process in which both ends of each fiber have a micro-clamp head and are connected to form an interdigital shape. The substrate is shown.
  • FIGS. 16 (a), 16 (b), and 16 (c) are diagrams showing the principle of an apparatus for film formation, dry etching, impurity doping, etc. on a cylindrical substrate.
  • Fig. 16 (a) shows a type using a focused beam or concentrated plasma state such as ion cluster beam, metal spray, atmospheric pressure plasma, etc.
  • Fig. 16 (b) G), (b) and (ii) are cylindrical CVD devices. Two forms are shown.
  • FIGS. 16 ( C ) G) and (c) (ii) show the sputtering system corresponding to FIGS. 16 (b) G) and (b) (ii).
  • FIG. 17 is a view showing the principle of an apparatus for applying a resist, an organic film or the like.
  • FIG. 18 shows the principle of a high-precision exposure machine.
  • FIG. 19 is a diagram showing the principle of the illumination optical system.
  • FIG. 20 is a diagram showing the principle of an optical system for 1: 1 proximity exposure.
  • FIGS. 21 (a), (b), and (c) are diagrams showing the principle of a wet process system such as development, peeling, wet etching, and cleaning.
  • Fig. 21 (a) shows a horizontal wet tank
  • Fig. 21 (b) shows a vertical wet tank
  • Fig. 21 (c) shows a wet method applicable to a tin substrate.
  • FIGS. 22 (a) and 22 (b) are diagrams illustrating the principle of assembling a composite fiber of TFT and OLED.
  • Fig. 22 (a) shows a method of depositing bumps on a cylindrical substrate
  • Fig. 22 (b) shows a method of connecting OLED fibers to TFT fibers.
  • FIGS. 23 (a) and 23 (b) are diagrams showing a method of arranging a composite fiber to display a display panel.
  • Figure 23 (a) shows a frame for alignment.
  • Figure 23 (b) shows the positional relationship between the frame and the fiber.
  • FIGS. 24 (a) and 24 (b) are diagrams showing a method of attaching a gate line to an array of composite fibers.
  • FIG. 24 (a) shows a frame for gate line arrangement.
  • Figure 24 (b) shows the positional relationship between the frame and the gate line.
  • FIG. 25 is a diagram showing the principle of a microwelder.
  • FIGS. 26 (a) and 26 (b) are diagrams showing a method of attaching two common wires to an array of composite fibers.
  • Figure 26 (a) shows a frame for common line arrangement.
  • Figure 26 (b) shows the positional relationship between the frame and the common line.
  • 10 Square cross-section silica fiber, 10 ': Round cross-section silica fiber, 11: Si thin film crystal, 11': ITO, 12: Thermal oxide film, 20: TFT fino, 21: OLED fino, 25,25 ': FPC or PCB, 2 6,26 ': External drive circuit, etc.
  • Figures l (a), (b) and c) show a conceptual diagram of a one-dimensional substrate based on quartz fiber.
  • reference numerals 10 and 10 ′ denote quartz fibers, which are produced by the same method as the optical fiber drawing process.
  • Figures l (a) and (b) show examples of circular and square cross-sections, respectively, but they can be oval, rectangular, or tube-shaped depending on the application.
  • the diameter of the fiber or the size of one side shall be 800 m or less where the fiber can be wound.
  • Reference numeral 11 denotes a single crystal or polycrystalline film of Si, which is called an SOI fiber. In this case, the thickness of the Si film is about 100 mm.
  • reference numeral 12 denotes an oxide film such as a thermal oxide film formed on the surface of Si.
  • the one-dimensional substrate in the second category is the one in which transparent electrodes such as ITO, zinc oxide, and oxide tin with a thickness of about 100 ° are formed instead of Si in Figs. L (a) and (b). .
  • transparent electrodes such as ITO, zinc oxide, and oxide tin with a thickness of about 100 ° are formed instead of Si in Figs. L (a) and (b).
  • high temperatures are not required to form the Si film, so that multi-component glass, plastic substrates, and other transparent insulating materials can be used instead of quartz.
  • FIG. 2 (a) shows a TFT with a composite one-dimensional substrate having a rectangular SOI fiber 20 with a pixel drive circuit and wiring and round ITO fibers 21-23 formed with a plurality of organic LEDs.
  • a plurality of ITO fibers 21, 22, and 23 in which RGB (red, green, and blue) pixel rows are formed are arranged in accordance with the pixel pitch, and a gate line 24 is connected orthogonally thereto.
  • the end of each wire is connected to a wiring board (PCB: Printed Circuit Boad) Fixed to 25,25 'and connected to the driver IC chip 26,26' mounted on the board.
  • PCB Printed Circuit Boad
  • a plurality of red pixels are formed in a row in the first ITO fiber 21, and a plurality of green pixels are formed in a row in the second ITO fiber 22.
  • the third ITO fiber 23 has a plurality of red pixels formed in a row.
  • Fig. 3 (a) shows a cross-sectional view of a rectangular SOI fiber in which a pixel drive circuit and wiring are configured
  • Figs. 3 (b) and 3 (c) show its plan views.
  • On one side (A) an organic EL (electroluminescence) pixel drive switch circuit 31 is formed.
  • a connection terminal 32 and a part of the signal line 33 and a part of the current source line 34 are connected to the organic LED in the same plane, and each is connected to the drive switch circuit 31.
  • the signal line 33 and the current source line 34 are applied to a part of the surface (D) passing through the surface (B) and (C) orthogonal to the surface (A) and facing the surface (A), respectively, and the longitudinal direction of the fiber. It extends throughout.
  • Fig. 3 (c) shows the configuration near the fiber terminal on side (D), 35 is a gate line node, and 36 and 37 are signal line and current source line terminal pads.
  • the drive switch circuit 31 is composed of an active element such as a MOS transistor.
  • FIG. 4 (a) A cross-sectional view of the round IT0 fiber is shown in Fig. 4 (a), and a plan view of the round IT0 fiber viewed from the bottom of the figure is shown in Fig. 4 (b).
  • This is a so-called bottom emission type organic LED configuration, in which an organic EL film 42 is stacked on an IT0 film 41 formed on the surface of a quartz or plastic fiber 40, and a cathode separated for each pixel.
  • a metal film 43 is formed.
  • the organic LED is formed so that it falls within the third and fourth quadrants (lower half of the figure) in Fig. 4 (a), and light is emitted from the first and second quadrants (upper half of the figure).
  • a pad 46 that penetrates the protective film 44 and is connected to the SOI fiber is formed for each pixel.
  • the metal electrode 45 is formed in the OLED in the longitudinal direction of the fiber and the part that does not interfere with the exit surface, so that it can be used for large screens.
  • FIGS. 5 (a) and 5 (b) there is a so-called front emission type organic LED method, and its cross section and plan view are shown in FIGS. 5 (a) and 5 (b).
  • a base metal film 51 and a cathode metal film 52 separated for each pixel are formed on the surface of a quartz or plastic fiber 50, and an insulating layer 55 is formed on a portion excluding the light emitting surface.
  • the organic EL layer 53 is formed so as to be within the first and second quadrants of FIG. 5 (a), and an ITO film 54 serving as a full-surface electrode is formed thereon.
  • Underlying metal film 51 Extends to the third and fourth quadrants, and pads 58 are formed for each pixel through the insulating layer 55 and the protective film 57 and connected to the SOI fibre.
  • the ITO reinforcing electrode 56 is formed in a region excluding the pad 58 and the light emitting surface.
  • organic EL laminated structure a 2-6 layer structure is used.
  • the composition and materials of each color are as follows.
  • FIG. 6 shows an example of an equivalent circuit of a fiber TFT-OLED.
  • reference numeral 60 is a pixel driving circuit corresponding to 31 in FIG. 3
  • 61 is an ITO electrode of an organic LED
  • 62 force organic EL layer
  • 63 is a cathode electrode
  • 64 is a common line including ITO and a reinforcing electrode
  • 65 is Bump that joins SOI fiber.
  • 61—65 corresponds to OLED fiber.
  • 66 is a signal line
  • 67 is a current source line
  • 60, 66, and 67 correspond to SOI fibers.
  • 68 is an external gate line.
  • FIG. 7 is a cross-sectional view perpendicular to the fiber in the fiber TFT-OLED structure.
  • Each of the composite lines of the SOI fiber 70 and the OLED fiber 71 corresponds to an RGB pixel column in the vertical direction of the display, that is, in the column direction.
  • the gate line 72 is connected to each pixel.
  • the external common line 73 may be one or two at the edge of the screen. This is also the force of attaching a metal reinforcing electrode to the ITO common electrode.
  • a fiber network composed of 70-73 is laminated with a black insulating resin 74 on the lower part of the light emitting part of the OLED fiber and a transparent resin 75 on the upper part. Furthermore, for protection of organic EL, it is against moisture, oxygen, etc.
  • Overlay Nolla film 76, 76 ' for protection of organic EL, it is against moisture, oxygen, etc.
  • FIG. 8 is a cross-sectional view in the direction parallel to the fiber in the fiber TFT-OLED structure, and particularly shows the configuration near the terminal portion.
  • a gate line 82 is connected to each pixel orthogonal to a composite TFT-OLED fiber consisting of SOI fine 80 and OLED fiber 81.
  • the common lines 83 and 83 'that connect the common electrodes of the OLEDs need only be at the screen edges.
  • the signal line and current supply line on each fiber are connected to an external circuit.
  • FPC87 and PCB88 for TAB or relay with driver IC are connected.
  • a one-dimensional substrate composed of LED pixels is coupled to each other at each corresponding pixel to form a composite one-dimensional substrate.
  • This composite one-dimensional substrate constitutes one row of the display surface.
  • one end force on the fiber is injected into the linear conductor signal line 33 running in the longitudinal direction of the fiber and the organic LEDs 42 and 53 constituting each pixel in order to introduce an external force image signal to each pixel.
  • a linear conductor current supply source 34 for supplying a current to be generated is formed in the same SOI fiber 20.
  • the number of these composite fibers 20-23 required for the number of columns on the display screen is regularly arranged in correspondence with the pixel pitch in the horizontal direction of the screen, and signals such as pixel display timing are orthogonal to these.
  • a gate line 24 of a linear conductor introduced into the pixel drive circuit 31 is connected to the SOI fiber 20.
  • a common electrode line 61 that connects the transparent electrodes 41 and 54 that are the light emission and emission surfaces of the ITO fibers 21 to 23 including the organic LEDs 42 and 53 is connected.
  • External drive circuits 26 and 26 'for applying a signal or a control signal for driving a pixel to the ends of the signal line 33 and gate line 24 on the fiber 20 are common to each current supply source 34.
  • the same potential source is connected to each common electrode line 61.
  • the entire mesh thus configured is attached to the light emitting side with a rigid or flexible transparent organic resin or the like on the opposite side, and the black organic resin or the like is attached to the opposite side to protect the above mesh screen.
  • a flat-panel TFT-organic LED light-emitting display with a thickness of 3 mm or less is constructed. In place of SOI fiber 20, use an SOI fiber with an oxide film.
  • FIGS. 9 (a) and 9 (b) are diagrams showing an example of a TFT process when an SOI fiber with an oxide film is used.
  • step (1-3) of FIGS. 9A and 9B an island of the silicon film 90 including the oxide film 91 is formed.
  • the circuit area is 28x2 4 ⁇ m. Even if various other circuit methods are used, an area of 50 ⁇ mD is sufficient.
  • the side surface of the silicon film 90 is plasma oxidized, thermal oxidized, oxide film formed, etc.
  • the gate electrode 93 is formed on the oxide film by covering with an oxide film.
  • metal tongue tungsten, tungsten silicide or the like was used as the gate electrode 93.
  • the source and drain regions 941 and 942 in the n-channel TFT have LDD (Lightly Doped Drain) width of about 1 ⁇ m. )
  • a structure having region 95 is formed. Impurities are introduced at a low concentration first.
  • the resist film thickness applied to the edge of the gate electrode 93 was adjusted to 1 ⁇ m, and high concentration implantation was performed.
  • an oxide film window is opened in an area corresponding to the source and drain regions, and low concentration ion implantation is first performed by plasma doping.
  • a high concentration of ions was introduced by plasma doping while adjusting the resist film thickness to 1 ⁇ m.
  • the first interlayer insulating film 96 is formed. Films were formed and through holes 961, 962,963 were opened to form wirings 971, 972, and 973 for the source, gate, and drain, respectively. At this time, Ti was used as the barrier metal and A1 was used as the wiring metal. At this stage, a part of the wiring for connecting each element in the pixel driving circuit and a part of the wiring for the signal line and the current supply line are formed.
  • a second interlayer insulating film 98 is formed, and the pixel driving circuit and gate pad are formed. Some connections to the circuit and no wiring 991 993 made.
  • deposit A1 for wiring on the side of the fiber complete the connection between the wiring pattern and the circuit, and then form a second interlayer insulating film on the side again to form A1 and form a pattern. To complete the connection to the gate pad.
  • FIGS. 10 (a) and 10 (b) Process diagrams (cross-sectional views) of one OLED fiber are shown in Figs. 10 (a) and 10 (b).
  • the method is bottom emission.
  • the starting one-dimensional substrate is a so-called ITO fiber on which an ITO film 101 is formed in advance.
  • A1 reinforcement wire 102 was formed on this by mask film formation or registry shift-off.
  • the first and second quadrants when the cross-section of the figure is represented by the XY coordinates are the EL light emission surfaces.
  • steps (2-4) of Figs. 10 (a) and 10 (b) the EL layer 103 Are formed in the third and fourth quadrants. Then, as shown in step (5) of FIGS.
  • the cathode metal electrode 104 on the EL layer 103 is separated for each pixel and is formed by mask deposition. Further, as shown in steps (6-9) of FIGS. 10 (a) and 10 (b), a transparent photosensitive resin 105 is applied to all of them, and exposed and cured except for through-holes to the cathode. The unexposed part becomes a through hole by development, and is filled with low melting point solder, conductive adhesive, etc. 106 by means such as ink jet, dispenser, etc., and used as a connection pad with SOI fiber.
  • FIGS. Ll (a) and (b) are process diagrams of a front emission type OLED fiber.
  • Fig.ll (a), (b) As shown in steps (16) and (7-8), the pattern 111 is formed by using the metal film on the one-dimensional substrate metal film fiber 110 as the connection terminal to the base electrode and the SOI substrate in pixel units, and then An insulating film 113 is formed on a semicircular portion opposite to the light emitting portion including the terminal portion. A through hole for the base metal terminal is formed at the same time as the patterning of the insulating film. Next, the metal ITO reinforcing electrode 112 is formed on the insulating film so as not to overlap the terminal portion.
  • a part of the metal film has a connection terminal with the base terminal electrode on the insulating film 113 through the through hole.
  • steps (19), (20-23), and (25) of Fig. Ll (a) and (b) the cathode electrode 114 and the organic EL layer 115 are not affected by the lower half circle. Is mask-deposited to make contact with the reinforcing electrode to form the OLED part. These are all covered with a photosensitive transparent resin 117 as shown in step (26) of Fig. 1 l (a) and (b), photocured with the exception of the connecting terminals, and the terminals are developed through holes.
  • the connection bumps to the SOI substrate are formed by means such as ink jet or dispenser.
  • the entire manufacturing process is roughly divided into four, and the flow chart of the major division process is shown in Fig. 12.
  • the fiber 1D substrate manufacturing process corresponds to the process of making a wafer or SOI substrate with the current 2D technology, so it may be considered independent of the display manufacturing process.
  • these one-dimensional substrates are cut to fit the display size, arranged and fixed on the cylinder, polygonal column surface, or cylinder inner surface, and these are redesigned as “substrates” in the TFT and OLED manufacturing process. It is a process.
  • the manufacturing process of TFT and OLED is the same as that of 2D substrate as described above.
  • the last is the process of assembling the finished fiber into a product.
  • an HD-TV with an aspect ratio of 16: 9 and a diagonal of 50 "and 15" is used as a display.
  • SXGA is taken up as a specific target.
  • the definition of the former is 1080 X 19 20 (screen size ⁇ or 1106 X 622 mm), pixel size 0.75 to 0.576 ⁇ 0.576 mm, and the pitch of each RGB color is 0.192 mm in full spec.
  • the system used was a composite type, with 125 apertures for TFT and 125 ⁇ quartz fiber for OLED.
  • the resolution is 1024 x 1280 (screen size ⁇ or 228.6 x 304.8 mm), pixel size ⁇ or 0.223 x 0.223 mm, RGB pitch H was 0.08 mm, and 70 and 70 ⁇ fibers were used.
  • the length of fiber per color of HD-TV is about 1200m. Since the throughput time of the current large 2D substrate is 60 seconds, the traveling speed of fiber 1D substrate production is about 20m / s, which is the same throughput.
  • Fig. 13 shows the manufacturing principle of one-dimensional substrates such as SOI and ITO using quartz fiber.
  • 131 is a normal silica fiber drawing stage, in which a silica fiber of a given diameter is formed, and then in stage 132, the Si film is formed in a high-temperature atmosphere by CVD, spraying, melt coating-cooling, etc. In this way, a Si crystal was formed, and when winding the fiber, a resist was applied as a protective film at 133 and 134 and wound by a roll 135.
  • the stage 132 is an apparatus suitable for these, and the substrate is formed by the same process.
  • FIG. 14 shows a principle diagram of the segment arraying process.
  • a fiber 142 with a resist protective film is rolled out from a roll 14 1 wound with a one-dimensional substrate, and the resist is peeled off and cleaned in the middle 143 to form a “process substrate”.
  • a segmented fiber is fixed to the surface by a cutting / arranging device 144.
  • Figures 15 (a), 15 (b), and 15 (c) show conceptual diagrams of “process substrates” formed by segment arraying.
  • Reference numeral 151 shown in FIG. 15 (a) is a segmented fiber
  • 152 is a fixing jig that uses these fibers as a “process substrate”.
  • the basic structure is a cylinder, cylinder, or polygonal column with a rotation axis. Fiber positioning grooves are formed on the surface along the axial direction. Although not shown in the figure, the fiber on the fixture is fixed at both ends.
  • two rings 153 and 153 'shown in Fig. 15 (b) are connected by a column 154, and in this case also, a fiber positioning groove is formed on the ring surface. It has a configuration that maintains the linearity of the fiber by fixing and tension at both ends.
  • the jig is 76.4 ⁇ in diameter for 50 ”HD-TV, 622 mm in effective length, and 28.5 ⁇ and 229 mm in the case of 15” SVGA. Therefore, compared to a flat substrate, the “footprint” is 1/14 for HD-TV and 1/10 for a 15 ”display.
  • both ends of the fiber 151 are connected to a micro clamp 15 as shown in FIG. This is held at 5 and fixed to the chain 156, and this is hereinafter referred to as a “interdigital substrate”.
  • This is a convenient form for processing the roll-to-roll used in organic films.
  • the micro clamp 155 has a structure that can rotate at a constant angle simultaneously with a simple clamp, thereby facilitating the processing of each surface of the fiber. Of course, the micro clamp can be used even on the cylindrical substrate.
  • FIG. 16 (a) shows a type in which a process head 162 that generates a focused beam state or a concentrated plasma state such as an ion cluster beam, metal spray, atmospheric pressure plasma, etc. is installed in a vacuum chamber 160, and is a cylindrical substrate.
  • 161 is a method of performing film formation in a one-dimensional direction in the axial direction.
  • the rotation mechanism 163 performs film formation and processing on the entire surface of the substrate.
  • Fig. 16 (b) shows two types of cylindrical CVD apparatus.
  • (0 is the case where the cylindrical substrate 161 is inside the outer cylindrical shape 164
  • GO is a method in which the fiber is fixed to the inner wall of the cylindrical substrate 165. Configure the outer wall.
  • Fig. 16 (c) shows a sputtering apparatus system corresponding to Fig. 16 (b).
  • Fig. 16 (c) (0 is an external cylindrical shape 166 forms a vacuum chamber, and the inside is sputtered.
  • One or a plurality of targets 167 are installed, and film formation is performed on the entire surface of the cylindrical substrate 161 by the rotating mechanism 163.
  • Fig. 16 (c) shows that the cylindrical substrate itself is a substrate holder, and in some cases a vacuum.
  • Sputter target 168 is installed on the central axis in the system that doubles as the outer wall of the room!
  • Dry etching and equipment are essentially the same processes and equipment principles as plasma CVD (P-CVD) and sputtering in film formation. That is, the force at which the process head introduces the etching gas with an atmospheric plasma in FIG. 16 (a), the force to change the CVD gas to the etching gas in FIG. 16 (b), or the target in FIG. 16 (c). Force to use only electrode Perform dry etching by either method.
  • the force pattern formation described above regarding various film formation and dry etching methods and apparatus principles applies photolithography similar to a two-dimensional substrate to a cylindrical substrate.
  • Figure 17 shows the concept of the resist coating method.
  • reference numeral 171 denotes a configuration in which a resist agent is poured onto a cylindrical substrate 170 such as a slit locuser, and the cylindrical substrate is rotated, uniformized and entirely coated by a rotating mechanism 172.
  • a resist agent is poured onto a cylindrical substrate 170 such as a slit locuser, and the cylindrical substrate is rotated, uniformized and entirely coated by a rotating mechanism 172.
  • the entire cylindrical substrate is dipped in a resist solution and rotated around the central axis to form a uniform resist layer around the entire fiber.
  • the resist-coated cylindrical substrate is pre-beta in a cylindrical baking furnace.
  • FIG. 18 shows a conceptual diagram of a high-precision exposure machine used for the pixel circuit TFT.
  • the exposure machine is a system that exposes a single fiber on a cylindrical or polygonal column substrate 180.
  • Reference numeral 181 in the figure rotates the substrate around the central axis and simultaneously moves it in the axial direction. It is.
  • Reference numeral 182 denotes a 5: 1 reduction projection imaging lens having an exposure area of 5 mm, and a plurality of them are connected.
  • the alignment is controlled by the servo control mechanism 183 that controls each of the X-Y-Z three axes independently.
  • the control data is read at high speed with the optical head for detection 186 in the pre-exposure stage and stored in the calculation system 188 via the line 187, and the control signal is received from the calculation system 188. This is transmitted to line 183 via line 189 and servo control of the lens system is performed.
  • a mechanical stylus that senses the side of the fiber may be used instead of the optical head.
  • An excimer laser with a wavelength of 308 nm or 248 nm is used as the light source 185 of this exposure system.
  • the illumination optical system 184 is an ordinary Koehler illumination system, but using a cylindrical lens, etc., the illumination area is 0.2 mm wide and the length corresponds to the length of the concatenation lens system connection, and is at least 250 mm in slit shape. is there.
  • FIG. 19 shows an equivalent optical system of the exposure optical system.
  • the secondary light source 190 is created by the splitting lens 192 from the parallel light 190 of the excimer laser processed into an appropriate shape, and the mask 196 is formed with the light uniformly distributed in a given shape together with the secondary light source 193 and the capacitor lens 194. Illuminate.
  • the field lens 195 forms a secondary light source image on the entrance pupil 198 of the imaging lens 197 and forms a mask image on the imaging surface 199.
  • the optical system 190-195 in the figure represents either the X-axis or Y-axis direction of the slit-like illumination, and actually two sets of optical system forces. This is a force that is a common optical system, and the field lens 195 and later are separate optical systems.
  • the above is a pixel switch exposure method that requires high accuracy, but it does not require as high accuracy as a TFT, and in the case of a pattern over a large area, such as wiring in a pixel switch, a pattern in a node / node, and a fiber axis direction, etc.
  • 1: 1 proximity exposure as shown in Fig. 20 was used.
  • a cylindrical lens 202 designed to collect the incident light 204 at the center of the fiber at a sufficient angle to cover the end of the fiber 201 is placed parallel to the fiber, so that the mask pattern 203 is a curved surface of the fiber. Projected along.
  • the cylindrical lens is composed of one or a plurality of lenses, and is configured to correspond to the alignment with the fiber.
  • FIGS. 21 (a), (b), and (c) show the principle diagrams of a wet process system such as development, peeling, wet etching, and cleaning.
  • FIG. 12A shows a method in which the cylindrical substrate 211 is processed in a horizontal wet tank 212, and a plurality of wet processes are performed in the rotation and transfer system 213 in the tank.
  • Figure 21 (b) shows the case where the vertical tank 214 is used.
  • FIG. 21 (c) is a method adapted to the interdigital substrate 215 having the shape shown in FIG. 15 (c), and the wet tank 216 is passed through the roller transport systems 217-1 to 217-3. After washing, dry clean air or nitrogen is sprayed or blown like an air knife.
  • the process head in Fig. 16 (a) is a slit ion gun.
  • the plasma doping method and equipment are essentially the same process and equipment principle as P-CVD and sputtering in film formation. That is, in FIG. 16 (a), the process head introduces the impurity gas by atmospheric pressure plasma.
  • the CVD gas is changed to the impurity gas, or in FIG. 16 (c), only the electrode is used instead of the target.
  • Doping is performed by either method of introducing impurity gas.
  • the impurity activity is the usual thermal annealing method.
  • the hydrogen anneal in the process is performed using a hydrogen furnace as in a normal semiconductor process.
  • the TFT and OLED cylindrical substrates 221 or the interdigital substrate 223 Deposit solder or conductive adhesive used at low temperatures that will not damage the OLED on the pad using means such as inkjet 224.
  • the cylindrical substrate rotates and moves around the shaft 222.
  • the axial movement may be performed by the inkjet head 224.
  • remove one 225 (223) from the cylindrical substrate, etc. and use the jig 227 to hold and crimp both ends of the two fibers with bumps formed in this way. Crimp on fiber 226 after alignment. For fiber processed substrate jigs, the connection of both fibers is tested at this stage.
  • these double-wire fibers 231 are fixed to the fiber fixing frame 232 shown in FIG. 23 (a) in the order of RGB in accordance with the screen pitch.
  • This frame 235 (232) is outside the OLED fiber 233 so as not to interfere with the gate line connection described below, as shown in FIG. 23 (b).
  • a low melting point solder or the like is deposited on the gate pad of the TFT fiber 234 from the direction of the arrow 236 by an ink jet method or the like as described above.
  • a connection test of both fibers may be performed. Further, the unnecessary end portion is cut here.
  • the fiber and the gate line are connected.
  • a frame 241 in which a copper wire for a gate line is stretched according to the pixel pitch has a partially nested structure with the fiber fixing frame 232 shown in FIG. Copper wire is pre-coated with low-temperature solder.
  • the positional relationship between the fibers 242, 243 and the copper wire is as shown in Fig. 24 (b), and is connected to the lower side of the TFT fiber 243 under the OLED fiber 242 by thermocompression bonding or the laser micro welder shown in Fig. 25. .
  • the frame in FIG. 24 is on the XY stage, and the gate line 251 runs perpendicularly (Y) to the paper surface as shown in FIG.
  • the laser welding head emits pulse light in synchronization with the gate pad position.
  • the gate wire 251 is a continuous copper wire, the wire diameter is 100 m ⁇ , and the gap between the copper wires is 476 ⁇ m for 50 ”HD-TV.
  • the optical head part 253 of the microwelder is This is a micro-optics optical system consisting of a trapezoidal prism 254, a mirror 255, and a microlens 256.
  • the pulsed laser beam 257 is divided by a trapezoidal prism and is divided into both copper wires.
  • the bump 258 on the TFT fiber 252 is irradiated from the side.
  • a YAG laser fundamental wave is used as a laser, and this is condensed to 10 ⁇ or less by a lens 256 to melt and weld the bump.
  • the output of the original laser source must be in TEM mode. For this reason, it is usually used as a light guide system.
  • the vertical pixel pitch of the HD-TV we are considering now is 576 ⁇ m, so when using a light source with an oscillation frequency of 20 kHz, the moving speed is about 12 m / s.
  • the travel time for one gate line is approximately 0.1 seconds, so 108 seconds are required for the full screen.
  • each operation such as acceleration, deceleration, and movement of one pixel pitch requires less than 0.1 seconds each, and it takes about 400 seconds, that is, a force that requires about 7 minutes for one head.
  • One display could be completed in less than a minute.
  • the common wire frame 261 as shown in FIG. 26 (a) has a structure in which the two conductors 263 stretched on it are positioned above the OLED fiber 264 as shown in FIG. 26 (b). have .
  • the OLED fiber and the two common wires are pre-deposited with a conductive adhesive that is connected at a low temperature by a method such as ink jet.
  • a lighting inspection is performed using a professional bar, and in particular, the above connection is inspected.
  • the signal driver IC chip and the current source are connected to the end of the TFT fiber.
  • circuit components are attached to a flexible or rigid circuit board having a multilayer wiring force of 0.4 mm thickness, and terminals are formed for each vertical pixel column.
  • the method for connecting these to the fiber is exactly the same as described above.
  • the gate line and the common line are similarly connected to each other by a gate driver IC chip and a flexible or rigid circuit board such as a multilayer wiring card on which common electrodes are mounted arranged on the side perpendicular to the above.
  • the resin containing black paint is poured on the opposite side of the fiber exit surface, and then the transparent resin is poured on the fiber exit surface side.
  • Complete the display panel by shaping it into a flat plate so that is less than lmm.
  • an ultra-thin and large-sized high-definition display of 2 mm or less can be manufactured at low cost. Therefore, various application areas such as full-scale wall-mounted TV, medical use, and electronic paper will be expanded. Furthermore, since it is a completely new production device, it will be possible to speed up technological innovation because it will create a new industry and at the same time it will be small in size and low in manufacturing costs. Although I will not go into the contents here, the ripple effect of these devices and processes other than the display is enormous, and is particularly significant as a pre-stage leading to nanotechnology.
  • a planar substrate made of a silicon wafer or a glass substrate is used as a drive circuit element, and an OLED fiber arrayed with them. It can also be combined as an organic EL display!
  • the silicon wafer process has the advantage that it can be procured very inexpensively because of the large volume of semiconductor devices used.
  • it is very difficult to produce a high-definition display with an element size of 50 ⁇ m or less using a normal two-dimensional substrate. This is because when manufacturing an organic EL element, a metal shadow mask is used, and a different mask is used for each of the red, green, and blue masks.
  • the relative position accuracy between the mask and the substrate may be mask processing accuracy of 3 ⁇ m or less, alignment accuracy of about 5 ⁇ m, and displacement of 1 to 3 m due to deformation due to thermal expansion during the process. Therefore, the total length is about 5 to 10 m, and it is difficult to achieve the above element size below the industrial level.
  • the organic EL film can be arranged and arranged independently for each color by using a reel 'two' reel method.
  • the mask since the mask may be one or several slit-shaped shadow masks, it can be manufactured with an accuracy of 1 or less, and can be easily obtained by fixing the mask and intermittently moving the one-dimensional substrate on the mask. Films can be formed with high accuracy. Of course, if the mask is moved in synchronization with the movement of the one-dimensional substrate, it can be manufactured continuously.
  • an inexpensive and high-definition display can be achieved by combining an OLED fiber array and a TFT circuit board made of a two-dimensional substrate. Ray can be realized.
  • the TFT performance is much better than that of a polycrystalline TFT, so that high-speed response can be improved, complicated functions can be added to the circuit, and color correction can be improved.

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Abstract

A display device capable of eliminating the need of the allocation of substrates and using a one-dimensional substrate enabling a further reduction in cost, comprising a first fiber (80) on the surface of which a silicon layer or an oxide film in which active elements are formed is formed, and a second fiber (81) bound to the first fiber (80) to form the composite one-dimensional substrate in association with the first fiber (80), and having light emitting layers formed in a plurality of zones. The first fiber (80) and the second fiber (81) are extracted from take-up tools and cut into a plurality of pieces of required lengths. The pluralityof first and second fibers (80) and (81) are fitted onto a fixing tool parallel with each other and, in that state, at least ones of the active elements and passive elements are formed on the first and second fibers (80) and (81).

Description

明 細 書  Specification

半導体装置、表示装置およびデバイス製造方法  Semiconductor device, display device, and device manufacturing method

技術分野  Technical field

[0001] 本発明は、半導体装置、表示装置およびデバイス製造方法に関し、より詳しくは、 有機 EL表示装置等を構成する半導体装置、有機 EL表示装置等のデバイスの製造 方法に関する。  The present invention relates to a semiconductor device, a display device, and a device manufacturing method, and more particularly, to a semiconductor device that constitutes an organic EL display device and the like, and a method for manufacturing a device such as an organic EL display device.

背景技術  Background art

[0002] 現在主流のアクティブマトリックス型平面表示装置は、表示面に TFT (Thin Film [0002] Currently, active-matrix flat panel display devices that use the TFT (Thin Film)

Transistor)からなる画素駆動スィッチと画素表示媒体からなる平面ディスプレイであり 、出発点の基板はソーダライム等の透明ガラス板である。基板としてはプラスチックフ イルムを用いる試みがなされているが、未だ実用化に至らず、表示媒体としては液晶 力 アクティブマトリックスとしては a- Si TFT (Amorphous- Silicon- TFT)が現在のところ 主流であり、 PC用、モニタ用等に 10"から 20"対角サイズのディスプレイが量産され ている。 A flat panel display composed of a pixel drive switch composed of a transistor and a pixel display medium, and the starting substrate is a transparent glass plate such as soda lime. Attempts have been made to use plastic film as the substrate, but it has not yet been put to practical use. As a display medium, a-Si TFT (Amorphous-Silicon-TFT) is currently the mainstream as an active matrix. 10 "to 20" diagonal displays are mass-produced for PCs and monitors.

[0003] 表示媒体としての LCD (Liquid Crystal Display)は、 CRT (Cathode Ray Tube)と比 較した時、 TV動画の表示性能、特に白色、ホワイトピーク、応答性に問題がある。こ れに対して、最近開発、製品化が進められている有機 LED ((OLED: Organic Light-Emitting-Diode)は自発光であり、白色、ホワイトピーク応答性等 LCDより優れ た画質を実現出来る。  [0003] LCD (Liquid Crystal Display) as a display medium has problems in display performance of TV video, especially white, white peak, and responsiveness when compared with CRT (Cathode Ray Tube). On the other hand, organic LEDs (OLED: Organic Light-Emitting-Diode), which are being developed and commercialized recently, are self-luminous and can achieve better image quality than LCD, such as white and white peak response. .

[0004] 一方、 TFTも最近、低温プロセスの多結晶 Si (低温 p-Si)の開発、製品化が急速に 進められている。これはまず p-Siの TFT性能が高く周辺回路内蔵が可能、従ってコス ト低減のメリットがあるためである。これに加えて、有機 LEDの駆動には駆動電流密度 の面から a-Si TFTでは対応困難であり、 LCDへの適用も含めて TFTは低温 p-Siへの 移行が全体的傾向である。  [0004] On the other hand, TFT has recently been rapidly developed and commercialized for low-temperature process polycrystalline Si (low-temperature p-Si). This is because the TFT performance of p-Si is high and peripheral circuits can be built in. Therefore, there is a merit of cost reduction. In addition to this, a-Si TFTs are difficult to drive organic LEDs from the viewpoint of drive current density, and TFTs, including application to LCDs, tend to move to low-temperature p-Si as a whole.

[0005] アクティブマトリックス型平面表示装置をはじめとする全ての表示装置における巿場 の要求は、常に、表示サイズの大型化、高精細化、低コストの 3点である。これらの要 求に対して、現在主流の a-Si TFT-LCDは、性能改良の余地は僅かで、大型化に関 しては 40"対角 TV、高精細化に対しては 20"以下のディスプレイが実質的な限界で 、コスト対応はガラス基板の大型化が唯一の手段と言ってよい状況である。 [0005] The demands of all display devices including active matrix type flat display devices are always three points: large display size, high definition, and low cost. In response to these demands, the mainstream a-Si TFT-LCD has little room for performance improvement, and it is important to increase the size. For this reason, 40 "diagonal TV and a display of 20" or less for high definition are practical limits, and the only way to deal with cost is to increase the size of the glass substrate.

[0006] 一方、低温 p-Si TFT-LCDは原理的に TFT自体の性能は優れており、周辺回路内 蔵が可能であるが、実態としては大きな問題がある。即ち、基板がガラスのため、プロ セスは 500°C以下の低温であること、多結晶故の不均一性、リソグラフィ精度が 1 m 以上等種々の原理的問題がある。特に周辺回路においては、 Si LSIと同等の性能を 実現せねばならないが、この様な制限の下では高画質の実現は困難で、精細度の 低!、ディスプレイの周辺回路の一部に適用されて 、る状況である。  [0006] On the other hand, the low-temperature p-Si TFT-LCD has excellent TFT performance in principle and can be embedded in peripheral circuits, but there is a big problem in reality. In other words, since the substrate is glass, the process has a low temperature of 500 ° C or less, non-uniformity due to polycrystals, and lithography accuracy of 1 m or more. Especially in the peripheral circuit, it is necessary to achieve the same performance as Si LSI, but under these restrictions, it is difficult to achieve high image quality and low definition! It is applied to a part of the peripheral circuit of the display. This is the situation.

[0007] 表示媒体が有機 LED、即ち TFT- OLED(TFT- Organic Liquid- Emitting- Diode)の場 合、自発光、高速応答、薄型化等の観点力 LCDに比べてディスプレイの質は大幅 に向上する。但し、画素駆動回路は電流駆動のため LCDの様に 1個のトランジスタで なぐ数個のトランジスタカゝら構成される。均一性の利点から a-Si TFTで構成する試 みもあるが、大型、高精細ディスプレイに対しては p-Si TFTを用いざるを得ない。  [0007] When the display medium is an organic LED, that is, TFT-OLED (TFT-Organic Liquid-Emitting Diode), the viewpoints of self-emission, high-speed response, thinning, etc., display quality is greatly improved compared to LCD To do. However, the pixel drive circuit is composed of several transistor modules that are not composed of a single transistor, like an LCD, for current drive. Although there are attempts to use a-Si TFTs for the advantage of uniformity, p-Si TFTs must be used for large, high-definition displays.

[0008] ところが、基板はガラスであり、上述の様な TFT自体に対して原理的な問題を有す る上、 a-SKTFT-LCD製造技術と同様、低コスト化には大形ガラス基板を用いざるを 得ない。  [0008] However, the substrate is made of glass, which has a fundamental problem with the TFT itself as described above, and, like the a-SKTFT-LCD manufacturing technology, a large glass substrate is used for cost reduction. It must be used.

[0009] 有機 LEDは 5— 8層の有機薄膜からなる力 全膜厚が 100から 500nm程度であり、 各構成膜の厚みは 1應程度の精度で形成せねばならない。おまけに大面積に亘っ て 3色に対応した画素を分離して形成せねばならない。更に LCDの場合、電圧駆動 で消費電流が 1 A/cm2であったの力 OLEDの場合は電流駆動で 10〜: L00mA/cm2 と大幅に向上するため、電流源力ゝらの配線抵抗は LCDの配線に比べて数桁低減す る必要がある。こういった製造上の問題点は、ディスプレイが大型、高精細に成る程 解決が厳しくなることは明らかである。 [0009] The organic LED is composed of 5-8 layers of organic thin film. The total film thickness is about 100 to 500 nm, and the thickness of each component film must be formed with an accuracy of about 1 degree. In addition, pixels corresponding to three colors must be formed separately over a large area. Furthermore, in the case of LCD, the current consumption was 1 A / cm 2 when driven by voltage. In the case of OLED, the current resistance is 10 ~: L00mA / cm 2 which greatly improves the wiring resistance. Must be reduced by several orders of magnitude compared to LCD wiring. It is clear that these manufacturing problems become more difficult to resolve as the display becomes larger and more detailed.

[0010] これら本質的な問題は一見当然と見られる事実、即ち、 2次元の平板を基板として 用いるという従来技術の基本的な前提にある。即ち、基板サイズの拡大と同時に各プ ロセス精度の向上が要求され、製造装置は大型化と同時に精密化されねばならない 。当然機構的に或る限界があり、スループットにも限界が出てくる。実際、現在 a-Si TF-LCD製造装置として約 2 m角に近いサイズの基板に対応するものが製作、使用 されている力 これが装置、製造ラインのコスト一パフォーマンスにとっての一つの限 界と考えられている。 [0010] These essential problems are based on the fact that it seems natural at first glance, that is, the basic premise of using the two-dimensional flat plate as a substrate. In other words, it is required to improve the accuracy of each process at the same time as increasing the substrate size, and the manufacturing equipment must be refined at the same time as the size increases. Naturally, there is a certain limit in terms of mechanism, and there is a limit in throughput. In fact, currently a-Si TF-LCD manufacturing equipment that can handle and use a substrate with a size of about 2 m square is used. This force is considered a limit to the cost performance of equipment and production lines.

[0011] 現行の a- Si TFT- LCD製造装置技術をベースとする p- Si TFT- LCDにおいても事 情は全く同様である。おまけに p-Si TFT-LCDは Si LSI的なプロセスを低温で実現せ ねばならないと言う更に困難な状況にある。回路内蔵によるコスト低減が p-Si TFT-LCDの優位性の一つである力 これは高性能の回路が実現された時に成り立 つことである。実際には、基板が大形になる程、膜質、フォトリソグラフィの精度、 Si LSI的なプロセス等、高性能デバイスに必要な各種の要件を実現することは益々困難 となる。この点は、 p-Si TFT-OLEDも全く同様な上、前述の様に LED構造、配線抵抗 といった問題がさらに付け加わって来る。  [0011] The same is true for p-Si TFT-LCDs based on the current a-Si TFT-LCD manufacturing equipment technology. In addition, p-Si TFT-LCDs are in a more difficult situation where Si LSI processes must be realized at low temperatures. Cost reduction by built-in circuit is one of the advantages of p-Si TFT-LCD. This is true when high-performance circuits are realized. In practice, the larger the substrate, the more difficult it is to achieve the various requirements for high-performance devices, such as film quality, photolithography accuracy, and Si LSI-like processes. In this respect, p-Si TFT-OLED is exactly the same, and problems such as LED structure and wiring resistance are added as described above.

発明の開示  Disclosure of the invention

発明が解決しょうとする課題  Problems to be solved by the invention

[0012] 以上、大型基板を用いた場合の製造に関わる技術的問題を指摘したが、ディスプ レイの具体的な製品化に当たっては種々のサイズが要求される。サイズによっては、 基板の割付が必ずしも効率的に行われず、無駄を生ずる場合が出てくる。製造業者 の使用基板に最適なサイズが必ずしもユーザーにとっての最適サイズとは限らない。  [0012] Although technical problems related to manufacturing when a large-sized substrate is used have been pointed out above, various sizes are required for commercializing a display. Depending on the size, the board is not necessarily allocated efficiently, and waste may occur. The optimal size for the substrate used by the manufacturer is not necessarily the optimal size for the user.

[0013] 本発明の目的は、これら性能、製造上の種々問題を解決し、更に低コストを実現す る一次元基板を用いた半導体装置、表示装置およびデバイス製造方法を提供するこ とである。  [0013] An object of the present invention is to provide a semiconductor device, a display device, and a device manufacturing method using a one-dimensional substrate that solve these various performance and manufacturing problems, and that further achieve low costs. .

課題を解決するための手段  Means for solving the problem

[0014] 本発明の第 1の態様は、石英ファイバの表面に形成された半導体層と、前記半導 体層に形成された能動素子とを有する半導体装置である。 [0014] A first aspect of the present invention is a semiconductor device having a semiconductor layer formed on a surface of a quartz fiber and an active element formed on the semiconductor layer.

[0015] 本発明の第 2の態様は、透明絶縁材カもなるファイバと、前記ファイバの上に形成さ れる電極膜と、前記ファイバの上に形成される発光層とを有することを特徴とする表 示装置である。 [0015] A second aspect of the present invention is characterized by having a fiber that also becomes a transparent insulating material, an electrode film formed on the fiber, and a light emitting layer formed on the fiber. This is a display device.

[0016] 本発明の第 3の態様は、能動素子が形成される第 1のファイバと、前記第 1のフアイ バに結合されて前記第 1のファイバとともに複合一次元基板を構成し且つ複数領域 に発光層が形成される第 2のファイバとを備えた表示装置である。 [0017] 本発明の第 4の態様は、半導体層又は絶縁層が表面に形成されさらに保護膜によ り被覆されたファイバを巻き取り治具力 引き出し、前記巻き取り治具から引き出され た前記保護膜を除去し、前記ファイバのうち前記保護膜が除去された部分を必要な 長さに切断して複数本に分け、複数本の前記ファイバを互いに間隔をおいて固定治 具に取り付け、前記固定治具に固定された前記ファイバに能動素子、受動素子の少 なくとも一方を形成することを特徴とするデバイス製造方法である。 [0016] A third aspect of the present invention includes a first fiber in which an active element is formed, a composite one-dimensional substrate coupled to the first fiber and the first fiber, and a plurality of regions. And a second fiber on which a light emitting layer is formed. [0017] In a fourth aspect of the present invention, a fiber having a semiconductor layer or an insulating layer formed on a surface thereof and further covered with a protective film is drawn out from a winding jig force, and is pulled out from the winding jig. The protective film is removed, and the portion of the fiber from which the protective film has been removed is cut into a required length to be divided into a plurality of pieces, and the plurality of fibers are attached to a fixed jig at intervals from each other. At least one of an active element and a passive element is formed on the fiber fixed to a fixing jig.

[0018] 上記の目的を達成するために、本発明は、従来の二次元基板に対して石英フアイ バー等をベースとする「一次元基板」 t 、う新 U、コンセプトを提案、上記表示装置の 諸問題を解決しょうというものである。従来の SOI(Silicon On Insulator)基板に対応す る本発明の一次元基板は、石英ファイバー上にシリコン単結晶または多結晶薄膜を 形成したものであり、以下 SOIファイバと称す。  In order to achieve the above object, the present invention proposes a “one-dimensional substrate” t based on quartz fiber or the like with respect to a conventional two-dimensional substrate, and proposes the above-described display device. It is to solve these problems. The one-dimensional substrate of the present invention corresponding to a conventional SOI (Silicon On Insulator) substrate is a silicon single crystal or polycrystalline thin film formed on a quartz fiber, and is hereinafter referred to as an SOI fiber.

[0019] この一次元基板の製法は、石英ファイバ線引きと同時にシリコン薄膜結晶を形成す る高温の製造技術であり、さらに出来たシリコン膜を熱酸ィ匕して高品質のゲート用酸 化膜を形成したものも製造できる。これを以下酸化膜付 SOIファイバと称す。これらを 用いると、基材が石英であるのでガラス基板の低温プロセスに換えて二次元の SOI基 板と全く同様なプロセスおよびプロセスフローを用いることが出来、高性能な各種半 導体素子が形成できる。  This one-dimensional substrate manufacturing method is a high-temperature manufacturing technology for forming a silicon thin film crystal simultaneously with quartz fiber drawing. Further, a high-quality gate oxide film is obtained by thermally oxidizing the resulting silicon film. Can also be produced. This is hereinafter referred to as an oxide-coated SOI fiber. If these are used, the base material is quartz, so that the same process and process flow as the two-dimensional SOI substrate can be used in place of the low-temperature process of the glass substrate, and various high-performance semiconductor elements can be formed. .

[0020] 有機 LEDに用いられて!/、る二次元の ITO (酸化インジウム錫: Indium Tin Oxide)ガラ ス基板に対応するのが ITOファイバである。これも石英ファイバ線引きと同時に ΙΤΟ膜 を形成する。但し、シリコン薄膜の形成に比べて低温で成膜できるのでプラスチックフ アイバを用いても良 、。この上に 、わゆるボトムェミッション型の有機 LEDが二次元と 同様なプロセスフローで形成される。この場合、 RGB3色は独立のファイバ上に形成 されている。  [0020] ITO fiber corresponds to the two-dimensional ITO (Indium Tin Oxide) glass substrate used in organic LEDs! This also forms a capsule simultaneously with the drawing of the quartz fiber. However, plastic fibers can be used because the film can be formed at a lower temperature than silicon thin film formation. On top of this, a so-called bottom emission type organic LED is formed with a process flow similar to that of two-dimensional. In this case, the three RGB colors are formed on separate fibers.

[0021] アクティブマトリックス型の TFT-OLEDでは SOIファイバを出発点として、 MOSトラン ジスタ素子力もなる画素駆動回路を形成する。この場合、同一ファイバー上に有機 LEDを形成するか、または別のファイバに有機 LEDを形成して両者を複合しても良い 。単一にせよ複合にせよ一本のファイバー上に画面垂直方向画素ピッチに対応して 行数分の画素が規則的に配列され、表示面の一列を構成する。但し、単一ファイバ の場合は、 OLEDの方式としてはフロントェミッションに限定される力 複合の場合は ボトム、フロントいずれの方式も用いることが出きる。更に、複合の場合は、 TFT、 OLEDという異なった技術が独立に開発、改良できる点が有利である。 [0021] In an active matrix TFT-OLED, starting from an SOI fiber, a pixel driving circuit that also has MOS transistor element strength is formed. In this case, the organic LED may be formed on the same fiber, or the organic LED may be formed on another fiber to combine both. Regardless of whether they are single or composite, pixels corresponding to the number of rows corresponding to the pixel pitch in the vertical direction of the screen are regularly arranged on one fiber to constitute one column of the display surface. However, single fiber In this case, the OLED method is limited to the front emission. In the case of a compound compound, both the bottom and front methods can be used. Furthermore, in the case of a composite, it is advantageous that different technologies such as TFT and OLED can be independently developed and improved.

[0022] 以上、「基板」はファイバと 、う特殊な形状である力 従来の SOI工程、有機 LEDェ 程をそのまま適用する。但し、これを実際に製作するには、二つの要因を考慮せね ばならない。 [0022] As described above, the “substrate” is a fiber and has a special shape. Conventional SOI process and organic LED process are applied as they are. However, in order to actually make this, two factors must be considered.

[0023] 第一の要因はファイバの形状である。 OLEDのような発光体を作製するには通常の 円形乃至は楕円断面が有利である。一方 SOIとしては角型 (実際には角が丸くなるが )が有利であることは明らかである。この様に用途により形状を選択せねばならない。 第二の要因はファイバー特有の製造方法であり、二つの方法が考えられる。  [0023] The first factor is the shape of the fiber. A normal circular or elliptical cross section is advantageous for producing a light emitter such as an OLED. On the other hand, it is clear that a square shape (actually rounded corners) is advantageous for SOI. In this way, the shape must be selected depending on the application. The second factor is a fiber-specific manufacturing method, and two methods are conceivable.

[0024] 第一の方法として、必要な長さのファイバーを巻き取り冶具に巻いておき、これから 出たファイバーが工程に対応した装置を通過して、別の巻き取り冶具に巻き取られる と言う基本的な製造ライン構成が考えられる。 2つの巻き取り冶具の間に設置する装 置、即ち工程の数、 1本のファイバーに対する装置の長さ、並列での本数、間欠走行 か等速走行か等、プロセスの性質、費用対効率に基付く種々の組合せが考えられる 。この場合、本質的な課題はスループットであり、基本的には 1本のファイバーを出来 るだけ高速で等速走行させることである。何故なら、従来の平面基板では大面積に 亘つて一括してプロセスが進行する力 石英ファイバーの場合は、基本的には 1画素 単位で進行する。即ち、 1画素分の「点」が二次元平面をスキャンすることと同一であ るため、従来方式と同じスループットを実現するためには、一画素当りのプロセス時 間が非常に短くなり 3— 6桁の高速プロセスが必要となる。等速性は、前に述べた様 に、露光工程の様に走行する基板にパターンを形成する場合、同期をとるため、また は成膜、エッチングにおいても均一性を保持するために必要な装置特性である。この 方式では、製造装置もいわば「一次元化」されて非常に小型になり、従来の平面基板 のベースである気相プロセス力 液相に換えることにより高速ィ匕は実現可能と考えら れる。  [0024] As a first method, a fiber having a required length is wound around a winding jig, and the fiber coming out of the fiber passes through a device corresponding to the process and is wound around another winding jig. A basic production line configuration is possible. Equipment installed between two winding jigs, that is, the number of processes, the length of the equipment for one fiber, the number in parallel, whether it is intermittent or constant speed, etc. Various combinations are possible. In this case, the essential issue is throughput, and basically it is to run a single fiber at as high a speed as possible. This is because the conventional flat substrate has a force that allows the process to proceed over a large area, and in the case of quartz fiber, it basically proceeds in units of one pixel. In other words, since “dots” for one pixel are the same as scanning a two-dimensional plane, in order to achieve the same throughput as the conventional method, the process time per pixel becomes very short. A 6-digit high-speed process is required. As described above, the constant velocity is a device required to synchronize when a pattern is formed on a traveling substrate as in the exposure process, or to maintain uniformity in film formation and etching. It is a characteristic. In this system, the manufacturing equipment is also “one-dimensional” so that it becomes very small, and it is thought that high-speed processing can be realized by changing to the gas phase process force liquid phase which is the base of the conventional flat substrate.

[0025] 第二の方法は、上記一次元基板を適当な長さに切断してこれらを円筒または多角 柱表面に配列、固定しこれを基板として用いる力、または「すだれ状」にしていわゆる ローラ方式として用いるカ^、ずれかの方式である。前者は 、つてみれば平面基板を 筒状に丸めた構造であり、製造装置は平面基板に比べて大幅に縮小される。更にプ ロセス領域をファイバに対応した線状として、露光、蒸着源、イオン源、プラズマ源等 の集中系により装置の小型化と同時にプロセスレートを大幅に上げることが可能とな る。 [0025] In the second method, the one-dimensional substrate is cut into an appropriate length, and these are arranged and fixed on the surface of a cylinder or a polygonal column, and the force is used as a substrate, or a so-called interdigital shape. This is a method of displacement, which is used as a roller method. The former has a structure in which a flat substrate is rolled into a cylindrical shape, and the manufacturing apparatus is greatly reduced compared to a flat substrate. Furthermore, the process area can be made into a linear shape corresponding to the fiber, and the process rate can be significantly increased at the same time as downsizing of the apparatus by the concentrated system of exposure, vapor deposition source, ion source, plasma source and the like.

図面の簡単な説明 Brief Description of Drawings

[図 1]図 l(a),(b),(c)は、一次元基板の概念を示す図である。図 1(a)は具体的な例とし て断面四角(角は実際は丸まっている)の石英フアイ上に Si薄膜結晶が形成された SOI基板を示し、図 1(b)は具体的な例として円形断面の石英ファイバ上に ITO膜が形 成された ITO基板を示し、図 1(c)は、図 1(a)の S膿上に熱酸ィ匕膜が形成された構造を 示す。 [FIG. 1] FIGS. L (a), (b), and (c) are diagrams showing the concept of a one-dimensional substrate. Fig. 1 (a) shows an SOI substrate with a Si thin film crystal formed on a quartz fiber with a square cross section (the corners are actually round) as a specific example, and Fig. 1 (b) shows a specific example. An ITO substrate with an ITO film formed on a quartz fiber with a circular cross section is shown, and Fig. 1 (c) shows a structure in which a thermal oxide film is formed on S pus in Fig. 1 (a).

[図 2]図 2(a),(b)は、一次元基板によって構成された表示装置の概念を示す図である 。図 2(a)は画素駆動回路と配線を積層した角型ファイバと OLEDを形成し丸型フアイ バを複合した形態の鳥瞰図で、角型ファイバの下面にゲート線が接続されている。図 2(b)は当該表示面と外部駆動回路との接続を示す図である。  [FIG. 2] FIGS. 2 (a) and 2 (b) are diagrams showing a concept of a display device constituted by a one-dimensional substrate. Fig. 2 (a) is a bird's-eye view of a form in which a square fiber in which pixel drive circuits and wiring are stacked and an OLED is formed and a round fiber is combined. A gate line is connected to the lower surface of the square fiber. FIG. 2B shows the connection between the display surface and the external drive circuit.

[図 3]図 3(a),(b),(c)は、角型ファイバ上の画素駆動回路と配線の配置を示す図である 。図 3(a)は画素駆動回路、 OLEDファイバとの接続パッド、信号線、電流供給線の配 線を一辺から見た図で、配線はファイバ軸上連続であり、画素駆動回路、 OLEDファ ィバとの接続パッドは画素ピッチで同じパターンが繰り返されている。図 3(b)は角型フ アイバの断面図である。信号線、電流供給線の配線は最初の辺と直交する 2辺上を 走っている。図 3(c)は、図 3(a)と同じ辺で端子部での信号線、電流供給線の端子部を 示す。  [FIG. 3] FIGS. 3 (a), 3 (b), and 3 (c) are diagrams showing a pixel drive circuit and wiring arrangement on a square fiber. Fig. 3 (a) is a diagram of the pixel drive circuit, OLED fiber connection pad, signal line, and current supply line from one side. The wiring is continuous on the fiber axis, and the pixel drive circuit and OLED fiber are connected. The same pattern is repeated at the pixel pitch on the connection pad to the bar. Fig. 3 (b) is a cross-sectional view of a square fiber. The signal line and current supply line run on two sides orthogonal to the first side. Fig. 3 (c) shows the signal line at the terminal and the terminal of the current supply line on the same side as Fig. 3 (a).

[図 4]図 4(a),(b)は、丸型 OLEDファイバの構造を示す図である。図 4(a)はボトムェミツ シヨンタイプの断面図で OLEDは第三、第四象限に形成されており、第一、第二象限 から発光が出射する。図 4(b)はパッド方向を見た平面図である。  FIGS. 4 (a) and 4 (b) are diagrams showing the structure of a round OLED fiber. Fig. 4 (a) is a cross-sectional view of the bottom emission type. The OLED is formed in the third and fourth quadrants, and light is emitted from the first and second quadrants. Fig. 4 (b) is a plan view of the pad direction.

[図 5]図 5(a),(b)は、丸型フロントェミッションタイプ OLEDファイバの構造を示す図であ る。図 5(a)は断面図で、第一、第二象限に OLEDが形成されておりそこ力も発光が出 射する。図 5(b)は平面図である。 [図 6]図 6は、画素駆動回路図である。 [FIG. 5] FIGS. 5 (a) and 5 (b) are diagrams showing the structure of a round front emission type OLED fiber. Fig. 5 (a) is a cross-sectional view. OLEDs are formed in the first and second quadrants, and light is emitted from these forces. FIG. 5 (b) is a plan view. FIG. 6 is a pixel drive circuit diagram.

[図 7]図 7は、複合一次元基板によって構成された表示装置のラミネート構造を複合 ファイバに垂直な断面から見た図である。  [FIG. 7] FIG. 7 is a view of a laminate structure of a display device constituted by a composite one-dimensional substrate, as viewed from a cross section perpendicular to the composite fiber.

[図 8]図 8は、複合一次元基板によって構成された表示装置のラミネート構造を複合 ファイバに平行な断面から見た図で、特に端子付近の構成を示す図である。  [FIG. 8] FIG. 8 is a view of a laminate structure of a display device constituted by a composite one-dimensional substrate as seen from a cross section parallel to the composite fiber, and particularly shows a structure near a terminal.

圆 9]図 9(a),(b)は、酸ィ匕膜付きの SOI基板力も出発する TFTの工程フローを示す図で ある。 [9] FIGS. 9 (a) and 9 (b) are diagrams showing a TFT process flow that also starts the SOI substrate with an oxide film.

[図 10]図 10(a),(b)は、 ITO基板を用いたボトムェミッションタイプ OLEDの工程フロー を示す図である。  [FIG. 10] FIGS. 10 (a) and 10 (b) are diagrams showing a process flow of a bottom emission type OLED using an ITO substrate.

圆 11]図 l l(a),(b)は、金属膜付きのファイノから出発するフロントェミッションタイプ OLEDの工程フローを示す図である。 [11] FIGS. L l (a) and l (b) are diagrams showing a process flow of a front emission type OLED starting from a fino with a metal film.

圆 12]図 12は、一次元基板とこれを用いた表示装置の製造工程を示す図である。 12] FIG. 12 is a diagram showing a manufacturing process of a one-dimensional substrate and a display device using the same.

[図 13]図 13は、一次元基板である SOIファイバ、 ITOファイバ等を製造する装置の概 念を示す図である。 [FIG. 13] FIG. 13 is a view showing the concept of an apparatus for producing a one-dimensional substrate such as an SOI fiber or an ITO fiber.

[図 14]図 14(FIG.14)は、一次元基板をセグメント化し、これをプロセス用基板とする ために基板冶具面に配列させる装置の概念を示す図である。  [FIG. 14] FIG. 14 (FIG. 14) is a diagram showing a concept of an apparatus for segmenting a one-dimensional substrate and arranging it on a substrate jig surface in order to use it as a process substrate.

[図 15]図 15(a),(b),(c)は、セグメント化されたファイバを「プロセス基板」とする 3種類の 構成例を示す図である。図 15(a)は「基板冶具」が円筒ないしは円柱形で、この表面 にファイバが配列、固定される。図 15(b)は両端力 Sリング状の固定部で中間が抜けた 基板冶具、図 15(c)は各ファイバの両端がマイクロクランプのヘッドを持ちこれを連ね て「すだれ状」にしたプロセス基板を示す。  [FIG. 15] FIGS. 15 (a), (b), and (c) are diagrams showing three types of configuration examples in which a segmented fiber is a “process substrate”. In Fig. 15 (a), the “substrate jig” is cylindrical or columnar, and the fibers are arranged and fixed on this surface. Fig. 15 (b) shows the substrate jig with the middle part of the S-ring-shaped fixed part, and Fig. 15 (c) shows the process in which both ends of each fiber have a micro-clamp head and are connected to form an interdigital shape. The substrate is shown.

圆 16]図 16(a),(b),(c)は、円筒基板に対するこれら成膜、ドライエッチング、不純物ド ープ等の装置の原理を示す図である。図 16(a)はイオンクラスタビーム、金属溶射、 大気圧プラズマ等、収束ビーム状、乃至は集中プラズマ状態を用いる形式、図 16 (b)G),(b)(ii)は円筒型 CVD装置の 2つの形式を示す。図 16(C)G),(c)(ii)は、図 16 (b)G),(b)(ii)に対応するスパッタ装置の方式である。 16] FIGS. 16 (a), 16 (b), and 16 (c) are diagrams showing the principle of an apparatus for film formation, dry etching, impurity doping, etc. on a cylindrical substrate. Fig. 16 (a) shows a type using a focused beam or concentrated plasma state such as ion cluster beam, metal spray, atmospheric pressure plasma, etc. Fig. 16 (b) G), (b) and (ii) are cylindrical CVD devices. Two forms are shown. FIGS. 16 ( C ) G) and (c) (ii) show the sputtering system corresponding to FIGS. 16 (b) G) and (b) (ii).

[図 17]図 17は、レジスト、有機膜等を塗布する装置の原理を示す図である。  FIG. 17 is a view showing the principle of an apparatus for applying a resist, an organic film or the like.

[図 18]図 18(FIG.18)は、高精度露光機の原理を示す図である。 [図 19]図 19は、照明光学系の原理を示す図である。 [FIG. 18] FIG. 18 (FIG. 18) shows the principle of a high-precision exposure machine. FIG. 19 is a diagram showing the principle of the illumination optical system.

[図 20]図 20は、 1: 1プロキシミティ露光の光学系の原理を示す図である。  FIG. 20 is a diagram showing the principle of an optical system for 1: 1 proximity exposure.

[図 21]図 21(a),(b),(c)は、現像、剥離、ウエットエッチング、洗浄、等のウエットプロセス 方式の原理図を示す図である。図 21(a)は横型のウエット槽、図 21(b)は縦型のゥ ッ ト槽、図 21(c)はすだれ基板に適応するウエット方式を示す。  [FIG. 21] FIGS. 21 (a), (b), and (c) are diagrams showing the principle of a wet process system such as development, peeling, wet etching, and cleaning. Fig. 21 (a) shows a horizontal wet tank, Fig. 21 (b) shows a vertical wet tank, and Fig. 21 (c) shows a wet method applicable to a tin substrate.

[図 22]図 22(a),(b)は、 TFT,OLEDの複合ファイバを組み立てる原理を示す図である。 図 22(a)は円筒基板にバンプをデポする方式、図 22(b)は TFTファイバに OLEDフアイ バを接続する方法を示す。  FIGS. 22 (a) and 22 (b) are diagrams illustrating the principle of assembling a composite fiber of TFT and OLED. Fig. 22 (a) shows a method of depositing bumps on a cylindrical substrate, and Fig. 22 (b) shows a method of connecting OLED fibers to TFT fibers.

[図 23]図 23(a),(b)は、複合ファイバを配列してディスプレイパネルイ匕する方法を示す 図である。図 23(a)は配列するために枠を示す。図 23(b)は枠とファイバの位置関係を 示す。  [FIG. 23] FIGS. 23 (a) and 23 (b) are diagrams showing a method of arranging a composite fiber to display a display panel. Figure 23 (a) shows a frame for alignment. Figure 23 (b) shows the positional relationship between the frame and the fiber.

[図 24]図 24(a),(b)は、複合ファイバの配列にゲート線を取り付ける方法を示す図であ る。図 24(a)はゲート線配列のための枠を示す。図 24(b)は枠とゲート線の位置関係を 示す。  [FIG. 24] FIGS. 24 (a) and 24 (b) are diagrams showing a method of attaching a gate line to an array of composite fibers. FIG. 24 (a) shows a frame for gate line arrangement. Figure 24 (b) shows the positional relationship between the frame and the gate line.

[図 25]図 25は、マイクロウエルダの原理を示す図である。  FIG. 25 is a diagram showing the principle of a microwelder.

[図 26]図 26(a),(b)は、複合ファイバの配列に 2本の共通線を取り付ける方法を示す図 である。図 26(a)は共通線配列のための枠を示す。図 26(b)は枠と共通線の位置関係 を示す。  [FIG. 26] FIGS. 26 (a) and 26 (b) are diagrams showing a method of attaching two common wires to an array of composite fibers. Figure 26 (a) shows a frame for common line arrangement. Figure 26 (b) shows the positional relationship between the frame and the common line.

符号の説明 Explanation of symbols

10:角断面石英ファイバ、 10 ':丸型断面石英ファイバ、 11: Si薄膜結晶、 11 ': ITO 、 12:熱酸化膜、 20:TFTファイノく、 21:OLEDファイノく、 25,25': FPCまたは PCB、 2 6,26':外部駆動回路等、 31:画素駆動回路、 32 :OLEDファイバへの接続パッド、 3 3:信号線、 34:電流供給線、 35:ゲート線接続パッド、 36:信号線端子、 37:電流供 給線端子、 41:ITO、 42:OLED層、 43:陰極電極、 44:透明有機保護膜、 45:ITO 補強線、 46:TFT基板への接続パッド、 50:石英ファイノく、 51:下地電極、 52:陰極、 53:有機 EL層、 54:ITO、 55:無機パッシベーシヨン膜、 56:ΙΤΟ補強電極、 57:透明 有機保護膜、 58:パッド、 60:画素駆動回路、 61:ΙΤΟ共通電極、 62:有機 EL層、 63 :陰極、 64:共通電極線(ΙΤΟ補強電極)、 65:TFTファイバー OLEDファイバ接続パッ ド、 66:信号線、 67:電流供給線、 68:ゲート線、 70:TFTファイノく、 71:OLEDフアイ ノ 、 72:ゲート線、 73:共通線、 74:黒色榭脂、 75:透明榭脂、 76、 76,:バリヤフィル ム、 80:TFTファイノく、 81:OLEDファイノく、 82:ゲート線、 83、 83':共通線、 84:黒 色榭脂、 85:透明榭脂、 86、 86':バリヤフィルム、 87、 87':外部駆動 IC等搭載 TAB または FPC、 88、 88,: PCBまたはフレーム、 90:薄膜 Si結晶、 91:ゲート酸化膜、 93 :ゲート電極、 941:ソース、 942:ドレイン、 951、 952:LDD、 961- 963:スルーホー ル、 971- 973:コンタクトおよび配線、 98:第二層間絶縁膜、 991- 993:コンタクト及 び配線、 100:石英ファイノく、 101:ITO、 102:ΙΤΟ補強電極、 103:有機 EL層、 104 :陰極、 105:透明有機保護膜、 106:パッド、 110:石英ファイノく、 111:下地電極、 1 12:ΙΤΟ補強電極、 113:無機パッシベーシヨン膜、 114:陰極、 115:有機5し層、 11 6:ΙΤΟ、 117:透明有機保護膜、 118:パッド、 131:石英ファイバ線引き部、 132:Si、 ITO等膜形成部、 133:レジスト保護膜塗布部、 134:乾燥部、 135:卷取り機構、 14 1:一次元基板リール、 142:—次元基板、 143:レジスト剥離、 144:ファイバセグメン ト化ヘッド、 145:基板冶具、 146:ファイバ走行調節、 151:セグメント化一次元基板 、 152:円筒、円柱基板冶具、 153、 153':固定リング、 154:支柱、 155:マイクロクラ ンプ、 156:マイクロチェイン、 160:真空チャンノ 、 161:円筒乃至円柱型基板、 162 :プロセスヘッド、 163:回転機構、 164:円筒型 CVD、ドライエッチ、プラズマドープ装 置、 165:円筒型 CVD、ドライエッチ、プラズマドープ装置 (基板冶具と兼用)、 166: 円筒型スパッタ、ドライエッチ、プラズマドープ装置、 167:ターゲット乃至電極、 168: 円筒型スパッタ、ドライエッチ、プラズマドープ装置 (基板冶具と兼用型)のターゲット 乃至電極、 170:円筒乃至は円柱基板、 171:レジストまたは榭脂滴下冶具、 172:回 転機構、 180:円筒基板、 181:回転、移動機構、 182:縮小投影結像レンズ、 183: マスクホールダおよびレンズサーボ制御機構、 184:照明光学系、 185:エキシマレ 一ザ一、 186:ファイバ位置検出ヘッド、 187:信号転送、 188:信号処理、サーボ制 御用コンピュータ、 189:サーボ制御データ転送、 190:平行化エキシマビーム、 191 ,192:分割レンズ、 193:二次光源、 194:コンデンサレンズ、 195:フィールドレンズ、 196:マスク、 197:結像レンズ、 198:入射瞳、 199:結像面、 201 :SOIファイノく、 20 2:円筒レンズ、 203:マスク、 204:均一化エキシマビーム、 211:円筒乃至円柱基板 、 212:横型槽、 213:搬送、回転機構、 214:縦型槽、 215:すだれ状基板、 216:横 型槽、 217-1-3:回転、搬送機構、 221:円筒乃至円柱基板、 222:回転、移動機構 、 223:TFTファイノく、 224:インクジェットヘッド、 225:OLEDファイノく、 226:TFTファ ィバ、 227:ファイバ保持、位置決め、固定冶具、 231:複合ファイバ、 232:複合ファ ィバ固定枠、 233:OLEDファイノく、 234:TFTファイノく、 235:固定枠一部、 241:ゲ ート線固定枠、 242:OLEDファイノく、 243:TFTファイノく、 244:ゲート線、 245:複合 ファイバ固定枠一部、 246:ゲート線固定枠一部、 251:ゲート線、 252 :TFTファイバ 、 253:マイクロウエルダヘッド、 254:台形反射鏡、 255:平面反射鏡、 256:集光レ ンズ、 257:YAGレーザー光、 258:ノ ンプ、 261:共通線固定枠、 263:共通線、 26 4:OLEDファイノく、 265:TFTファイノく、 266:共通線固定枠一部。 10: Square cross-section silica fiber, 10 ': Round cross-section silica fiber, 11: Si thin film crystal, 11': ITO, 12: Thermal oxide film, 20: TFT fino, 21: OLED fino, 25,25 ': FPC or PCB, 2 6,26 ': External drive circuit, etc. 31: Pixel drive circuit, 32: Connection pad to OLED fiber, 3 3: Signal line, 34: Current supply line, 35: Gate line connection pad, 36 : Signal line terminal, 37: Current supply line terminal, 41: ITO, 42: OLED layer, 43: Cathode electrode, 44: Transparent organic protective film, 45: ITO reinforcing wire, 46: Connection pad to TFT substrate, 50 : Quartz fino, 51: Base electrode, 52: Cathode, 53: Organic EL layer, 54: ITO, 55: Inorganic passivation film, 56: Reinforcement electrode, 57: Transparent organic protective film, 58: Pad, 60: Pixel Drive circuit, 61: Common electrode, 62: Organic EL layer, 63: Cathode, 64: Common electrode wire (Reinforcement electrode), 65: TFT fiber OLED fiber connection pad , 66: Signal line, 67: Current supply line, 68: Gate line, 70: TFT fine, 71: OLED fibre, 72: Gate line, 73: Common line, 74: Black grease, 75: Transparent Oil: 76, 76 ,: Barrier film, 80: TFT fine, 81: OLED fine, 82: Gate wire, 83, 83 ': Common wire, 84: Black colored oil, 85: Transparent grease, 86, 86 ': Barrier film, 87, 87': External drive IC, etc. TAB or FPC, 88, 88 ,: PCB or frame, 90: Thin film Si crystal, 91: Gate oxide film, 93: Gate electrode, 941: Source, 942: Drain, 951, 952: LDD, 961-963: Through hole, 971-973: Contact and wiring, 98: Second interlayer insulating film, 991- 993: Contact and wiring, 100: Quartz fine plate, 101: ITO, 102: ΙΤΟ Reinforcing electrode, 103: Organic EL layer, 104: Cathode, 105: Transparent organic protective film, 106: Pad, 110: Quartz fine electrode, 111: Base electrode, 1 12: ΙΤΟ reinforcing electrode, 113: None Passivation film, 114: Cathode, 115: Organic 5 layer, 11 6: ΙΤΟ, 117: Transparent organic protective film, 118: Pad, 131: Quartz fiber drawing part, 132: Film formation part such as Si, ITO, 133: Resist protective film coating section, 134: Drying section, 135: Stripping mechanism, 14 1: One-dimensional substrate reel, 142: —Dimensional substrate, 143: Resist stripping, 144: Fiber segmentation head, 145: Substrate jig, 146 : Fiber travel adjustment, 151: Segmented one-dimensional substrate, 152: Cylindrical and cylindrical substrate jig, 153, 153 ': Fixing ring, 154: Support, 155: Micro clamp, 156: Micro chain, 160: Vacuum channel, 161 : Cylindrical or cylindrical substrate, 162: Process head, 163: Rotating mechanism, 164: Cylindrical CVD, dry etching, plasma doping apparatus, 165: Cylindrical CVD, dry etching, plasma doping apparatus (also used as substrate jig), 166: Cylindrical sputtering, dry etch, plasma dough 167: Target or electrode, 168: Cylindrical sputtering, dry etching, plasma doping apparatus (also used as substrate jig) target or electrode, 170: Cylindrical or cylindrical substrate, 171: Resist or grease dropping jig, 172: Rotation mechanism, 180: Cylindrical substrate, 181: Rotation, movement mechanism, 182: Reduction projection imaging lens, 183: Mask holder and lens servo control mechanism, 184: Illumination optical system, 185: Excimerizer, 186 : Fiber position detection head, 187: Signal transfer, 188: Signal processing, servo control computer, 189: Servo control data transfer, 190: Parallelized excimer beam, 191, 192: Split lens, 193: Secondary light source, 194: Condenser lens, 195: Field lens, 196: Mask, 197: Imaging lens, 198: Entrance pupil, 199: Imaging plane, 201: SOI fino, 20 2: Cylindrical lens, 203: Mask, 204: Uniform excimer Beam, 211: cylinder Itaru cylindrical substrate 212: Horizontal tank, 213: Transport and rotation mechanism, 214: Vertical tank, 215: Interdigital substrate, 216: Horizontal tank, 217-1-3: Rotation, transfer mechanism, 221: Cylindrical or cylindrical substrate, 222 : Rotating and moving mechanism, 223: TFT fiber, 224: Inkjet head, 225: OLED fiber, 226: TFT fiber, 227: Fiber holding, positioning, fixing jig, 231: Composite fiber, 232: Composite fiber 234: OLED Fino, 234: TFT Fino, 235: Part of fixed frame, 241: Gate line fixed frame, 242: OLED Fino, 243: TFT Fino, 244: Gate line, 245 : Composite fiber fixed frame part, 246: Gate line fixed frame part, 251: Gate line, 252: TFT fiber, 253: Microwelder head, 254: Trapezoidal reflector, 255: Planar reflector, 256: Condenser 257: YAG laser light, 258: Knob, 261: Common line fixed frame, 263: Common line, 26 4: OLED Fino, 265: TFT Fino, 266: Through line fixed frame part.

発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION

[0028] 以下、図面によって本発明に係る実施形態を説明する。図 l(a),(b)ズ c)に石英フアイ バを基材とする一次元基板の概念図を示す。  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. Figures l (a), (b) and c) show a conceptual diagram of a one-dimensional substrate based on quartz fiber.

[0029] 図 l(a),(b),(c)において、符号 10、 10'は石英ファイバで、光ファイバの線引き工程と 同一の方法で作成される。図 l(a),(b)にそれぞれ円形、正方形の断面を例として示し ているが、用途に応じて楕円、矩形、チューブ状を取り得る。ファイバの直径、または 一辺の大きさはファイバの巻き取りが可能な 800 m以下とする。符号 11は Siの単結 晶または多結晶膜で、これを SOIファイバと称するが、この場合の Si膜の厚みは 100 應程度である。図 1(c)において、符号 12は、 Siの表面に形成された熱酸化膜等の 酸化膜である。第二の範疇の一次元基板は図 l(a),(b)において Siの代わりに厚さ 10 0應程度の ITO、酸化亜鉛、酸ィ匕錫等の透明電極が形成されたものである。但しこの 場合は、 Si膜を形成するほどの高温は必要ないので、石英の代わりに多成分ガラス やプラスチック基材、その他の透明絶縁材料も用いることが出来る。  In FIGS. L (a), (b), and (c), reference numerals 10 and 10 ′ denote quartz fibers, which are produced by the same method as the optical fiber drawing process. Figures l (a) and (b) show examples of circular and square cross-sections, respectively, but they can be oval, rectangular, or tube-shaped depending on the application. The diameter of the fiber or the size of one side shall be 800 m or less where the fiber can be wound. Reference numeral 11 denotes a single crystal or polycrystalline film of Si, which is called an SOI fiber. In this case, the thickness of the Si film is about 100 mm. In FIG. 1 (c), reference numeral 12 denotes an oxide film such as a thermal oxide film formed on the surface of Si. The one-dimensional substrate in the second category is the one in which transparent electrodes such as ITO, zinc oxide, and oxide tin with a thickness of about 100 ° are formed instead of Si in Figs. L (a) and (b). . However, in this case, high temperatures are not required to form the Si film, so that multi-component glass, plastic substrates, and other transparent insulating materials can be used instead of quartz.

[0030] 図 2(a)に画素駆動回路と配線が構成された角型の SOIファイバ 20と複数の有機 LEDが形成された丸型の ITOファイバ 21— 23とを有する複合一次元基板による TFT-OLEDの構成の概念を示す。 RGB (赤、緑、青)それぞれの画素列が形成され た複数の ITOファイバ 21、 22、 23を画素ピッチに従い配列し、これに直交してゲート 線 24が接続されている。各線の端部は、図 2(b)に示す様に配線ボード (PCB: Printed Circuit Boad) 25,25'上に固定され、ボード上に実装された駆動ドライバ IC チップ 26,26'と接続される。例えば、第 1の ITOファイバ 21には複数の赤の画素(有 機 LED)が複数個一列に形成され、第 2の ITOファイバ 22には複数の緑の画素が複 数個一列に形成され、第 3の ITOファイバ 23には複数の赤の画素が複数個一列に形 成されている。 [0030] FIG. 2 (a) shows a TFT with a composite one-dimensional substrate having a rectangular SOI fiber 20 with a pixel drive circuit and wiring and round ITO fibers 21-23 formed with a plurality of organic LEDs. -Shows the concept of OLED configuration. A plurality of ITO fibers 21, 22, and 23 in which RGB (red, green, and blue) pixel rows are formed are arranged in accordance with the pixel pitch, and a gate line 24 is connected orthogonally thereto. The end of each wire is connected to a wiring board (PCB: Printed Circuit Boad) Fixed to 25,25 'and connected to the driver IC chip 26,26' mounted on the board. For example, a plurality of red pixels (organic LEDs) are formed in a row in the first ITO fiber 21, and a plurality of green pixels are formed in a row in the second ITO fiber 22. The third ITO fiber 23 has a plurality of red pixels formed in a row.

[0031] 画素駆動回路と配線が構成された角型の SOIファイバの断面図を図 3(a)に、その平 面図を図 3(b)、(c)に示す。一面 (A)に有機 EL (electroluminescence)画素の駆動スイツ チ回路 31が形成されている。また、同一面内に有機 LEDとの接続端子 32及び信号 線 33の一部と電流源線 34の一部がかかり、各々が駆動スィッチ回路 31に接続され ている。信号線 33と電流源線 34は、それぞれ一面 (A)と直交する面 (B)、(C)を通って 面 (A)に対向する面 (D)の一部にかかり、ファイバの長手方向全体に延びている。図 3 (c)は辺 (D)のファイバ端子付近の構成を示すもので、 35はゲート線用のノッド、 36、 37は信号線、電流源線の端子部パッドである。なお、駆動スィッチ回路 31は MOSト ランジスタ等の能動素子力 構成されて 、る。  [0031] Fig. 3 (a) shows a cross-sectional view of a rectangular SOI fiber in which a pixel drive circuit and wiring are configured, and Figs. 3 (b) and 3 (c) show its plan views. On one side (A), an organic EL (electroluminescence) pixel drive switch circuit 31 is formed. In addition, a connection terminal 32 and a part of the signal line 33 and a part of the current source line 34 are connected to the organic LED in the same plane, and each is connected to the drive switch circuit 31. The signal line 33 and the current source line 34 are applied to a part of the surface (D) passing through the surface (B) and (C) orthogonal to the surface (A) and facing the surface (A), respectively, and the longitudinal direction of the fiber. It extends throughout. Fig. 3 (c) shows the configuration near the fiber terminal on side (D), 35 is a gate line node, and 36 and 37 are signal line and current source line terminal pads. The drive switch circuit 31 is composed of an active element such as a MOS transistor.

[0032] 丸型の IT0ファイバの断面図を図 4(a)に示し、これを図下部から見た平面図を図 4 (b)に示す。これはいわゆるボトムェミッション型の有機 LEDの構成で、石英またはプラ スチックのファイバ 40表面に成膜された IT0膜 41上に有機 EL膜 42を積層し、この上 に画素ごとに分離された陰極金属膜 43を形成する。有機 LEDは図 4(a)の第 3及び第 4象限 (図の下半分)内に収まるように形成され、発光は第 1、第 2象限 (図の上半分) 力も出射される。保護膜 44を貫通して SOIファイバと接続するパッド 46が各画素ごと に形成されている。 ITOの抵抗値を補強するために金属電極 45がファイバ長手方向 に OLED、出射面と干渉しない部分に形成され、大型画面にも対応出来る様になつ ている。  [0032] A cross-sectional view of the round IT0 fiber is shown in Fig. 4 (a), and a plan view of the round IT0 fiber viewed from the bottom of the figure is shown in Fig. 4 (b). This is a so-called bottom emission type organic LED configuration, in which an organic EL film 42 is stacked on an IT0 film 41 formed on the surface of a quartz or plastic fiber 40, and a cathode separated for each pixel. A metal film 43 is formed. The organic LED is formed so that it falls within the third and fourth quadrants (lower half of the figure) in Fig. 4 (a), and light is emitted from the first and second quadrants (upper half of the figure). A pad 46 that penetrates the protective film 44 and is connected to the SOI fiber is formed for each pixel. In order to reinforce the resistance value of ITO, the metal electrode 45 is formed in the OLED in the longitudinal direction of the fiber and the part that does not interfere with the exit surface, so that it can be used for large screens.

[0033] 上記方式の他にいわゆるフロントェミッション型の有機 LED方式があり、この断面と 平面図を図 5(a),(b)に示す。石英またはプラスチックのファイバ 50の表面に画素ごと に分離された下地金属膜 51と陰極金属膜 52が形成されており、発光面を除く部分 に絶縁層 55が形成されている。有機 EL層 53は図 5(a)の第 1及び第 2象限内に収ま るように形成され、この上に全面電極である ITO膜 54が形成される。下地金属膜 51 は第 3及び第 4象限内にまで延びており絶縁層 55と保護膜 57を貫通して SOIフアイ ノ と接続するパッド 58が各画素ごとに形成されている。 ITO補強電極 56はパッド 58と 発光面を除 、た領域に形成されて 、る。 In addition to the above method, there is a so-called front emission type organic LED method, and its cross section and plan view are shown in FIGS. 5 (a) and 5 (b). A base metal film 51 and a cathode metal film 52 separated for each pixel are formed on the surface of a quartz or plastic fiber 50, and an insulating layer 55 is formed on a portion excluding the light emitting surface. The organic EL layer 53 is formed so as to be within the first and second quadrants of FIG. 5 (a), and an ITO film 54 serving as a full-surface electrode is formed thereon. Underlying metal film 51 Extends to the third and fourth quadrants, and pads 58 are formed for each pixel through the insulating layer 55 and the protective film 57 and connected to the SOI fibre. The ITO reinforcing electrode 56 is formed in a region excluding the pad 58 and the light emitting surface.

[0034] 上記有機 EL積層構造として、 2— 6層の構成が用いられる。各色の構成と材料は次 の通りである。 [0034] As the organic EL laminated structure, a 2-6 layer structure is used. The composition and materials of each color are as follows.

[0035] 図 6はファイバ TFT- OLEDの等価回路の一例を示す。図 6において符号 60が図 3 の 31に対応する画素駆動回路、 61が有機 LEDの ITO電極、 62力有機 EL層、 63が 陰極電極、 64が ITOと補強電極を含めた共通線、 65が SOIファイバと接合するバン プである。 61— 65が OLEDファイバに対応する。 66は信号線、 67は電流源線であり 60、 66、 67が SOIファイバに対応する。 68が外付けのゲート線である。  FIG. 6 shows an example of an equivalent circuit of a fiber TFT-OLED. In FIG. 6, reference numeral 60 is a pixel driving circuit corresponding to 31 in FIG. 3, 61 is an ITO electrode of an organic LED, 62 force organic EL layer, 63 is a cathode electrode, 64 is a common line including ITO and a reinforcing electrode, 65 is Bump that joins SOI fiber. 61—65 corresponds to OLED fiber. 66 is a signal line, 67 is a current source line, and 60, 66, and 67 correspond to SOI fibers. 68 is an external gate line.

[0036] 図 7はファイバ TFT- OLED構造においてファイバに垂直方向の断面図である。 SOI ファイバ 70と OLEDファイバ 71の複合線の各々はディスプレイの垂直方向、即ち列方 向 RGBの画素列に対応している。ゲート線 72は各画素に接続されている力 外付け 共通線 73は画面の端部のみ 1ないし 2本で良い。これは ITO共通電極に金属の補強 電極を取り付けてある力もである。 70— 73で構成されたファイバの網を OLEDフアイ バの発光部の下部に黒色の絶縁レジン 74を、上部を透明レジン 75でラミネートし、 更に有機 ELの保護の為に、水分、酸素等に対するノリャフィルム 76、 76'を重ねる。  FIG. 7 is a cross-sectional view perpendicular to the fiber in the fiber TFT-OLED structure. Each of the composite lines of the SOI fiber 70 and the OLED fiber 71 corresponds to an RGB pixel column in the vertical direction of the display, that is, in the column direction. The gate line 72 is connected to each pixel. The external common line 73 may be one or two at the edge of the screen. This is also the force of attaching a metal reinforcing electrode to the ITO common electrode. A fiber network composed of 70-73 is laminated with a black insulating resin 74 on the lower part of the light emitting part of the OLED fiber and a transparent resin 75 on the upper part. Furthermore, for protection of organic EL, it is against moisture, oxygen, etc. Overlay Nolla film 76, 76 '.

[0037] 図 8はファイバ TFT-OLED構造においてファイバに平行方向の断面図で、特に端 子部近辺の構成を示す。 SOIファイノく 80と OLEDファイバ 81からなる複合 TFT- OLED ファイバに直交してゲート線 82が各画素に接続されている。 OLEDの共通電極を繋ぐ 共通線 83, 83'は画面端部のみでよい。各ファイバ上の信号線と電流供給線は外部 回路へ接続される。ここでは駆動 ICの載った TABないしは中継用の FPC87と PCB88 が接続されている。ゲート線 82、共通線 83, 83,のさらに外側にはノリャフィルム 86 、 86'が配置される。  [0037] FIG. 8 is a cross-sectional view in the direction parallel to the fiber in the fiber TFT-OLED structure, and particularly shows the configuration near the terminal portion. A gate line 82 is connected to each pixel orthogonal to a composite TFT-OLED fiber consisting of SOI fine 80 and OLED fiber 81. The common lines 83 and 83 'that connect the common electrodes of the OLEDs need only be at the screen edges. The signal line and current supply line on each fiber are connected to an external circuit. Here, FPC87 and PCB88 for TAB or relay with driver IC are connected. On the outer side of the gate line 82 and the common lines 83 and 83, NORA films 86 and 86 'are arranged.

[0038] 以上の表示装置では、 SOIファイバ 20上に形成された MOS型トランジスタ素子等か らカもなる画素駆動回路 31を形成した一次元基板と、 ITOファイバ 21— 23上に形成 された有機 LED画素からなる一次元基板とを、対応する各画素で互いに結合して複 合一次元基盤が構成される。この複合一次元基板が表示面の一列を構成する。 [0039] さらに、ファイバー上の一端力 各画素に外部力 画像信号を導入するためにファ ィバーの長手方向に走る線状導体の信号線 33、並びに各画素を構成する有機 LED 42, 53に注入する電流を供給する線状導体の電流供給源 34が同一の SOIファイバ 20に形成されている。 [0038] In the above display device, a one-dimensional substrate on which a pixel driving circuit 31 is formed from a MOS transistor element or the like formed on an SOI fiber 20 and an organic material formed on an ITO fiber 21-23. A one-dimensional substrate composed of LED pixels is coupled to each other at each corresponding pixel to form a composite one-dimensional substrate. This composite one-dimensional substrate constitutes one row of the display surface. [0039] Furthermore, one end force on the fiber is injected into the linear conductor signal line 33 running in the longitudinal direction of the fiber and the organic LEDs 42 and 53 constituting each pixel in order to introduce an external force image signal to each pixel. A linear conductor current supply source 34 for supplying a current to be generated is formed in the same SOI fiber 20.

[0040] これら複合ファイバー 20— 23を表示画面の列数に必要な本数を画面水平方向画 素ピッチに対応して規則的に配列し、これらに直交して画素表示のタイミング等の信 号を画素駆動回路 31に導入する線状導体のゲート線 24を SOIファイバ 20に接続す る。また、有機 LED42, 53を備えた ITOファイバ 21— 23の発光出射面である透明電 極 41, 54を共通に接続する共通電極線 61を接続する。  [0040] The number of these composite fibers 20-23 required for the number of columns on the display screen is regularly arranged in correspondence with the pixel pitch in the horizontal direction of the screen, and signals such as pixel display timing are orthogonal to these. A gate line 24 of a linear conductor introduced into the pixel drive circuit 31 is connected to the SOI fiber 20. In addition, a common electrode line 61 that connects the transparent electrodes 41 and 54 that are the light emission and emission surfaces of the ITO fibers 21 to 23 including the organic LEDs 42 and 53 is connected.

[0041] これらファイバー 20上の信号線 33、ゲート線 24の端部に画素を駆動するための信 号、乃至制御信号を印加する外部駆動回路 26, 26'を、各電流供給源 34に共通の 電流源を接続し、各共通電極線 61に同電位源を各々接続する。このように構成され た網目全体を剛性乃至は可撓性を有する透明有機榭脂等を発光側に、黒色有機榭 脂等を反対側に装着して両者で上記網目画面を保護し、これにより厚み 3mm以下に 平板化した TFT-有機 LED発光型表示装置が構成される。なお、 SOIファイバ 20の代 わりに酸ィ匕膜付 SOIファイバを用いてもょ 、。  [0041] External drive circuits 26 and 26 'for applying a signal or a control signal for driving a pixel to the ends of the signal line 33 and gate line 24 on the fiber 20 are common to each current supply source 34. The same potential source is connected to each common electrode line 61. The entire mesh thus configured is attached to the light emitting side with a rigid or flexible transparent organic resin or the like on the opposite side, and the black organic resin or the like is attached to the opposite side to protect the above mesh screen. A flat-panel TFT-organic LED light-emitting display with a thickness of 3 mm or less is constructed. In place of SOI fiber 20, use an SOI fiber with an oxide film.

[0042] 図 9(a),(b)は酸ィ匕膜附きの SOIファイバを用いた場合の TFT工程の一例を示す図で ある。まず、図 9(a),(b)のステップ(1—3)に示すように、酸ィ匕膜 91を含めてシリコン膜 9 0のアイランドを形成する。図 6の画素駆動回路を 0.5 mの設計ルールで全て n-チ ャネルとし、 L/W=2/2 mとした場合のレイアウトした場合、回路部分の面積は 28x2 4 μ mである。これ以外の種々回路方式をとるとしても、アイランドの面積は 50 μ mD あれば十分である。  [0042] FIGS. 9 (a) and 9 (b) are diagrams showing an example of a TFT process when an SOI fiber with an oxide film is used. First, as shown in step (1-3) of FIGS. 9A and 9B, an island of the silicon film 90 including the oxide film 91 is formed. When the pixel drive circuit in Fig. 6 is all n-channel with 0.5 m design rule and L / W = 2/2 m, the circuit area is 28x2 4 μm. Even if various other circuit methods are used, an area of 50 μmD is sufficient.

[0043] 次に、図 9(a),(b)のステップ (4 6)、(7— 10)に示すように、シリコン膜 90の側面をプ ラズマ酸化、熱酸化、酸化膜成膜等の手段により酸化膜で覆い、ゲート電極 93を酸 化膜の上に形成する。ゲート電極 93としては金属タンングステン、タングステンシリサ イド等を用いた。続いて、図9(&),0))のステップ(11—18)に示すように、 n-チャネル TFTに於いてソース、ドレイン領域 941, 942は幅 1 μ m程度の LDD (Lightly Doped Drain)領域 95持つ構造を形成する。不純物導入はまず低濃度でイオン打ち込みを 行い、次いで、ゲート電極 93端部に力かるレジスト膜厚を 1 μ mになる様調節して高 濃度の打ち込みを行った。不純物導入の別の方法として、ソース、ドレイン領域に対 応した面積で酸ィ匕膜の窓をあけて、プラズマドーピングによりまず低濃度のイオン導 入を行い、次いで上記と同様、ゲート電極 93端部に力かるレジスト膜厚を 1 μ mにな る様調節してプラズマドーピングにより高濃度のイオン導入を行った。 Next, as shown in steps (4 6) and (7-10) of FIGS. 9 (a) and 9 (b), the side surface of the silicon film 90 is plasma oxidized, thermal oxidized, oxide film formed, etc. Thus, the gate electrode 93 is formed on the oxide film by covering with an oxide film. As the gate electrode 93, metal tongue tungsten, tungsten silicide or the like was used. Next, as shown in step (11-18) of Fig. 9 (&), 0)), the source and drain regions 941 and 942 in the n-channel TFT have LDD (Lightly Doped Drain) width of about 1 μm. ) A structure having region 95 is formed. Impurities are introduced at a low concentration first. Next, the resist film thickness applied to the edge of the gate electrode 93 was adjusted to 1 μm, and high concentration implantation was performed. As another method for introducing impurities, an oxide film window is opened in an area corresponding to the source and drain regions, and low concentration ion implantation is first performed by plasma doping. A high concentration of ions was introduced by plasma doping while adjusting the resist film thickness to 1 μm.

[0044] いずれの方式に於いても、その後に図 9(a),(b)のステップ(19—22)、 (23— 28)〖こ示 すように、第一層間絶縁膜 96を成膜、これにスルーホール 961, 962,963を開けてソ ース、ゲート、ドレイン各々の配線 971, 972, 973を形成した。この際バリヤメタルと して Tiを用い、配線用金属として A1を用いた。この段階で画素駆動回路内の各素子 接続間の接続用配線と、信号線及び電流供給線への回路力ゝらの配線の一部を形成 する。 [0044] In either method, after that, as shown in steps (19-22) and (23-28) of FIGS. 9 (a) and 9 (b), the first interlayer insulating film 96 is formed. Films were formed and through holes 961, 962,963 were opened to form wirings 971, 972, and 973 for the source, gate, and drain, respectively. At this time, Ti was used as the barrier metal and A1 was used as the wiring metal. At this stage, a part of the wiring for connecting each element in the pixel driving circuit and a part of the wiring for the signal line and the current supply line are formed.

[0045] 更に、図 9(a),(b)のステップ(29—31)、(32— 39)に示すように、第二層間絶縁膜 98 を成膜、前記画素駆動回路とゲート用パッドへの接続の一部と回路ない配線 991一 993を行った。次にファイバの側面に配線用 A1の成膜を行い、配線パターンと回路と の接続を完成させ、次いで再度第二層間絶縁膜を側面に形成して、 A1を成膜、バタ ーン形成を行いゲート用パッドへの接続を完成させる。  Furthermore, as shown in steps (29-31) and (32-39) of FIGS. 9 (a) and 9 (b), a second interlayer insulating film 98 is formed, and the pixel driving circuit and gate pad are formed. Some connections to the circuit and no wiring 991 993 made. Next, deposit A1 for wiring on the side of the fiber, complete the connection between the wiring pattern and the circuit, and then form a second interlayer insulating film on the side again to form A1 and form a pattern. To complete the connection to the gate pad.

[0046] 一方の OLEDファイバの工程図(断面図)を図 10(a),(b)に示す。方式はボトムェミツ シヨンである。図 10(a),(b)のステップ(1)に示すように出発点の 1次元基板は ITO膜 1 01があらかじめ成膜されたいわゆる ITOファイバである。これに A1補強線 102をマスク 成膜、またはレジストリフトオフにより形成した。図の断面を X-Y座標で表した場合の 第一、第二象限が EL発光の出射面であり、図 10(a),(b)のステップ(2— 4)に示すよう に、 EL層 103は第三、第四象限に形成される。それから図 10(a),(b)のステップ(5)に 示すように EL層 103上の陰極金属電極 104は画素ごとに分離されておりマスク蒸着 で形成される。さらに、図 10(a),(b)のステップ(6—9)に示すように、これら全体に透明 な感光性榭脂 105を塗布、陰極へのスルーホールを除いて露光 '硬化する。未露光 部分は現像によりスルーホールとなり、ここに低融点半田、導電性接着剤等 106をィ ンクジェット、デイスペンサ等の手段で充填し、 SOIファイバとの接続パッドとする。  [0046] Process diagrams (cross-sectional views) of one OLED fiber are shown in Figs. 10 (a) and 10 (b). The method is bottom emission. As shown in step (1) of FIGS. 10 (a) and 10 (b), the starting one-dimensional substrate is a so-called ITO fiber on which an ITO film 101 is formed in advance. A1 reinforcement wire 102 was formed on this by mask film formation or registry shift-off. The first and second quadrants when the cross-section of the figure is represented by the XY coordinates are the EL light emission surfaces. As shown in steps (2-4) of Figs. 10 (a) and 10 (b), the EL layer 103 Are formed in the third and fourth quadrants. Then, as shown in step (5) of FIGS. 10 (a) and 10 (b), the cathode metal electrode 104 on the EL layer 103 is separated for each pixel and is formed by mask deposition. Further, as shown in steps (6-9) of FIGS. 10 (a) and 10 (b), a transparent photosensitive resin 105 is applied to all of them, and exposed and cured except for through-holes to the cathode. The unexposed part becomes a through hole by development, and is filled with low melting point solder, conductive adhesive, etc. 106 by means such as ink jet, dispenser, etc., and used as a connection pad with SOI fiber.

[0047] 図 l l(a),(b)はフロントェミッション方式の OLEDファイバの工程図である。図 l l(a),(b) のステップ(1 6)、 (7— 8)に示すように、一次元基板金属膜ファイバ 110上の金属膜 を画素単位の下地電極および SOI基板への接続端子としてパターン 111を形成、次 いで当該端子部を含む発光部と逆の半円部に絶縁膜 113を形成する。この絶縁膜 のパターン形成時に下地金属の端子に対するスルーホールも同時に形成しておく。 次に当該絶縁膜上に端子部と重ならない様に金属の ITO補強電極 112を形成する 力 この時金属膜の一部はスルーホールを介して下地端子電極との接続端子を絶縁 膜 113上に形成する。次いで、図 l l(a),(b)のステップ(19)、 (20— 23)、 (25)に示す ように、陰極電極 114、有機 EL層 115は下半円に力からない様、 IT0116は補強電 極と接触する様マスク蒸着し OLED部を形成する。これら全体を図 1 l(a),(b)のステツ プ(26)に示すように感光性透明榭脂 117で被覆し、上記接続端子を除いて光硬化 し、端子部は現像によりスルーホールを形成、ここにインクジェット、デイスペンサ等の 手段により SOI基板との接続バンプを形成する。 FIGS. Ll (a) and (b) are process diagrams of a front emission type OLED fiber. Fig.ll (a), (b) As shown in steps (16) and (7-8), the pattern 111 is formed by using the metal film on the one-dimensional substrate metal film fiber 110 as the connection terminal to the base electrode and the SOI substrate in pixel units, and then An insulating film 113 is formed on a semicircular portion opposite to the light emitting portion including the terminal portion. A through hole for the base metal terminal is formed at the same time as the patterning of the insulating film. Next, the metal ITO reinforcing electrode 112 is formed on the insulating film so as not to overlap the terminal portion. At this time, a part of the metal film has a connection terminal with the base terminal electrode on the insulating film 113 through the through hole. Form. Next, as shown in steps (19), (20-23), and (25) of Fig. Ll (a) and (b), the cathode electrode 114 and the organic EL layer 115 are not affected by the lower half circle. Is mask-deposited to make contact with the reinforcing electrode to form the OLED part. These are all covered with a photosensitive transparent resin 117 as shown in step (26) of Fig. 1 l (a) and (b), photocured with the exception of the connecting terminals, and the terminals are developed through holes. The connection bumps to the SOI substrate are formed by means such as ink jet or dispenser.

[0048] 以下に、上記のプロセスの具体的な実行方法とデバイス構造の製造方法及び製造 装置の原理につ!、て述べる。 [0048] Hereinafter, the specific execution method of the above process, the manufacturing method of the device structure, and the principle of the manufacturing apparatus will be described.

全体の製造工程は大きく 4つに区分され、その大区分工程のフロー図を図 12に示 す。ファイバ 1次元基板製作工程は、現行二次元技術でのウェハー乃至 SOI基板を 作る工程に対応するので、ディスプレイ製造工程と独立と考えてもよい。セグメントァ レー化工程は、これら 1次元基板をディスプレイサイズに合わせて切断して円柱、多 角柱表面、または円筒内面内に配列、固定し、これらを改めて TFT, OLEDの製造ェ 程の「基板」とする工程である。 TFT, OLEDの製造工程は前述の様に工程フローとし ては二次元基板と同一である。最後は出来上がったファイバを組み立て製品化する 工程である。  The entire manufacturing process is roughly divided into four, and the flow chart of the major division process is shown in Fig. 12. The fiber 1D substrate manufacturing process corresponds to the process of making a wafer or SOI substrate with the current 2D technology, so it may be considered independent of the display manufacturing process. In the segment arraying process, these one-dimensional substrates are cut to fit the display size, arranged and fixed on the cylinder, polygonal column surface, or cylinder inner surface, and these are redesigned as “substrates” in the TFT and OLED manufacturing process. It is a process. The manufacturing process of TFT and OLED is the same as that of 2D substrate as described above. The last is the process of assembling the finished fiber into a product.

[0049] 本実施例ではディスプレイとしてアスペクト比 16:9、対角 50"の HD- TV及び 15" [0049] In the present embodiment, an HD-TV with an aspect ratio of 16: 9 and a diagonal of 50 "and 15" is used as a display.

SXGAを具体的な対象として取り上げる。前者の精細度はフルスペックで 1080 X 19 20 (画面サイズ ίま 1106 X 622mm)、画素サイズ ίま 0.576 χ 0.576 mm、 RGB各色の ピッチは 0.192 mmである。方式としては複合タイプを採用、 TFTは 125口、 OLEDは 125 μ φの石英ファイバを用いた。 15"ディスプレイの場合は、精細度 1024 X 1280 (画面サイズ ίま 228.6 X 304.8 mm)、画素サイズ ίま 0.223 χ 0.223 mm、 RGBのピッ チは 0.08 mmで、 70 ロおよび 70 φのファイバを用いた。 HD- TVの 1色当たりの ファイバ一長は約 1200mである。現行の大型 2次元基板のスループット時間は 60秒 であるので、これと同じスループットとして、ファイバ 1次元基板製作の走行速度は約 20m/sとした。 SXGA is taken up as a specific target. The definition of the former is 1080 X 19 20 (screen size ί or 1106 X 622 mm), pixel size 0.75 to 0.576 χ 0.576 mm, and the pitch of each RGB color is 0.192 mm in full spec. The system used was a composite type, with 125 apertures for TFT and 125 μφ quartz fiber for OLED. For a 15 "display, the resolution is 1024 x 1280 (screen size ί or 228.6 x 304.8 mm), pixel size ί or 0.223 x 0.223 mm, RGB pitch H was 0.08 mm, and 70 and 70 φ fibers were used. The length of fiber per color of HD-TV is about 1200m. Since the throughput time of the current large 2D substrate is 60 seconds, the traveling speed of fiber 1D substrate production is about 20m / s, which is the same throughput.

[0050] 図 13に石英ファイバによる SOI、ITO等 1次元基板の製造原理を示す。 131は通常 の石英ファイバ線引きのステージであり、ここで所与の径の石英ファイバを形成し、次 いでステージ 132で Si膜を高温雰囲気の中で、 CVD,溶射、融液塗膜-冷却等の手段 により Si結晶を形成、ファイバ一巻き取りに当たって 133, 134に於いてレジストを保護 膜として塗布、ロール 135により巻き取った。 ITO、金属膜等はステージ 132をこれら に適合した装置とし、以下同様な工程で基板を形成する。  [0050] Fig. 13 shows the manufacturing principle of one-dimensional substrates such as SOI and ITO using quartz fiber. 131 is a normal silica fiber drawing stage, in which a silica fiber of a given diameter is formed, and then in stage 132, the Si film is formed in a high-temperature atmosphere by CVD, spraying, melt coating-cooling, etc. In this way, a Si crystal was formed, and when winding the fiber, a resist was applied as a protective film at 133 and 134 and wound by a roll 135. For ITO, metal film, etc., the stage 132 is an apparatus suitable for these, and the substrate is formed by the same process.

[0051] 図 14にセグメントアレー化工程の原理図を示す。一次元基板が巻かれたロール 14 1からレジスト保護膜がかけられたファイバ 142が繰り出されて途中 143でレジストの 剥離、洗浄が行われ、「プロセス基板」化する冶具、「基板冶具」 145の表面に切断 · 配列装置 144によりセグメント化されたファイバが固定される。  FIG. 14 shows a principle diagram of the segment arraying process. A fiber 142 with a resist protective film is rolled out from a roll 14 1 wound with a one-dimensional substrate, and the resist is peeled off and cleaned in the middle 143 to form a “process substrate”. A segmented fiber is fixed to the surface by a cutting / arranging device 144.

[0052] 図 15(a),(b),(c)にセグメントアレー化により形成された「プロセス基板」の概念図を示 す。図 15(a)に示す符号 151がセグメントィ匕されたファイバで、 152がこれらファイバを 「プロセス基板」とする固定冶具である。この固定冶具には種々の構造が適用される 力 基本的な構造は回転軸を持つ円筒ないしは円柱または多角柱で、表面に軸方 向に沿ってファイバ位置決め用の溝が形成されている。図に明示していないが、冶 具上のファイバは両端で固定される。  [0052] Figures 15 (a), 15 (b), and 15 (c) show conceptual diagrams of “process substrates” formed by segment arraying. Reference numeral 151 shown in FIG. 15 (a) is a segmented fiber, and 152 is a fixing jig that uses these fibers as a “process substrate”. A variety of structures can be applied to this fixture. The basic structure is a cylinder, cylinder, or polygonal column with a rotation axis. Fiber positioning grooves are formed on the surface along the axial direction. Although not shown in the figure, the fiber on the fixture is fixed at both ends.

[0053] 他の基本的な構造として、図 15(b)に示す 2つのリング 153、 153'が支柱 154により 結合されているもので、この場合もリングの表面にファイバ位置決め用の溝が形成さ れており、両端には固定と張力によりファイバの直線性を保つ構成を持つ。円筒形状 の場合、当該冶具は 50"HD- TV用の場合直径 76.4 Φ、有効長さ 622mm,15"SVGA の場合は同 28.5 φ、 229mmである。従って平面基板に比較して HD- TVに対しては 1/14、 15"ディスプレイに対しては 1/10の「フットプリント」となり、装置の大幅な小型 化が実現出来る。  [0053] As another basic structure, two rings 153 and 153 'shown in Fig. 15 (b) are connected by a column 154, and in this case also, a fiber positioning groove is formed on the ring surface. It has a configuration that maintains the linearity of the fiber by fixing and tension at both ends. In the case of a cylindrical shape, the jig is 76.4 Φ in diameter for 50 ”HD-TV, 622 mm in effective length, and 28.5 φ and 229 mm in the case of 15” SVGA. Therefore, compared to a flat substrate, the “footprint” is 1/14 for HD-TV and 1/10 for a 15 ”display.

[0054] 更に別の構成として、図 15(c)に示す様にファイバ 151の両端をマイクロクランプ 15 5で保持しこれをチェイン 156に固定、以下これを「すだれ状基板」と称する。これは 有機フィルムで用いられて ヽる様なロール'ッゥ ·ロールの加工法に便利な形態であ る。マイクロクランプ 155としては単純なクランプと同時に一定角度回転可能な構造を とることによってファイバの各面の加工を容易にする。マイクロクランプは当然前記円 筒形基板にぉ 、ても用いることが出来る。 As another configuration, both ends of the fiber 151 are connected to a micro clamp 15 as shown in FIG. This is held at 5 and fixed to the chain 156, and this is hereinafter referred to as a “interdigital substrate”. This is a convenient form for processing the roll-to-roll used in organic films. The micro clamp 155 has a structure that can rotate at a constant angle simultaneously with a simple clamp, thereby facilitating the processing of each surface of the fiber. Of course, the micro clamp can be used even on the cylindrical substrate.

[0055] 図 9一図 11で説明した TFTおよび OLEDのプロセスでは、現行の二次元基板のプ 口セスと同一の工程、膜材を使用している。電極、配線等の金属材料は W、タンダス テンシリサイド、 Ti、 A1等であり、無機系絶縁材料としては SiO [0055] In the TFT and OLED processes described in Fig. 9 and Fig. 11, the same process and film material as the process of the current two-dimensional substrate are used. Metal materials such as electrodes and wiring are W, tandane silicide, Ti, A1, etc., and inorganic insulating materials are SiO.

2、 SiN等、有機系は感光 性透明榭脂である。成膜法としては金属の場合スパッタ、イオンクラスタビーム、金属 溶射等が用いられ、絶縁膜の場合は各種の CVDが用いられる。図 16(a),(b),(c)に円 筒基板に対するこれら成膜方法の原理図を示す。  2. Organic systems such as SiN are photosensitive transparent resins. As the film formation method, sputtering, ion cluster beam, metal spraying, etc. are used in the case of metal, and various CVDs are used in the case of an insulating film. Figures 16 (a), (b), and (c) show the principle of these deposition methods for a cylindrical substrate.

[0056] 図 16(a)は真空室 160にイオンクラスタビーム、金属溶射、大気圧プラズマ等、収束 ビーム状、乃至は集中プラズマ状態を発生するプロセスヘッド 162が設置された形式 であり、円筒基板 161の軸方向一次元的に成膜を行う方法である。回転機構 163に より基板全面の成膜、加工が行われる。  [0056] FIG. 16 (a) shows a type in which a process head 162 that generates a focused beam state or a concentrated plasma state such as an ion cluster beam, metal spray, atmospheric pressure plasma, etc. is installed in a vacuum chamber 160, and is a cylindrical substrate. 161 is a method of performing film formation in a one-dimensional direction in the axial direction. The rotation mechanism 163 performs film formation and processing on the entire surface of the substrate.

[0057] 図 16(b)は円筒型 CVD装置の 2つの形式を示す。図 16(b)の (0は外部の円筒形 16 4の内部に円筒基板 161がある場合で、 GOは円筒基板 165の内壁にファイバが固定 される方法で、この場合円筒基板が CVD装置の外壁を構成する。  [0057] Fig. 16 (b) shows two types of cylindrical CVD apparatus. In Fig. 16 (b), (0 is the case where the cylindrical substrate 161 is inside the outer cylindrical shape 164, and GO is a method in which the fiber is fixed to the inner wall of the cylindrical substrate 165. Configure the outer wall.

[0058] 図 16(c)は、図 16(b)に対応するスパッタ装置の方式であり、図 16(c)の (0は外部の 円筒形 166が真空室を形成し、この内部にスパッタターゲット 167が 1個乃至は複数 個設置されており、回転機構 163により円筒基板 161全面に成膜が行われる。図 16 (c)の (ii)は円筒基板自体が基板ホールダー、場合によっては真空室の外壁を兼ねる 方式で、中心軸にスパッタターゲット 168が設置されて!、る。  [0058] Fig. 16 (c) shows a sputtering apparatus system corresponding to Fig. 16 (b). In Fig. 16 (c), (0 is an external cylindrical shape 166 forms a vacuum chamber, and the inside is sputtered. One or a plurality of targets 167 are installed, and film formation is performed on the entire surface of the cylindrical substrate 161 by the rotating mechanism 163. (ii) in Fig. 16 (c) shows that the cylindrical substrate itself is a substrate holder, and in some cases a vacuum. Sputter target 168 is installed on the central axis in the system that doubles as the outer wall of the room!

[0059] ドライエッチング及び装置は成膜におけるプラズマ CVD (P-CVD)及びスパッタと本 質的に同一のプロセス、装置原理である。即ち図 16(a)でプロセスヘッドが大気圧プ ラズマでエッチングガスを導入する力、図 16(b)で CVDガスをエッチングガスに変更す る力、または図 16(c)でターゲットの代わりに電極のみとする力 いずれかの方法でド ライエッチングを行う。 [0060] 以上各種成膜並びにドライエッチングの方式と装置原理について述べた力 バタ ーン形成は二次元基板と同様なフォトリソグラフィを円筒基板に適用する。図 17にレ ジスド塗布方法の概念を示す。図中符号 171はレジスト剤をスリットロカゝら円筒基板 1 70上に注出させる構成で、円筒基板は回転機構 172により回転、均一化と全面塗布 を行う。図 15(b)のタイプの冶具の場合には、円筒基板全体をレジスト液中にディップ して中心軸の回りに回転させファイバ全周に均一なレジスト層を形成する方法をとる 。レジスト塗布した円筒基板は円筒状のベーク炉でプリベータされる。 [0059] Dry etching and equipment are essentially the same processes and equipment principles as plasma CVD (P-CVD) and sputtering in film formation. That is, the force at which the process head introduces the etching gas with an atmospheric plasma in FIG. 16 (a), the force to change the CVD gas to the etching gas in FIG. 16 (b), or the target in FIG. 16 (c). Force to use only electrode Perform dry etching by either method. [0060] The force pattern formation described above regarding various film formation and dry etching methods and apparatus principles applies photolithography similar to a two-dimensional substrate to a cylindrical substrate. Figure 17 shows the concept of the resist coating method. In the figure, reference numeral 171 denotes a configuration in which a resist agent is poured onto a cylindrical substrate 170 such as a slit locuser, and the cylindrical substrate is rotated, uniformized and entirely coated by a rotating mechanism 172. In the case of the jig shown in FIG. 15 (b), the entire cylindrical substrate is dipped in a resist solution and rotated around the central axis to form a uniform resist layer around the entire fiber. The resist-coated cylindrical substrate is pre-beta in a cylindrical baking furnace.

[0061] 図 18に画素回路 TFTに用いられる高精度露光機の概念図を示す。その露光機は 、円筒または多角柱基板 180上のファイバ 1本づっを対象として露光する方式で、図 中符号 181は基板を中心軸の回りに回転させると同時に軸方向への移動も行わせる 機構である。 182は、露光領域が 5mm口の 5:1縮小投影結像レンズで、複数個連結 されている。アラインメントはサーボ制御機構 183が各レンズを独立に X-Y-Z 3軸を 制御する。制御データは露光の前段階で各ファイバの位置座標を検出用の光学へッ ド 186で高速で読みとつて回線 187を介して記憶 ·計算系 188に入力、記憶 ·計算系 188から制御信号が回線 189を介して 183に伝達されレンズ系のサーボ制御が行わ れる。光学ヘッドの代わりにファイバの側面を感知する機械的な触針でもよい。本露 光系の光源 185として、波長 308nmまたは 248nmのエキシマレーザーを用いる。照 明光学系 184は通常のケーラー照明系であるが、円筒レンズ等を用いて照明領域は 幅 0.2mm、長さは結象レンズ系の連結の長さに対応し、少なくとも 250mmのスリット状 である。  FIG. 18 shows a conceptual diagram of a high-precision exposure machine used for the pixel circuit TFT. The exposure machine is a system that exposes a single fiber on a cylindrical or polygonal column substrate 180. Reference numeral 181 in the figure rotates the substrate around the central axis and simultaneously moves it in the axial direction. It is. Reference numeral 182 denotes a 5: 1 reduction projection imaging lens having an exposure area of 5 mm, and a plurality of them are connected. The alignment is controlled by the servo control mechanism 183 that controls each of the X-Y-Z three axes independently. The control data is read at high speed with the optical head for detection 186 in the pre-exposure stage and stored in the calculation system 188 via the line 187, and the control signal is received from the calculation system 188. This is transmitted to line 183 via line 189 and servo control of the lens system is performed. A mechanical stylus that senses the side of the fiber may be used instead of the optical head. An excimer laser with a wavelength of 308 nm or 248 nm is used as the light source 185 of this exposure system. The illumination optical system 184 is an ordinary Koehler illumination system, but using a cylindrical lens, etc., the illumination area is 0.2 mm wide and the length corresponds to the length of the concatenation lens system connection, and is at least 250 mm in slit shape. is there.

[0062] 図 19に露光光学系の等価光学系を示す。適当な形状に加工されたエキシマレー ザ一の平行光 190を分割レンズ 192により二次光源を作成し、二次光源 193とコン デンサレンズ 194と共に所与の形状で均一分布化された光でマスク 196を照明する 。フィールドレンズ 195は結像レンズ 197の入射瞳 198に二次光源像を形成し、結像 面 199にマスク像を形成する。図の光学系 190— 195はスリツト状照明の X, Y軸方向 のいずれかを現しており、実際には 2組の光学系力もなる。これは共通の光学系であ る力、フィールドレンズ 195以降はそれぞれ個別の光学系となっている。  FIG. 19 shows an equivalent optical system of the exposure optical system. The secondary light source 190 is created by the splitting lens 192 from the parallel light 190 of the excimer laser processed into an appropriate shape, and the mask 196 is formed with the light uniformly distributed in a given shape together with the secondary light source 193 and the capacitor lens 194. Illuminate. The field lens 195 forms a secondary light source image on the entrance pupil 198 of the imaging lens 197 and forms a mask image on the imaging surface 199. The optical system 190-195 in the figure represents either the X-axis or Y-axis direction of the slit-like illumination, and actually two sets of optical system forces. This is a force that is a common optical system, and the field lens 195 and later are separate optical systems.

[0063] ここでのエキシマ光源の出力は、 2kHz、 10W,即ち 5mJ/lshotである。従ってスリツ ト状照明部のエネルギー密度は光源ベースで 10mJ/cm2、光学系の損失を 50%とし て 5mJ/cm2となる。化学増感系のレジストの必要ドーズ量は 30mJ/cm2程度であるの で、 6 shot/siteの露光が必要となる。 6 shotでエキシマレーザーの空間コヒーレンス の効果も打ち消される。 50"HD-TV用の円筒基板に対する総 shot数は従って、 633/ 50 X 1920 X 6 = 149760となり、 2kHzのレーザーでは 75禾少、サーボ帘 U御の時間を 入れて約 2分が高精度露光工程の所要時間である。 The output of the excimer light source here is 2 kHz, 10 W, that is, 5 mJ / lshot. Therefore Slitz The energy density of bets spread illuminating unit 10 mJ / cm 2 in the light source base, the 5 mJ / cm 2 loss in the optical system by 50%. Since the required dose of chemically sensitized resist is about 30 mJ / cm 2 , exposure of 6 shots / site is required. The effect of the spatial coherence of the excimer laser is canceled with 6 shots. The total number of shots for a 50 "HD-TV cylindrical substrate is therefore 633/50 X 1920 X 6 = 149760, with a 2kHz laser, 75% less, and approximately 2 minutes high with servo time. This is the time required for the exposure process.

[0064] 以上は高精度を要する画素スィッチの露光方式であるが、 TFT程の精度を要せず 広い面積にわたるパターン、例えば画素スィッチ内配線、ノ¾ /ド並びにファイバー軸 方向のパターン等の場合には、図 20に示す様な 1: 1プロキシミティ露光を用いた。 入射光 204がファイバ 201の端部を充分カバーする角度を張ってファイバ中心に集 光する様設計された円筒型レンズ 202がファイバと平行に置かれ、これによつてマス クパターン 203はファイバ曲面に沿って投影される。上記円筒形レンズは 1本ないし 多数本カゝらなり、ファイバとのアラインメントに対応する様に構成されている。当該露 光で光源として前記エキシマ照明系を用いた場合、 1 : 1のため、工程時間は短縮さ れて 30秒程度となる。 [0064] The above is a pixel switch exposure method that requires high accuracy, but it does not require as high accuracy as a TFT, and in the case of a pattern over a large area, such as wiring in a pixel switch, a pattern in a node / node, and a fiber axis direction, etc. For this, 1: 1 proximity exposure as shown in Fig. 20 was used. A cylindrical lens 202 designed to collect the incident light 204 at the center of the fiber at a sufficient angle to cover the end of the fiber 201 is placed parallel to the fiber, so that the mask pattern 203 is a curved surface of the fiber. Projected along. The cylindrical lens is composed of one or a plurality of lenses, and is configured to correspond to the alignment with the fiber. When the excimer illumination system is used as a light source in the exposure, the process time is reduced to about 30 seconds because of 1: 1.

[0065] 図 21(a),(b),(c)は現像、剥離、ウエットエッチング、洗浄、等のウエットプロセス方式 の原理図を示す。図 12(a)は円筒基板 211を横型のウエット槽 212で処理する方式で 、槽内で回転、搬送系 213で複数のウエットプロセスを行う。図 21(b)は縦型の槽 214 を用いた場合である。図 21(c)は、図 15(c)の形状のすだれ基板 215に適応する方式 で、ローラ搬送系 217- 1— 217- 3によりウエット槽 216を通過させる。洗浄後乾燥清 浄空気または窒素等を噴射またはエアナイフ状に吹き付けて乾燥させる。  [0065] FIGS. 21 (a), (b), and (c) show the principle diagrams of a wet process system such as development, peeling, wet etching, and cleaning. FIG. 12A shows a method in which the cylindrical substrate 211 is processed in a horizontal wet tank 212, and a plurality of wet processes are performed in the rotation and transfer system 213 in the tank. Figure 21 (b) shows the case where the vertical tank 214 is used. FIG. 21 (c) is a method adapted to the interdigital substrate 215 having the shape shown in FIG. 15 (c), and the wet tank 216 is passed through the roller transport systems 217-1 to 217-3. After washing, dry clean air or nitrogen is sprayed or blown like an air knife.

[0066] 不純物の導入方式としてはイオン打ち込み、プラズマドーピングの 2方式を用いて いる。イオン打ち込みは図 16(a)でのプロセスヘッドがスリット状のイオンガンとなった ものである。プラズマドーピングの方式、装置は成膜における P-CVD及びスパッタと 本質的に同一のプロセス、装置原理である。即ち図 16(a)でプロセスヘッドが大気圧 プラズマで不純物ガスを導入する力 図 16(b)で CVDガスを不純物ガスに変更するか 、または図 16(c)でターゲットの代わりに電極のみとして不純物ガスを導入する力、い ずれかの方法でドーピングを行う。不純物活性ィ匕は通常の熱ァニール法である。また 工程中の水素ァニールも通常の半導体プロセスと同様、水素炉を用いて 、る。 [0066] As an impurity introduction method, two methods of ion implantation and plasma doping are used. In the ion implantation, the process head in Fig. 16 (a) is a slit ion gun. The plasma doping method and equipment are essentially the same process and equipment principle as P-CVD and sputtering in film formation. That is, in FIG. 16 (a), the process head introduces the impurity gas by atmospheric pressure plasma. In FIG. 16 (b), the CVD gas is changed to the impurity gas, or in FIG. 16 (c), only the electrode is used instead of the target. Doping is performed by either method of introducing impurity gas. The impurity activity is the usual thermal annealing method. Also The hydrogen anneal in the process is performed using a hydrogen furnace as in a normal semiconductor process.

[0067] この様にして作製されたファイバを 2次元の平面ディスプレイとするためには、まず 図 22(a)に示す様に TFT、 OLED各円筒基板 221ないしはすだれ状基板上のフアイ ノ 223のパッド部に OLEDにダメージを与えない低温で用いられる半田ないしは導電 接着剤をインクジェット 224等の手段でデポする。この際、円筒基板は軸 222で回転 、移動を行う。または軸方向の移動はインクジェットヘッド 224でもよい。このようにし てバンプの形成された両ファイバの内、図 22(b)に示す様に片方 225 (223)を円筒 基板等から外し、両端の保持と圧着を行う冶具 227を用いてもう片方のファイバ 226 に位置合わせ後圧着する。ファイバのプロセス化基板冶具によつてはこの段階で両 ファイバの接続のテストを行う。  [0067] In order to make the fiber manufactured in this way into a two-dimensional flat display, first, as shown in Fig. 22 (a), the TFT and OLED cylindrical substrates 221 or the interdigital substrate 223 Deposit solder or conductive adhesive used at low temperatures that will not damage the OLED on the pad using means such as inkjet 224. At this time, the cylindrical substrate rotates and moves around the shaft 222. Alternatively, the axial movement may be performed by the inkjet head 224. As shown in Fig. 22 (b), remove one 225 (223) from the cylindrical substrate, etc., and use the jig 227 to hold and crimp both ends of the two fibers with bumps formed in this way. Crimp on fiber 226 after alignment. For fiber processed substrate jigs, the connection of both fibers is tested at this stage.

[0068] 次いでこれら複線ファイバ 231を図 23(a)に示すファイバ固定枠 232に画面ピッチ に合わせて RGBの順で固定する。この枠 235 (232)は図 23(b)に示す様に下記に 述べるゲート線接続の妨げにならない様、 OLEDファイバ 233より外側にある。固定後 、 TFTファイバ 234のゲート用パッドに上記と同様、インクジェット等の方法で矢印 23 6の方向から低融点半田等を堆積する。この段階で両ファイバの接続テストを行って もよい。またここで不用端部の切断を行う。次にファイバとゲート線との接続を行う。  Next, these double-wire fibers 231 are fixed to the fiber fixing frame 232 shown in FIG. 23 (a) in the order of RGB in accordance with the screen pitch. This frame 235 (232) is outside the OLED fiber 233 so as not to interfere with the gate line connection described below, as shown in FIG. 23 (b). After fixing, a low melting point solder or the like is deposited on the gate pad of the TFT fiber 234 from the direction of the arrow 236 by an ink jet method or the like as described above. At this stage, a connection test of both fibers may be performed. Further, the unnecessary end portion is cut here. Next, the fiber and the gate line are connected.

[0069] 図 24に示す様にゲート線用銅線を画素ピッチに従って張った枠 241は、図 23で示 したファイバ固定枠 232と一部入れ子の構造となっている。銅線には予め低温半田 がつけられている。ファイバ 242, 243と銅線の位置関係は図 24(b)に示す通りで、 OLEDファイバ 242の下の TFTファイバ 243の下辺に熱圧着または図 25に示すレー ザ一マイクロ溶接機により接続される。  As shown in FIG. 24, a frame 241 in which a copper wire for a gate line is stretched according to the pixel pitch has a partially nested structure with the fiber fixing frame 232 shown in FIG. Copper wire is pre-coated with low-temperature solder. The positional relationship between the fibers 242, 243 and the copper wire is as shown in Fig. 24 (b), and is connected to the lower side of the TFT fiber 243 under the OLED fiber 242 by thermocompression bonding or the laser micro welder shown in Fig. 25. .

[0070] 後者の場合、図 24の枠は X-Yステージ上にあり、図 25に示すようにゲート線 251は 紙面に垂直 (Y)に走っている。レーザー溶接ヘッドはゲートパッド位置に同期してパ ルス光を出射する。 1ゲートラインが終了すると X-ステージにより画素垂直ピッチ分移 動して同様な操作を行う。ゲート線 251は通状の銅線で、線径は 100 m φであり、 銅線間の空隙は 50"HD- TVの場合、 476 μ mである。マイクロウェルダーの光学へッ ド部 253は台形プリズム 254とミラー 255、マイクロレンズ 256からなるマイクロォプテ イツタス光学系である。パルスレーザー光 257は台形プリズムより分割され銅線の両 側から TFTファイバ 252上のバンプ 258に照射される。 In the latter case, the frame in FIG. 24 is on the XY stage, and the gate line 251 runs perpendicularly (Y) to the paper surface as shown in FIG. The laser welding head emits pulse light in synchronization with the gate pad position. When one gate line is completed, the same operation is performed by moving the pixel vertical pitch by the X-stage. The gate wire 251 is a continuous copper wire, the wire diameter is 100 mφ, and the gap between the copper wires is 476 μm for 50 ”HD-TV. The optical head part 253 of the microwelder is This is a micro-optics optical system consisting of a trapezoidal prism 254, a mirror 255, and a microlens 256. The pulsed laser beam 257 is divided by a trapezoidal prism and is divided into both copper wires. The bump 258 on the TFT fiber 252 is irradiated from the side.

[0071] レーザーとして YAGレーザー基本波を用い、これをレンズ 256により 10 πι φ以下 に集光してバンプを融解、溶接する。 m φ以下の集光のためには元のレーザー 光源の出力が TEM モードでなければならずない。このため導光系として通常用いら [0071] A YAG laser fundamental wave is used as a laser, and this is condensed to 10πιφ or less by a lens 256 to melt and weld the bump. For condensing below mφ, the output of the original laser source must be in TEM mode. For this reason, it is usually used as a light guide system.

00  00

れて 、るファイバーを使用せず、出来るだけ単純な 2枚レンズのビームイクスパンダと 図 25の光学系を用いている。今考えている HD- TVの垂直画素ピッチは 576 μ mであ るので、発振周波数 20kHzの光源を用いると、移動速度は約 12m/sとなる。 1ゲート ラインの走行所要時間は約 0.1秒、従って全画面で 108秒必要である。実際には、加 速、減速、 1画素ピッチ移動等の各動作がそれぞれ 0.1秒弱必要であり、約 400秒、 即ち 1ヘッドでは約 7分を要した力 これを多ヘッドにすることにより、 1分以下で 1枚 のディスプレイを完成することが出来た。  However, it uses a simple two-lens beam expander and the optical system shown in Fig. 25 without using any fiber. The vertical pixel pitch of the HD-TV we are considering now is 576 μm, so when using a light source with an oscillation frequency of 20 kHz, the moving speed is about 12 m / s. The travel time for one gate line is approximately 0.1 seconds, so 108 seconds are required for the full screen. Actually, each operation such as acceleration, deceleration, and movement of one pixel pitch requires less than 0.1 seconds each, and it takes about 400 seconds, that is, a force that requires about 7 minutes for one head. One display could be completed in less than a minute.

[0072] OLEDの共通電極に対する接続は画面に入らない端部に 2本の線を OLEDファイバ に接続する。この為に図 26(a)に示す様な共通線用枠 261は、この上に張られた 2本 の導線 263が図 26(b)のように OLEDファイバ 264の上部に位置する様な構造を持つ 。 OLEDファイバおよび 2本の共通線には予め低温で接続する導電性接着剤がインク ジェット等の方法でデポされており、これを低温熱圧着する。  [0072] To connect to the common electrode of the OLED, connect two wires to the OLED fiber at the end that does not enter the screen. For this reason, the common wire frame 261 as shown in FIG. 26 (a) has a structure in which the two conductors 263 stretched on it are positioned above the OLED fiber 264 as shown in FIG. 26 (b). have . The OLED fiber and the two common wires are pre-deposited with a conductive adhesive that is connected at a low temperature by a method such as ink jet.

[0073] 以上の^ aみ立てが終了した後、プロ一バーを用いて点灯検査を行い、特に、上記 接続の検査を行う。接続が完全であることを確認して次に信号ドライバー ICチップ、 電流源、ゲートドライバー ICチップ、共通電極等の実装を行う。信号ドライバー ICチッ プと電流源とは TFTファイバの端部と接続される。  [0073] After the above preparation is completed, a lighting inspection is performed using a professional bar, and in particular, the above connection is inspected. After confirming that the connection is complete, mount the signal driver IC chip, current source, gate driver IC chip, common electrode, etc. The signal driver IC chip and the current source are connected to the end of the TFT fiber.

[0074] これらの回路部品は 0. 4mm厚の多層配線力もなるフレキシブル乃至はリジッドな回 路基板に取り付けられておりそれぞれ垂直画素列に対して端子が形成されている。 これらとファイバの接続方法は上記と全く同様である。ゲート線および共通線は同じく ゲートドライバー ICチップ、共通電極を積載した多層配線カゝらなるフレキシブル乃至 はリジッドな回路基板が前記と直行する辺に配置され、同様に接続される。これら実 装の検査終了後、図 7、図 8に示す様に、ファイバーの出射面と反対側に黒色塗料を 含む榭脂を流し込み、次いでファイバーの出射面側に透明榭脂を流し込み全体の 厚みが lmm以下となる様平板に整形し表示パネルを完成する。 [0075] 以上説明した様に本発明によれば、 2mm以下の超薄型、且つ大型高精細ディスプ レイを低コストで製作出来る。従って、本格的な壁掛け TV、医療用、電子ペーパー等 の種々の応用範囲が拡大する。更に、全く新規の生産装置であるため、新しい産業 を興すと同時に、装置自体が小型で製造コストが低いため、技術革新のスピードアツ プが可能となる。また、ここでは内容に立ち入らないが、これら装置、プロセスのデイス プレイ以外への波及効果が多大であり、特にナノ技術に至る前段としての意義が大 きい。 [0074] These circuit components are attached to a flexible or rigid circuit board having a multilayer wiring force of 0.4 mm thickness, and terminals are formed for each vertical pixel column. The method for connecting these to the fiber is exactly the same as described above. The gate line and the common line are similarly connected to each other by a gate driver IC chip and a flexible or rigid circuit board such as a multilayer wiring card on which common electrodes are mounted arranged on the side perpendicular to the above. After the inspection of these implementations, as shown in Fig. 7 and Fig. 8, the resin containing black paint is poured on the opposite side of the fiber exit surface, and then the transparent resin is poured on the fiber exit surface side. Complete the display panel by shaping it into a flat plate so that is less than lmm. [0075] As described above, according to the present invention, an ultra-thin and large-sized high-definition display of 2 mm or less can be manufactured at low cost. Therefore, various application areas such as full-scale wall-mounted TV, medical use, and electronic paper will be expanded. Furthermore, since it is a completely new production device, it will be possible to speed up technological innovation because it will create a new industry and at the same time it will be small in size and low in manufacturing costs. Although I will not go into the contents here, the ripple effect of these devices and processes other than the display is enormous, and is particularly significant as a pre-stage leading to nanotechnology.

[0076] また、携帯電話用のディスプレイや 7から 10インチ用のディスプレイの場合は、駆動 回路素子をシリコンウェハやガラス基板で作製された平面基板を用い、それらと OLEDファイバをアレイ化したものを組合わせて有機 ELディスプレイとしても良!、。比 較的小型サイズのディスプレイの場合、シリコンウェハプロセスは半導体デバイスが 大量に使われているために非常に安価に調達できる利点がある。し力し素子のサイ ズが 50 μ m以下の高精細なディスプレイを作製する事は通常の二次元基板を用いた ディスプレイでは非常に難 U、。それは有機 EL素子を作製するばぁ 、金属のシャド ゥマスクをもちいて作製するためで、マスクの赤、緑、青色ごとに別のマスクを用いる のでその都度ァライメントしなければならず、真空装置内でァライメント精度が 5 μ m 以下を出すのが非常に困難なためである。マスクと基板の相対位置精度としては、マ スクの加工精度 3 μ m以下、ァライメント精度 5 μ m程度、プロセス中の熱膨張による変 形によるずれ 1から 3 mが考えられる。従って、総合的には 5から 10 m程度となり、 上記の素子サイズ以下を産業レベルで実現する事は難 ヽ。しかし一次元基板を用 いる方式では、有機 ELの成膜をリール 'ツー'リール方式を用いて、各色事に独立に 行い配列する事が出来る。この場合、マスクは 1または数箇所のスリット状のシャドウ マスクでよいので、 1 以下の精度で作製でき、前記マスクを固定し、間欠的に一次 元基板を前記マスク上を移動させることで容易に高精度に成膜できる。もちろん一次 元基板の移動に同期させて前記マスクを移動させると連続的に製造する事が出来る  [0076] In addition, in the case of a display for a mobile phone or a display for 7 to 10 inches, a planar substrate made of a silicon wafer or a glass substrate is used as a drive circuit element, and an OLED fiber arrayed with them. It can also be combined as an organic EL display! For relatively small size displays, the silicon wafer process has the advantage that it can be procured very inexpensively because of the large volume of semiconductor devices used. However, it is very difficult to produce a high-definition display with an element size of 50 μm or less using a normal two-dimensional substrate. This is because when manufacturing an organic EL element, a metal shadow mask is used, and a different mask is used for each of the red, green, and blue masks. This is because it is very difficult to obtain alignment accuracy of 5 μm or less. The relative position accuracy between the mask and the substrate may be mask processing accuracy of 3 μm or less, alignment accuracy of about 5 μm, and displacement of 1 to 3 m due to deformation due to thermal expansion during the process. Therefore, the total length is about 5 to 10 m, and it is difficult to achieve the above element size below the industrial level. However, in the method using a one-dimensional substrate, the organic EL film can be arranged and arranged independently for each color by using a reel 'two' reel method. In this case, since the mask may be one or several slit-shaped shadow masks, it can be manufactured with an accuracy of 1 or less, and can be easily obtained by fixing the mask and intermittently moving the one-dimensional substrate on the mask. Films can be formed with high accuracy. Of course, if the mask is moved in synchronization with the movement of the one-dimensional substrate, it can be manufactured continuously.

[0077] このように、比較的小型のディスプレイの場合は、 OLEDファイバのアレーと二次元 基板で作製された TFT回路基板を組み合わせる事で、安価でかつ高精細なディスプ レイが実現できる。シリコンウェハを用いた場合は、 TFTの性能は、多結晶の TFTに 比べて非常に良いので高速応答が向上でき、又回路も複雑な機能を追加でき、色補 正なども向上できる。 [0077] In this way, in the case of a relatively small display, an inexpensive and high-definition display can be achieved by combining an OLED fiber array and a TFT circuit board made of a two-dimensional substrate. Ray can be realized. When a silicon wafer is used, the TFT performance is much better than that of a polycrystalline TFT, so that high-speed response can be improved, complicated functions can be added to the circuit, and color correction can be improved.

Claims

請求の範囲 The scope of the claims [I] 石英ファイバの表面に形成された半導体層と、  [I] a semiconductor layer formed on the surface of the quartz fiber; 前記半導体層に形成された能動素子と  An active element formed in the semiconductor layer; を有する半導体装置。  A semiconductor device. [2] 前記半導体層は、単結晶又は多結晶のシリコン膜であることを特徴とする請求項 1に 記載の半導体装置。  2. The semiconductor device according to claim 1, wherein the semiconductor layer is a monocrystalline or polycrystalline silicon film. [3] 前記石英ファイバの上には配線が形成されていることを特徴とする請求項 1又は請求 項 2に記載の半導体装置。  [3] The semiconductor device according to [1] or [2], wherein a wiring is formed on the quartz fiber. [4] 前記配線には、金属線材が接続されることを特徴とする請求項 3に記載の半導体装 置。 [4] The semiconductor device according to [3], wherein a metal wire is connected to the wiring. [5] 前記能動素子はトランジスタであることを特徴とする請求項 1乃至請求項 4の 、ずれ 力 1つに記載の半導体装置。  5. The semiconductor device according to claim 1, wherein the active element is a transistor. [6] 前記トランジスタは MOS型トランジスタであって、前記半導体層の表面に形成された 酸化膜と、前記酸化膜上に形成されたゲート電極とを有することを特徴とする請求項6. The transistor is a MOS type transistor, and has an oxide film formed on a surface of the semiconductor layer and a gate electrode formed on the oxide film. 5に記載の半導体装置。 5. The semiconductor device according to 5. [7] 透明絶縁材カ なるファイバと、 [7] A transparent insulating material fiber, 前記ファイバの上に形成される電極膜と、  An electrode film formed on the fiber; 前記ファイバの上に形成される発光層と  A light emitting layer formed on the fiber; を有することを特徴とする表示装置。  A display device comprising: [8] 前記ファイバは、石英、ブラスティックのいずれか 1つから構成されていることを特徴と する請求項 7に記載の標示装置。 8. The marking device according to claim 7, wherein the fiber is composed of any one of quartz and plastic. [9] 前記電極膜は、透明電極膜であることを特徴とする請求項 7又は請求項 8に記載の 表示装置。 [9] The display device according to claim 7 or 8, wherein the electrode film is a transparent electrode film. [10] 前記透明電極は、前記発光層と前記ファイバの間に形成されていることを特徴とする 請求項 9に記載の標示装置。  10. The marking device according to claim 9, wherein the transparent electrode is formed between the light emitting layer and the fiber. [II] 前記透明電極は、前記有機発光層うち前記ファイバ側とは反対の面に形成されるこ とを特徴とする請求項 7又は請求項 8に記載の標示装置。  [II] The marking device according to claim 7 or 8, wherein the transparent electrode is formed on a surface of the organic light emitting layer opposite to the fiber side. [12] 前記電極膜は、前記発光層のうち光出射方向に対して反対側の面に接続されてい る金属電極膜であることを特徴とする請求項 7乃至請求項 11のいずれか 1つに記載 の表示装置。 [12] The electrode film is connected to a surface of the light emitting layer opposite to a light emitting direction. 12. The display device according to claim 7, wherein the display device is a metal electrode film. [13] 前記発光層は、有機エレクト口ルミネッセント層であることを特徴とする請求項請求項 13. The light emitting layer is an organic electoluminescent layer, 7乃至請求項 12のいずれか 1つに記載の表示装置。 The display device according to any one of claims 7 to 12. [14] 前記発光層は複数の領域に形成されていることを特徴とする請求項 7乃至請求項 13 のいずれか 1つに記載の表示装置。 [14] The display device according to any one of [7] to [13], wherein the light emitting layer is formed in a plurality of regions. [15] 前記ファイバは、隣接して並列に複数配置されていることを特徴とする請求項 7乃至 請求項 14のいずれか 1つに記載の表示装置。 [15] The display device according to any one of claims 7 to 14, wherein a plurality of the fibers are adjacently arranged in parallel. [16] 能動素子が形成される第 1のファイバと、 [16] a first fiber on which an active element is formed; 前記第 1のファイバに結合されて前記第 1のファイバとともに複合一次元基板を構 成し且つ複数領域に発光層が形成される第 2のファイバと  A second fiber coupled to the first fiber to form a composite one-dimensional substrate together with the first fiber and having a light emitting layer formed in a plurality of regions; を備えた表示装置。  A display device comprising: [17] 前記復号一次元基板は、並列に複数配置されて画面を構成することを特徴とする請 求項 16に表示装置。  [17] The display device according to claim 16, wherein a plurality of the decoding one-dimensional substrates are arranged in parallel to form a screen. [18] 前記画面のうち光出射側には透明材カ なる第 1の保護膜と、 [18] On the light exit side of the screen, a first protective film made of a transparent material, 前記画面のうち光出射側と反対側には遮光材カ なる第 2の保護膜と  A second protective film serving as a light shielding material is provided on the opposite side of the screen from the light emitting side. を有することを特徴とする請求項 16又は請求項 17に記載の表示装置。  18. The display device according to claim 16 or claim 17, further comprising: [19] 前記第 1のファイバ上には、長手方向に形成されて前記能動素子に外部の画像信 号を導入する第 1の信号線導体と、長手方向に形成されて前記発光層に電流を供 給する電流源線状導体とが形成されていることを特徴とする請求項 16乃至請求項 1[19] On the first fiber, a first signal line conductor that is formed in the longitudinal direction and introduces an external image signal to the active element, and is formed in the longitudinal direction to pass current to the light emitting layer. A current source linear conductor to be supplied is formed. 8のいずれか 1つに記載の表示装置。 8. The display device according to any one of 8. [20] 前記電流源線状導体の端部には電流源が接続されて!ヽることを特徴とする請求項 1The current source is connected to a current source at the end of the current source linear conductor. 6乃至請求項 19のいずれか 1つに記載の表示装置。 The display device according to any one of claims 6 to 19. [21] 前記第 1のファイバ上に形成されて前記能動素子に接続される導電性パッドと、 前記第 1のファイバの長手方向に交差する方向に配置されて導電性パッドに接続 される第 2の信号線導体と [21] A conductive pad formed on the first fiber and connected to the active element; and a second conductive pad arranged in a direction intersecting the longitudinal direction of the first fiber and connected to the conductive pad Signal line conductor and をさらに有することを特徴とする請求項 16乃至請求項 20に記載の表示装置。  21. The display device according to claim 16, further comprising: [22] 前記第 1の信号線導体と前記第 2の信号線導体の端部には駆動回路が接続されて V、ることを特徴とする請求項 21に記載の表示装置。 [22] A driving circuit is connected to ends of the first signal line conductor and the second signal line conductor. The display device according to claim 21, wherein the display device is V. [23] 前記発光層のうち光出射側に形成された透明導電性力 なる共通電極を有すること を特徴とする請求項 6乃至請求項 22のいずれか 1つに記載の表示装置。 [23] The display device according to any one of [6] to [22], wherein a common electrode having a transparent conductive force is formed on the light emitting side of the light emitting layer. [24] 前記ファイノからなる一次元基材または該一次元基材に電極を形成した一次元基板 の長手方向に、発光素子を形成した発光素子ファイバを並べて平面または曲面状と し、さらに前記各々の発光素子の近傍に駆動回路をそれぞれ配設したことを特徴と する請求項 7に記載の標示装置。 [24] A light-emitting element fiber in which a light-emitting element is formed is arranged in a longitudinal direction of a one-dimensional base material made of the above-mentioned fino or a one-dimensional substrate on which an electrode is formed on the one-dimensional base material, and is formed into a plane or a curved surface. 8. The marking device according to claim 7, wherein a drive circuit is provided in the vicinity of each of the light emitting elements. [25] 前記駆動回路が前記一次元基材または前記一次元基材に半導体を形成した一次 元基板で形成され、前記駆動回路に対応する前記発光素子ファイバと接続されたこ とを特徴とする請求項 24に記載の表示装置。 [25] The drive circuit is formed of the one-dimensional substrate or a one-dimensional substrate in which a semiconductor is formed on the one-dimensional substrate, and is connected to the light-emitting element fiber corresponding to the drive circuit. Item 25. The display device according to item 24. [26] 前記一次元基板の断面の形状が矩形または多角形であることを特徴とする請求項 226. The cross-sectional shape of the one-dimensional substrate is a rectangle or a polygon. 5に記載のディスプレイ。 5. The display according to 5. [27] 前記発光素子ファイバの最大投影面積が前記一次元基板の最大投影面積以上で あることを特徴とする請求項 25または請求項 26に記載の表示装置。 27. The display device according to claim 25 or claim 26, wherein a maximum projected area of the light emitting element fiber is equal to or greater than a maximum projected area of the one-dimensional substrate. [28] 前記一次元基材または前記一次元基材に透明電極を形成した一次元 TCO基板の 長手方向に、前記発光素子を形成した前記発光素子ファイバを並べて平面または曲 面状とし、さらに前記各々の発光素子の前記駆動回路が前記一次元基板を用いて 形成することを特徴とする請求項 24から請求項 27のいずれ力 1項に記載の表示装 置。 [28] The light-emitting element fibers on which the light-emitting elements are formed are arranged in a longitudinal direction of the one-dimensional base material or a one-dimensional TCO substrate in which a transparent electrode is formed on the one-dimensional base material to form a plane or a curved surface. 28. The display device according to claim 24, wherein the drive circuit of each light emitting element is formed using the one-dimensional substrate. [29] 半導体層又は絶縁層が表面に形成されさらに保護膜により被覆されたファイバを卷 き取り治具力 引き出し、  [29] A fiber having a semiconductor layer or an insulating layer formed on the surface and further coated with a protective film is scraped off, 前記巻き取り治具から引き出された前記保護膜を除去し、  Removing the protective film drawn from the winding jig, 前記ファイバのうち前記保護膜が除去された部分を必要な長さに切断して複数本 に分け、  A portion of the fiber from which the protective film has been removed is cut into a required length and divided into a plurality of pieces, 複数本の前記ファイバを環状面の外表面又は内表面の固定し、  Fixing a plurality of the fibers on the outer surface or inner surface of the annular surface; 前記環状面上の前記ファイバに能動素子、受動素子の少なくとも一方を形成する ことを特徴とするデバイス製造方法。  A device manufacturing method, wherein at least one of an active element and a passive element is formed on the fiber on the annular surface. [30] 前記環状面は、円柱、多角柱の表面、筒の内面のいずれかであることを特徴とする 請求項 29に記載のデバイス製造方法。 [30] The annular surface is any one of a cylinder, a surface of a polygonal column, and an inner surface of a cylinder. 30. The device manufacturing method according to claim 29. [31] 前記環状面には前記ファイバ上にプロセスヘッドを配置して、前記環状面を回転させ て順次前記ファイバに一次元的に膜を成長させる工程を有することを特徴とする請 求項 29又は請求項 30に記載のデバイス製造方法。 [31] The process of claim 29, further comprising a step of disposing a process head on the fiber on the annular surface and rotating the annular surface to sequentially grow a film on the fiber in a one-dimensional manner. The device manufacturing method according to claim 30. [32] 前記フアイバは前記環状面に固定された状態で成膜雰囲気に置かれる工程を有す ることを特徴とする請求項 29乃至請求項 31のいずれか 1つに記載のデバイス製造 方法。 32. The device manufacturing method according to claim 29, further comprising a step of placing the fiber in a film forming atmosphere in a state of being fixed to the annular surface. [33] 前記ファイバ上にプロセスヘッドを配置して、前記環状面を回転させて順次前記ファ ィバにレジストを塗布する工程を有することを特徴とする請求項 29乃至請求項 31の [33] The method of claim 29, further comprising a step of disposing a process head on the fiber and rotating the annular surface to sequentially apply a resist to the fiber. V、ずれか 1つに記載のデバイス製造方法。 The device manufacturing method according to one of V and Missing. [34] 前記ファイバ上に露光装置のレンズ系を配置して、前記環状面を回転させて順次前 記ファイバ上の前記レジストを露光する工程を有することを特徴とする請求項 33に記 載のデバイス製造方法。 34. The method according to claim 33, further comprising a step of arranging a lens system of an exposure apparatus on the fiber and rotating the annular surface to sequentially expose the resist on the fiber. Device manufacturing method. [35] 前記ファイバは前記環状面とともに溶液に浸漬されてゥヱット処理がなされる工程を 有することを特徴とする請求項 29乃至請求項 34のいずれか 1つに記載のデバイス 製造方法。 [35] The device manufacturing method according to any one of [29] to [34], wherein the fiber has a step of being wet-treated by being immersed in a solution together with the annular surface. [36] 半導体層又は絶縁層が表面に形成されさらに保護膜により被覆されたファイバを卷 き取り治具力 引き出し、  [36] A fiber having a semiconductor layer or an insulating layer formed on the surface and coated with a protective film is scraped off, and the jig force is drawn. 前記巻き取り治具から引き出された前記保護膜を除去し、  Removing the protective film drawn from the winding jig, 前記ファイバのうち前記保護膜が除去された部分を必要な長さに切断して複数本 に分け、  A portion of the fiber from which the protective film has been removed is cut into a required length and divided into a plurality of pieces, 複数本の前記ファイバを互いに間隔をおいて固定治具に取り付け、  A plurality of the fibers are attached to a fixing jig at intervals, 前記固定治具に固定された前記ファイバに能動素子、受動素子の少なくとも一方 を形成する  At least one of an active element and a passive element is formed on the fiber fixed to the fixing jig. ことを特徴とするデバイス製造方法。  A device manufacturing method.
PCT/JP2004/013773 2003-09-19 2004-09-21 Semiconductor device, display device, and device manufacturing method WO2006022036A1 (en)

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Cited By (3)

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JP2010015775A (en) * 2008-07-02 2010-01-21 Furukawa Electric Co Ltd:The Manufacturing method of fiber substrate junction element, and fiber substrate junction element
JP2010015776A (en) * 2008-07-02 2010-01-21 Furukawa Electric Co Ltd:The Manufacturing method of fiber substrate junction element, and fiber substrate junction element
JP2013089753A (en) * 2011-10-18 2013-05-13 Nippon Hoso Kyokai <Nhk> Thin film transistor, thin film transistor array substrate, flexible display element, flexible display device, and manufacturing method of thin film transistor array substrate

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JP2002184580A (en) * 2000-08-17 2002-06-28 General Electric Co <Ge> Oled fiber light source
JP2002258775A (en) * 2001-03-05 2002-09-11 Matsushita Electric Ind Co Ltd Translucent conductive wire-shaped material, fibrous phosphor and woven fabric type display device
JP2003174171A (en) * 2001-12-06 2003-06-20 Sharp Corp Function line, transistor array using the same, active matrix substrate, display device, semiconductor device, and method for manufacturing transistor array and active matrix substrate
JP2004258206A (en) * 2003-02-25 2004-09-16 Kenkichi Suzuki Active matrix type led display apparatus and its element

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JP2002184580A (en) * 2000-08-17 2002-06-28 General Electric Co <Ge> Oled fiber light source
JP2002258775A (en) * 2001-03-05 2002-09-11 Matsushita Electric Ind Co Ltd Translucent conductive wire-shaped material, fibrous phosphor and woven fabric type display device
JP2003174171A (en) * 2001-12-06 2003-06-20 Sharp Corp Function line, transistor array using the same, active matrix substrate, display device, semiconductor device, and method for manufacturing transistor array and active matrix substrate
JP2004258206A (en) * 2003-02-25 2004-09-16 Kenkichi Suzuki Active matrix type led display apparatus and its element

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010015775A (en) * 2008-07-02 2010-01-21 Furukawa Electric Co Ltd:The Manufacturing method of fiber substrate junction element, and fiber substrate junction element
JP2010015776A (en) * 2008-07-02 2010-01-21 Furukawa Electric Co Ltd:The Manufacturing method of fiber substrate junction element, and fiber substrate junction element
JP2013089753A (en) * 2011-10-18 2013-05-13 Nippon Hoso Kyokai <Nhk> Thin film transistor, thin film transistor array substrate, flexible display element, flexible display device, and manufacturing method of thin film transistor array substrate

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