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WO2006017874A3 - Cache d'instruction pour systemes fonctionnant en temps reel - Google Patents

Cache d'instruction pour systemes fonctionnant en temps reel Download PDF

Info

Publication number
WO2006017874A3
WO2006017874A3 PCT/AT2005/000326 AT2005000326W WO2006017874A3 WO 2006017874 A3 WO2006017874 A3 WO 2006017874A3 AT 2005000326 W AT2005000326 W AT 2005000326W WO 2006017874 A3 WO2006017874 A3 WO 2006017874A3
Authority
WO
WIPO (PCT)
Prior art keywords
instruction cache
real
wcet
cache memory
time systems
Prior art date
Application number
PCT/AT2005/000326
Other languages
German (de)
English (en)
Other versions
WO2006017874A2 (fr
Inventor
Martin Schoeberl
Original Assignee
Martin Schoeberl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Martin Schoeberl filed Critical Martin Schoeberl
Priority to AT0932505A priority Critical patent/AT505203A5/de
Publication of WO2006017874A2 publication Critical patent/WO2006017874A2/fr
Publication of WO2006017874A3 publication Critical patent/WO2006017874A3/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30054—Unconditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
    • G06F9/4482—Procedural
    • G06F9/4484—Executing subprograms

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

Dans les systèmes fonctionnant en temps réel, la connaissance du temps d'exécution maximal (en anglais, Worst Case Execution Time WCET) revêt une importance capitale. L'influence du cache d'instruction sur ce WCET est difficile à prévoir dans les configurations classiques et mène à des valeurs de WCET pessimistes. L'invention concerne un cache d'instruction (103) pour un processeur (100) qui permet de parvenir à une prédicabilité plus précise du comportement en temps réel. Le cache d'instruction est chargé avec des fonctions complètes et regroupe tous les 'ratés de cache' en cas de demande de fonction et de retour de fonction. L'analyse du comportement de cache se trouve de ce fait réduite à l'analyse de 'l'arbre d'appel'.
PCT/AT2005/000326 2004-08-17 2005-08-12 Cache d'instruction pour systemes fonctionnant en temps reel WO2006017874A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT0932505A AT505203A5 (de) 2004-08-17 2005-08-12 Instruction cache für echtzeitsysteme

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
AT0138304A AT500858B8 (de) 2004-08-17 2004-08-17 Instruction cache für echtzeitsysteme
ATA1383/2004 2004-08-17

Publications (2)

Publication Number Publication Date
WO2006017874A2 WO2006017874A2 (fr) 2006-02-23
WO2006017874A3 true WO2006017874A3 (fr) 2006-11-23

Family

ID=35134456

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/AT2005/000326 WO2006017874A2 (fr) 2004-08-17 2005-08-12 Cache d'instruction pour systemes fonctionnant en temps reel

Country Status (2)

Country Link
AT (2) AT500858B8 (fr)
WO (1) WO2006017874A2 (fr)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4755935A (en) * 1986-01-27 1988-07-05 Schlumberger Technology Corporation Prefetch memory system having next-instruction buffer which stores target tracks of jumps prior to CPU access of instruction
US5197131A (en) * 1988-02-10 1993-03-23 Hitachi, Ltd. Instruction buffer system for switching execution of current instruction to a branch or to a return from subroutine
US5490262A (en) * 1989-09-01 1996-02-06 Oki Electric Industry Co., Ltd. Dual cache memory device with cache monitoring
WO1997036234A1 (fr) * 1996-03-28 1997-10-02 International Business Machines Corporation Mecanisme de contacts multiblocs d'antememoire pour les systemes orientes objet
US5893142A (en) * 1996-11-14 1999-04-06 Motorola Inc. Data processing system having a cache and method therefor
WO2003065204A1 (fr) * 2002-02-01 2003-08-07 Philips Semiconductors Dresden Ag Procede pour traiter des instructions

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9118312D0 (en) * 1991-08-24 1991-10-09 Motorola Inc Real time cache implemented by dual purpose on-chip memory
US5353425A (en) * 1992-04-29 1994-10-04 Sun Microsystems, Inc. Methods and apparatus for implementing a pseudo-LRU cache memory replacement scheme with a locking feature
US5974534A (en) * 1994-02-14 1999-10-26 Hewlett-Packard Company Predecoding and steering mechanism for instructions in a superscalar processor
US5913224A (en) * 1997-02-26 1999-06-15 Advanced Micro Devices, Inc. Programmable cache including a non-lockable data way and a lockable data way configured to lock real-time data
US6157981A (en) * 1998-05-27 2000-12-05 International Business Machines Corporation Real time invariant behavior cache
US7143268B2 (en) * 2000-12-29 2006-11-28 Stmicroelectronics, Inc. Circuit and method for instruction compression and dispersal in wide-issue processors

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4755935A (en) * 1986-01-27 1988-07-05 Schlumberger Technology Corporation Prefetch memory system having next-instruction buffer which stores target tracks of jumps prior to CPU access of instruction
US5197131A (en) * 1988-02-10 1993-03-23 Hitachi, Ltd. Instruction buffer system for switching execution of current instruction to a branch or to a return from subroutine
US5490262A (en) * 1989-09-01 1996-02-06 Oki Electric Industry Co., Ltd. Dual cache memory device with cache monitoring
WO1997036234A1 (fr) * 1996-03-28 1997-10-02 International Business Machines Corporation Mecanisme de contacts multiblocs d'antememoire pour les systemes orientes objet
US5893142A (en) * 1996-11-14 1999-04-06 Motorola Inc. Data processing system having a cache and method therefor
WO2003065204A1 (fr) * 2002-02-01 2003-08-07 Philips Semiconductors Dresden Ag Procede pour traiter des instructions

Also Published As

Publication number Publication date
AT500858B8 (de) 2007-02-15
AT500858B1 (de) 2006-04-15
AT505203A5 (de) 2008-11-15
AT500858A4 (de) 2006-04-15
WO2006017874A2 (fr) 2006-02-23

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