WO2006013664A1 - 半導体パッケージ,その製造方法及び半導体デバイス - Google Patents
半導体パッケージ,その製造方法及び半導体デバイス Download PDFInfo
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- WO2006013664A1 WO2006013664A1 PCT/JP2005/008697 JP2005008697W WO2006013664A1 WO 2006013664 A1 WO2006013664 A1 WO 2006013664A1 JP 2005008697 W JP2005008697 W JP 2005008697W WO 2006013664 A1 WO2006013664 A1 WO 2006013664A1
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- Prior art keywords
- sealing body
- lead
- leads
- area
- semiconductor package
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 99
- 238000000034 method Methods 0.000 title abstract description 54
- 238000007789 sealing Methods 0.000 claims abstract description 173
- 238000004080 punching Methods 0.000 claims abstract description 36
- 238000000465 moulding Methods 0.000 claims abstract description 26
- 238000005520 cutting process Methods 0.000 claims description 55
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims description 40
- 238000004519 manufacturing process Methods 0.000 claims description 33
- 239000012778 molding material Substances 0.000 claims description 3
- 238000009434 installation Methods 0.000 claims 2
- 244000126211 Hericium coralloides Species 0.000 claims 1
- 230000008569 process Effects 0.000 description 49
- 239000011347 resin Substances 0.000 description 31
- 229920005989 resin Polymers 0.000 description 31
- 238000005452 bending Methods 0.000 description 21
- 230000003287 optical effect Effects 0.000 description 9
- 239000000919 ceramic Substances 0.000 description 8
- 238000003384 imaging method Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 5
- 239000011521 glass Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000010008 shearing Methods 0.000 description 2
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- 244000017020 Ipomoea batatas Species 0.000 description 1
- 235000002678 Ipomoea batatas Nutrition 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 235000009508 confectionery Nutrition 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000003449 preventive effect Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
Definitions
- the present invention relates to a semiconductor package made of resin or ceramic, on which an LSI chip, a solid-state imaging device, a light emitting / receiving device, etc. are mounted, a method of manufacturing the same, and a semiconductor device.
- a lead frame having leads and a dam bar connecting each lead is sandwiched between a lower mold and an upper mold in a molding die in a region adjacent to a cavity. It is done by molding a sweet ceramic within the cavity.
- Patent Document 1 As shown in FIG. 2 of the same publication, by cutting a dam bar using a resin cut die provided with an elastic body, residual resin can be obtained together with the dam bar. I try to drop it.
- Patent Document 1 Japanese Patent Application Laid-Open No. 7-193095
- Patent Document 2 Japanese Patent Application Laid-Open No. 2003-17643 Disclosure of the invention
- the semiconductor package has an overhang structure larger than that of the partial force sealing body above the lead of the sealing body and the portion below the lead of the sealing body.
- FIG. 13 is a cross-sectional view showing the structure of an optical device provided with a semiconductor package having a conventional overhang structure. However, the left end of FIG. 13 shows the structure of the cross section passing through the resin part between the leads, and the right end of FIG. 13 shows the structure of the cross section passing through the lead.
- the optical device includes an optical chip 101 such as a solid-state imaging device, a light emitting / receiving element, an LSI, a lead 102 for exchanging signals between the optical chip 101 and an external device, and a semiconductor
- an optical chip 101 such as a solid-state imaging device, a light emitting / receiving element, an LSI, a lead 102 for exchanging signals between the optical chip 101 and an external device, and a semiconductor
- a thin metal wire 107 for connecting the chip 101 and the lead 102, a rectangular sealing body 103 for sealing the lead 102, and a lid member such as a glass window, a hologram, a ceramic lid or the like attached to the upper surface of the sealing body 103. It has 105.
- the portion of the sealing body 103 surrounding the lead 102 is a sealing body upper portion 103a located on the upper surface side of the lead 102, a sealing body lower portion 103b located on the lower surface side of the lead 102, and sealing. It is divided into a lead side area 103c which is sandwiched by the lower part 103b and the upper part 103a of the sealing body and fills the gap between the leads.
- the sealing body 103 is integrally formed by the resin poured at the time of molding. It is formed.
- the lid member 105 is attached to the upper surface of the sealing body upper portion 103a, and the optical chip 101 is attached to the central portion of the sealing body lower portion 103b. That is, the optical chip 101 is disposed in the internal space 106 surrounded by the upper part 103 a of the sealing body, the lower part 103 b of the sealing body, the lead side area 103 c and the glass window 105.
- a region Rd of the outer lead 102b shown at the left end of FIG. 13 indicates a portion where the diver is removed. Further, although not shown in FIG. 13, immediately after the molding process, there is a portion (residual resin) which is a part of the side region 103 c of the lead and protrudes outside the upper portion 103 a of the sealing body. is there. And, at the time of cutting the dam bar (partial punching process), Of the lead side regions 103c that were present immediately after the completion of the lead process, the region projecting laterally beyond the overhanging portion of the sealing body upper portion 103a is removed together with the dam bar.
- the tip end region Rb of the lead side region 103c located below the sealing body upper portion 103a remains without being removed, the tip end region Rb falls off when the lead 102 is bent. There is a risk of Then, after the lead 102 is bent, the optical chip 101 is attached to the lower part 103b of the sealing body, wire bonding, attachment of the glass window 105, and so on. There is a problem that when it enters the space 106 of the cage / cage body, it causes malfunction of the optical device.
- An object of the present invention is to provide a highly reliable semiconductor package, a method of manufacturing the same, and a semiconductor device by suppressing the dropping of the mold material inside the dam bar in the overhang type semiconductor package.
- the area around the lead in the sealing body is located on the lower side of the sealing body located on the lower surface side of the lead and on the upper surface side of the lead, Divide into the upper part of the sealing body that hangs up from the bottom of the stopper body and the lead side area that fills the gap between the leads, and incline the outer side face of the lead side area downward and inward,
- the width of the tip area of the lead side area protruding from the lower portion of the sealing body is 1Z5 of the overhang amount of the upper portion of the sealing body.
- the area around the lead in the sealing body is located on the lower side of the sealing body located on the lower surface side of the lead and on the upper surface side of the lead, In the upper part of the sealing body, which is one bar-hanging from the lower part of the stopper body, and the lead side area which fills the gap between the leads.
- the outer side surface of the lead side area is inclined inward toward the lower side, and the seal lower portion force of the lead side area is brought into contact with the bent area of the outer lead so as to contact the outer lead. It is something like that.
- the first or second semiconductor device of the present invention is a semiconductor device having a semiconductor chip and a semiconductor package for housing the semiconductor chip, wherein the structure of the semiconductor package is the same as the first or second semiconductor described above. It is a package structure.
- the area around the lead is located on the lower surface side of the sealing body and the upper surface side of the lead by the molding process, and a part of the sealing body is located on the upper surface side of the lead.
- the structure of the first or second semiconductor package is obtained.
- the load applied to the pedestal can be reduced by using a punch whose edge angle on the lead side region side of the sealing body is in the range of 95 ° to 120 °. It is possible to prevent the breakage of the platform.
- the strength of the pedestal is ensured by using a comb-like pedestal projecting to the dam bar side. Can be maintained to prevent damage to the cradle.
- a lower mold provided with a convex portion having an outer side in contact with the dam bar and an inner side inclined upward with a force directed upward, and a lower mold Using the upper mold sandwiching the lead frame between them and molding at least the respective portions between the tips and the proximal ends of the plurality of leads distal to the dam bar by the molding material having the above. is there.
- the structure of the first or second semiconductor package can be obtained.
- the semiconductor package of the present invention provides a highly reliable semiconductor package or semiconductor device with few defects due to debris of the mold material.
- FIG. 1 is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention.
- FIGS. 2 (a) and 2 (b) are a perspective view and a cross-sectional view showing the structure of the semiconductor package when the molding step in the first embodiment is completed.
- FIGS. 3 (a) and 3 (b) are a perspective view and a sectional view of an individual semiconductor package formed in the partial punching process of the first embodiment.
- FIG. 4 is a cross-sectional view showing only the semiconductor package when the lead bending process in the first embodiment is finished.
- FIGS. 5 (a) and 5 (b) respectively show the structure of the cradle and the punch used in the conventional partial punching process, and the cradle and the pedestal used in the partial punching process of the first embodiment. It is a fragmentary sectional view showing the structure of a punch.
- FIGS. 6 (a) to 6 (d) are a partial sectional view of the semiconductor package in the conventional manufacturing process, a partial back view before lead bending, a partial perspective view after lead bending, and a lead bend, respectively.
- (e) to (h) are a partial sectional view of the semiconductor package in the manufacturing process of the first embodiment, a partial rear view before lead bending, and a part after lead bending, respectively. It is a perspective view, and a partial reverse view after lead bending.
- FIG. 7 is a partial cross-sectional view for explaining an appropriate range of the width of the lower surface of the end region of the lead side region of the sealing body in the first embodiment.
- FIG. 8 is a view showing a change of a cutting load with respect to the resin side cutting edge angle of the punch in the first embodiment.
- Figs. 9 (a) and 9 (b) are partial sectional views of a sealing body, a die and a pedestal for explaining the relationship between the planar shape of the cutting edge of the pedestal and the shape of the lead frame, and Figs. Is a plan view of the platform
- FIG. 10 Figs. 10 (a) and 10 (b) show a pedestal and a die and a seal used in the conventional partial punching process. It is the top view which shows the positional relationship with a stop, and sectional drawing in the Xb-Xb line which shows the state at the time of lead side field fall, (c), (d) is the partial punching process of 1st Embodiment.
- FIG. 16 is a plan view showing the positional relationship between the pedestal and die used in and the sealing body, and a cross-sectional view taken along the line Xd-Xd showing the state when the lead lateral region is dropped.
- FIGS. 11 (a) and 11 (b) are a perspective view and a plan view showing only the structure in the vicinity of the diversity of the lower mold of the molding die in the second embodiment.
- FIGS. 12 (a) and 12 (b) are partial cross-sectional views showing the positional relationship between the mold and the lead frame in the molding step of the second embodiment, and a sealing body immediately after the molding step is completed. It is a fragmentary sectional view showing structure.
- FIG. 13 is a cross-sectional view showing the structure of an optical device provided with a semiconductor package having a conventional overhang structure.
- FIG. 1 is a cross-sectional view showing the structure of a semiconductor device 1 according to a first embodiment of the present invention. However, at the left end of Fig. 1, the structure of the cross section passing through the resin part between the leads is shown, and at the right end of Fig. 1, the structure of the cross section passing through the lead is shown.
- the semiconductor device 1 includes a semiconductor chip 11 such as a solid-state imaging device, a light emitting / receiving element, an LSI, a lead 12 for exchanging signals between the semiconductor chip 11 and an external device, and a semiconductor chip.
- a thin metal wire 17 which is an electrical connection member for connecting the lead 12 and the lead 12, a rectangular sealing body 13 for sealing the lead 12, a glass window attached to the upper surface of the sealing body 13, a hologram lamp,
- a lid member 15 such as a ceramic lid is provided.
- the portions (specifically, two side regions) of the sealing body 13 around the lead 12 are located on the upper surface 13 a of the sealing body located on the upper surface side of the lead 12 and the lower surface side of the lead 12. It is divided into a sealing body lower portion 13b and a lead side area 13c which is sandwiched by the sealing body lower portion 13b and the sealing body upper portion 13a and which fills the gap between the leads.
- the sealing body 13 which is not melted is a resin poured at the time of molding. Are integrally formed.
- the lid member 15 is attached to the upper surface of the sealing body upper portion 13a, and the semiconductor chip 11 is attached to the central portion of the sealing body lower portion 13b. That is, the semiconductor chip 11 is disposed in the internal space 16 surrounded by the upper part 13 a of the sealing body, the lower part 13 3 of the sealing body, and the lid member 15.
- an inner lead 12 a a portion of the lead 12 sealed by the sealing body 13 and a portion exposed in the internal space 16 are referred to as an inner lead 12 a, and the lead 12 is outside the sealing body 13.
- the portion protruding in the direction is called an outer lead 12b.
- the semiconductor package 2 is constituted by the lead 12, the upper sealing body 13a, the lower sealing body 13b, and the lead lateral region 13c, and the semiconductor package 2 is provided with the semiconductor chip 11,
- the semiconductor device 1 is configured by attaching the thin metal wire 17 and the lid member 15.
- a region Rd of the outer lead 12b shown at the left end of FIG. 1 shows a portion from which the dam bar is removed.
- a part which is a part of the lead side area 13c and which protrudes outside the sealing body upper part 13a is not shown in FIG. 1, immediately after the molding process, there is a part which is a part of the lead side area 13c and which protrudes outside the sealing body upper part 13a.
- the sealing body is included in the lead side area 13c that was present immediately after the end of the molding process. Not only the region projecting laterally beyond the overhanging portion of the upper portion 13a, but also a portion of the portion positioned directly under the overhanging portion of the sealing body upper portion 13a is removed together with the dam bar, as a result,
- the side surface of the tip end region Ra of the side region 13c is an inclined surface Fal that is greatly inclined so as to move downward and enter inside.
- FIGS. 2 (a) and 2 (b) are a perspective view and a cross-sectional view showing the structure of the semiconductor package when the molding process is completed.
- the left end of FIG. 2 (b) shows a cross section not passing through the lead, and the right end of FIG. 2 (b) shows a cross section passing through the lead. Note that the dimensions in Fig. 2 (a) and Fig. 2 (b) are not the same.
- the lead frame 20 is made of mold resin. Between the upper sealing body 13 a and the lower sealing body 13 b. However, as described above, since there is a clear boundary between the upper sealing body 13a and the lower sealing body 13b, the sealing body 13 is integrally formed by the resin poured at the time of molding. It is
- a lead inside the dam bar 20c is called an inner lead 20a
- a lead outside the dam bar 20c is called an outer lead 20b.
- a lead side area 13c of the sealing body 13 exists between a portion of the inner lead 20a that protrudes laterally from the lower portion 13b of the sealing body and the dam bar 20c.
- the lead frame 20 is provided with a large number of sealing body forming areas. Further, the upper surface of the end portion of the inner lead 20a is exposed inside the lower portion 13b of the sealing body, and wire bonding is performed on the exposed portion.
- a part of the dam bar 20c and the lead side area 13c is partially punched out and partially punched out).
- a pedestal 30, a punch 31 and a die 32 as shown in FIGS. 10 (b) and 10 (c) are used.
- wire bonding or wire bonding and attachment of the lid member are performed, and then the tip of the outer lead is separated from the lead frame main body force, and the lead along the side of the sealing body where the lead is not provided.
- the individual semiconductor packages are also separated by leadframe force by cutting the frame (final punching step).
- FIGS. 3 (a) and 3 (b) are a perspective view and a cross-sectional view of an individual semiconductor package formed in a partial punching process.
- the left end of Fig. 3 (b) shows the cross section not passing through the lead, and the right end of Fig. 3 (b) shows the cross section passing through the lead.
- the scale of Fig. 3 (a) and Fig. 3 (b) are not the same.
- the dam bar 20c is removed together with the lead side area 13c so that the leads are separated and independent from each other.
- the portion of the lead 12 embedded in the sealing body 13 and the partial force inner lead 12 a inside the sealing body 13 are referred to as outer leads from the sealing body 13.
- This portion is called outer lead 12b. That is, since the dam bar is eliminated, the boundary between the outer lead 12b and the inner lead 12a is different from the boundary in the lead frame.
- the sealing body shown in FIGS. 2 (a) and 2 (b) By shearing the lead side area 13c of the lower portion 13b diagonally between the cutting edge of the punch and the cutting edge of the receiving stand, a portion of the lead side area 13c that protrudes outward beyond the sealing body upper portion 13a And a portion of the portion directly under the overhang portion of the sealing body upper portion 13a. Therefore, the side surface of the tip region Ra of the lower sealing body portion 13b sandwiched between the outer leads 12b is an inclined surface Fal inclined downward and directed inward.
- the outer lead 12b is bent downward and finished into a shape that can be mounted on the mother substrate of the semiconductor package 2 (lead bend step).
- FIG. 4 is a cross-sectional view showing only the semiconductor package when the lead bend process is completed.
- the left end of Fig. 4 shows the cross section not passing through the lead, and the right end of Fig. 4 shows the cross section passing through the lead.
- the tip area Ra of the lower portion 13b of the sealing body which is a part of the side area of the lead, is adjusted between the outer leads 12b by adjusting the width of the pedestal. It is sheared diagonally, and there is almost no lead lateral area on the side of the bent portion of the outer lead 12b. Therefore, generation of debris in the lead lateral area in the lead bending process can be suppressed. This can prevent the deterioration of the reliability of semiconductor devices due to debris.
- a semiconductor chip 11 such as a solid-state imaging device, a light emitting / receiving element, or an LSI is placed on the bottom of the recess in the lower portion 13b of the sealing body before the lead bend process.
- a part (electrode pad) of the semiconductor chip 11 and the inner lead 12a are connected (wire bonding step).
- the semiconductor device shown in FIG. 1 is formed by fixing the lid member 15 with an adhesive on the upper surface of the upper part 13a of the sealing body.
- a lead bend process may be performed to form the semiconductor package shown in FIG.
- the lead bend process may be performed. Even in this case, if the debris is scattered to the equipment used in the manufacturing process, the debris infiltrates before attaching the lid member to the other semiconductor package. It can improve.
- FIGS. 5 (a) and 5 (b) respectively show the structures of a pedestal and a punch used in the conventional partial punching process, and the structures of the pedestal and the punch used in the partial punching process of this embodiment, respectively.
- FIG. 5 (a) and 5 (b) respectively show the structures of a pedestal and a punch used in the conventional partial punching process, and the structures of the pedestal and the punch used in the partial punching process of this embodiment, respectively.
- the pedestal 130 used in the conventional partial punching process has a seal for the punch 131 although it generally has the clearance required in the partial punching process. It has an outer side at a position approximately close to the side of the upper portion 103a, and an inner side at a position substantially close to the side of the lower portion 103b of the seal (not shown on the die). Therefore, the width Wb of the upper surface of the pedestal 130 has a value close to the overhang amount of the upper portion 103a of the sealing body.
- the sheared surface of the lead side area 103c is formed substantially along the vertical direction, so removal of the lead side area 103c is carried out.
- the portion to be formed is almost only a portion projecting outward beyond the upper portion 103a of the sealing body.
- the tip end region Rb directly below the overhanging portion of the upper part 103 a of the sealing body is almost left as it is.
- the pedestal 30 used in the present embodiment has an outer side surface at a portion where the side force of the upper portion 13a of the sealing body is also retracted as much as possible. It has an inner side almost close to the side of the lower part 13b. Therefore, the width Wa of the upper surface of the pedestal 30 has a value that is significantly smaller than the overhang amount of the sealing body upper portion 13a.
- the sheared surface of the lead side area 13c is between the lower end portion of the outer side surface of the sealing body upper portion 13a and the cutting edge of the punch 31.
- the tip end area Ra of the lead side area 13c located directly under the overhanging portion of the sealing body upper part 13a has an inclined surface Fal directed downward and inclined inward. doing.
- the resin side cutting edge angle of the punch is 90 °. May be However, by using the punch 31 with the resin side cutting edge angle ⁇ larger than 90 °, it is possible to reduce the load applied simultaneously when cutting the dam bar 20c and the lead side area 13c.
- FIGS. 6 (a) to 6 (d) are a partial sectional view of the semiconductor package in the conventional manufacturing process, a partial rear view before lead bending, a partial perspective view after lead bending, and a lead bend, respectively.
- 6 (e) to 6 (h) are a partial sectional view of the semiconductor package in the manufacturing process of this embodiment, a partial rear view before lead bending, and a partial perspective view after lead bending, respectively.
- 4 is a partial reverse side view after lead bending.
- FIG. 7 is a partial cross-sectional view for explaining an appropriate range of the width B of the lower surface Fa2 of the distal end region Ra.
- FIG. 7 an appropriate range of the width B of the lower surface Fa2 of the tip end region Ra shown in FIG. 5 (b) will be described.
- the tip of the lower surface Fa2 of the tip region Ra is located inside the bending start portion of the outer lead 12b.
- the inner radius of curvature R of the outer lead 12b is typically between 0.1 mm and 0.3 mm to minimize springback. Further, depending on the thickness of the outer lead 12b, if it is forcibly bent with a small radius of curvature, a crack may occur in the layer near the outer surface of the outer lead 12b. In the lead bend process while preventing these Calculate the width B of the lower surface Fa2 to avoid debris.
- Lead thickness 0.15 mm to 0.25 mm
- Inner radius of curvature R 0. lmm to 0.3 mm
- the bending start position of the lower surface Fa2 is, by design,
- the width B of the lower surface Fa2 is because it only goes inside the overhang position.
- the minimum value of B is 0.1145 mm if this value is added with the mold displacement amount (process variation) of 0.05 mm.
- the width B of the lower surface Fa2 of the tip region Ra is 80% at the maximum and 28% at the minimum with respect to the overhang amount A. That is, the appropriate range of width B is
- the blade width Wa of the pedestal 30 shown in FIG. 5 (b) needs to be about 0.1 mm. .
- the mechanical strength of the cutting edge of the receiving stand 30 is reduced, and there is a risk of breakage in the partial punching process.
- the load at the time of cutting is reduced by devising the resin side cutting edge angle of the punch, and the cutting edge surface of the pedestal.
- the edge strength is strengthened by devising the plane shape of
- the edge angle on the resin side of the punch 31 is set to approximately 90 °, the load is simultaneously applied to the entire front end face of the punch 31 and the cutting load is large relative to the receiving stand 30 where the cutting load is large. If it is added, the pedestal 30 may be damaged.
- the resin side cutting edge angle ⁇ of the punch 31 is made larger than 90 °, and the cutting edge of the punch 31 bites into the lead frame from the outside and gradually By cutting, the contact area between the instantaneous punch 31 and the lead frame can be reduced, so that the cutting load can be greatly reduced.
- FIG. 8 is a diagram showing a change in cutting load with respect to the resin side cutting edge angle of the punch.
- the load can be reduced.
- the cutting load can be reduced in the range of 95 ° to 120 °.
- the resin side cutting edge angle is in the range of 95 ° or more and 102 ° or less, a more preferable result is obtained that the yield is particularly high.
- the cutting edge of the punch 31 is dam bar 2 first.
- the dam bar 20c and the lead side area 13c lower as shown in FIG. 5 (b). Due to the bending action, a shear surface is formed between the lower end of the outer surface of the upper seal 13 a and the blade tip of the pedestal 30. Therefore, it is possible to reliably prevent the generation of uncut parts that will later become debris. Even in the case where the distance between the cutting edge of the receiving stand 30 of the present embodiment and the cutting edge of the punch 31 is large, there is an advantage that a stable shearing surface can be formed between the cutting edges during cutting.
- 9 (a) and 9 (b) are partial sectional views of a sealing body, a die and a pedestal, and a plan view of the pedestal for explaining the relationship between the planar shape of the cutting edge of the pedestal and the shape of the lead frame. It is.
- the cutting edge of the pedestal 30 is a convex 30a in the area contacting the inner lead 20a of the lead frame, and is concave in the area contacting the lead side area 13c. It becomes department 30b. That is, the cutting edge of the receiving table 30 has a comb-like planar shape. Then, the cutting edge width in the recess 30 b is about 0.1 mm, and the cutting edge width in the protrusion 30 a is 0.2 mm or more. The outer side surface of the convex portion 30a of the cradle 30 and the 32nd outer side surface are in contact with each other.
- the cradle 30 can be configured using a cemented carbide material excellent in wear resistance. That is, while cemented carbide materials are hard and excellent in wear resistance, they have the property of being brittle and easily chipped, and require a certain thickness to be applied to a part to which mechanical load is applied. Therefore, by adopting the structure shown in FIG. 9 (b), the wear resistance is improved, so that it is possible to stabilize the change with time of the initial cutting dimension and extend the life cycle of the part.
- cemented carbide materials are hard and excellent in wear resistance, they have the property of being brittle and easily chipped, and require a certain thickness to be applied to a part to which mechanical load is applied. Therefore, by adopting the structure shown in FIG. 9 (b), the wear resistance is improved, so that it is possible to stabilize the change with time of the initial cutting dimension and extend the life cycle of the part.
- 10 (a) and 10 (b) are plan views showing the positional relationship between the pedestal and die used in the conventional partial punching step and the sealing body, and the state when the lead side area is dropped.
- 10 (c) and 10 (d) are plan views showing the positional relationship between the pedestal and die used in the partial punching step of the present embodiment and the sealing body, and the leads, and FIGS.
- FIG. 7 is a cross-sectional view taken along the line Xd-Xd showing a state when the side area is dropped.
- the distance between the edge portions supporting the outer leads 120b and the dam bars 120c of the die 132 used conventionally is about 0.69 mm.
- the width of the punch 131 was 0.67 mm, in the case of such a structure of the die 132, the lead lateral region 103c may be clogged between the dies 132 or the natural drop may not be smoothly performed immediately. There is.
- the width of the die 32 of the present embodiment is reduced to 0.60 mm and 0.54 mm below the lead side area 13c.
- the distance between the edge portions supporting the outer leads 20b and the dam bars 20c of the die 32 is about 0.73 mm in the wide area, and the width of the punch 31 is 0.69 mm. . Therefore, as shown in FIG. 10 (d), in the case of the structure of the die 32 according to the present embodiment, natural side drop which makes the lead side area 13 c clogged between the dies 32 is performed smoothly.
- FIGS. 11 (a) and 11 (b) are a perspective view and a plan view showing only the structure of the vicinity of the likelihood of the lower mold of the mold according to the second embodiment.
- a dam block for filling the area surrounded by the inner leads of the lead frame and the dam bar on the side of the diversity 55 of the lower mold 50 of the molding die. 51 are provided.
- the inner surface 51a of this dam block 51 is the first real The inclined surface Fa of the tip end region Ra of the lower portion 13b of the sealing body described in the embodiment is inclined.
- FIGS. 12 (a) and 12 (b) are partial cross-sectional views showing the positional relationship between the mold and the lead frame in the molding step, and partial cross-sectional views showing the structure of the sealing body immediately after the molding step. .
- the outer surface 51b of the dam block 51 of the lower mold 50 is in contact with the dam bar 20c of the lead frame. With the upper end of the inner side surface 51a of the dam block 51 substantially aligned with the lower end of the inner side surface of the upper mold 52, molding of the ceramic is performed.
- the dimension in the width direction is set to a dimension smaller than the dimension between the leads by at least 0. 06 mm.
- the length of the upper surface of the dam block 51 is set to a length of 0.06 mm with respect to the dimension from the outer side surface of the sealing body upper portion 13a to the inner side surface of the dam bar 20c shown in FIG.
- the length of the lower surface of the dam block 51 is a dimension from the inner side surface of the dam bar 20c to a portion which is inside by 4Z5 of the overhang amount of the seal upper portion 13a.
- the height of the dam block 51 is set to the minus tolerance value of the thickness of the lead frame 20.
- an inclined surface Fal corresponding to the inner side surface 51a of the dam block 51 is formed in the end region Ra of the lower portion 13b of the sealing body 13 after the molding process.
- a flat lower surface Fa2 is formed corresponding to the portion received by the cutting edge of the pedestal in the first embodiment. That is, by the partial punching process in the first embodiment, the same structure as the structure when the lead side area is removed can be obtained.
- the same structure as the structure when the lead lateral region is removed can be obtained by the partial punching step in the first embodiment. Therefore, defects due to resin and ceramic debris can be prevented.
- the sealing body has a container-like shape and has an internal space
- the semiconductor device of the present invention also has a semiconductor chip and a thin metal wire surrounding the internal space.
- the present invention can also be applied to types filled with mold material. Even in the event that debris may adhere to equipment in the manufacturing process, it may cause various defects due to debris in the semiconductor device manufacturing process, but by applying the present invention And the mechanical failure can be reduced.
- the semiconductor package of the present invention a method of manufacturing the same, and a semiconductor device thereof can be used as a solid-state imaging device, a semiconductor device on which an LSI such as a light emitting / receiving device, a memory, or a logic is mounted, or a method of manufacturing the same.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/659,468 US7808096B2 (en) | 2004-08-06 | 2005-05-12 | Semiconductor package and production method thereof, and semiconductor device |
US12/869,172 US20100320614A1 (en) | 2004-08-06 | 2010-08-26 | Semiconductor package and production method thereof, and semiconductor device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004230712A JP4473674B2 (ja) | 2004-08-06 | 2004-08-06 | 半導体パッケージ及びその製造方法 |
JP2004-230712 | 2004-08-06 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US12/869,172 Continuation US20100320614A1 (en) | 2004-08-06 | 2010-08-26 | Semiconductor package and production method thereof, and semiconductor device |
Publications (1)
Publication Number | Publication Date |
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WO2006013664A1 true WO2006013664A1 (ja) | 2006-02-09 |
Family
ID=35786964
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2005/008697 WO2006013664A1 (ja) | 2004-08-06 | 2005-05-12 | 半導体パッケージ,その製造方法及び半導体デバイス |
Country Status (5)
Country | Link |
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US (2) | US7808096B2 (ja) |
JP (1) | JP4473674B2 (ja) |
CN (1) | CN100470768C (ja) |
TW (1) | TWI277188B (ja) |
WO (1) | WO2006013664A1 (ja) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4473674B2 (ja) * | 2004-08-06 | 2010-06-02 | パナソニック株式会社 | 半導体パッケージ及びその製造方法 |
JP2008124097A (ja) * | 2006-11-09 | 2008-05-29 | Shinko Electric Ind Co Ltd | 半導体装置用パッケージ及びその作製方法 |
KR101705700B1 (ko) * | 2010-07-01 | 2017-02-10 | 엘지이노텍 주식회사 | 발광 소자 |
CN102456806A (zh) * | 2010-10-26 | 2012-05-16 | 展晶科技(深圳)有限公司 | 发光二极管封装结构 |
US8487426B2 (en) * | 2011-03-15 | 2013-07-16 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with embedded die and manufacturing methods thereof |
JP6296687B2 (ja) | 2012-04-27 | 2018-03-20 | キヤノン株式会社 | 電子部品、電子モジュールおよびこれらの製造方法。 |
JP2013243340A (ja) * | 2012-04-27 | 2013-12-05 | Canon Inc | 電子部品、実装部材、電子機器およびこれらの製造方法 |
JP5885690B2 (ja) | 2012-04-27 | 2016-03-15 | キヤノン株式会社 | 電子部品および電子機器 |
JP2014207261A (ja) * | 2013-04-10 | 2014-10-30 | 株式会社デンソー | 半導体装置及びその製造方法 |
JP2015038920A (ja) * | 2013-08-19 | 2015-02-26 | ソニー株式会社 | 撮像装置および電子機器 |
EP4174931A4 (en) * | 2020-06-29 | 2024-07-03 | Kyocera Corporation | HOUSING FOR ACCOMMODATION OF AN ELECTRONIC ELEMENT, ELECTRONIC DEVICE AND ELECTRONIC MODULE |
US12002780B2 (en) * | 2020-11-12 | 2024-06-04 | Taiwan Semiconductor Manufacturing Company Ltd. | Package structure including a base and a lid disposed over the base and method of forming the package structure |
JP2023132777A (ja) * | 2022-03-11 | 2023-09-22 | キオクシア株式会社 | 半導体装置 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0722542A (ja) * | 1993-06-29 | 1995-01-24 | Hitachi Ltd | 半導体装置および半導体装置の実装構造 |
JP2002094035A (ja) * | 2000-09-14 | 2002-03-29 | Shinko Electric Ind Co Ltd | 光透過用キャップ及びその製造方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06120375A (ja) | 1992-10-06 | 1994-04-28 | Sony Corp | 半導体装置とその製造方法 |
JPH07193095A (ja) | 1993-12-27 | 1995-07-28 | Hitachi Ltd | リード間のはみ出しレジン除去方法 |
JP2003017643A (ja) | 2001-06-28 | 2003-01-17 | Hitachi Ltd | 半導体装置の製造方法および切断装置 |
JP2003197827A (ja) * | 2001-12-25 | 2003-07-11 | Toshiba Corp | 半導体装置およびその製造方法 |
JP3888228B2 (ja) * | 2002-05-17 | 2007-02-28 | 株式会社デンソー | センサ装置 |
JP4473674B2 (ja) * | 2004-08-06 | 2010-06-02 | パナソニック株式会社 | 半導体パッケージ及びその製造方法 |
-
2004
- 2004-08-06 JP JP2004230712A patent/JP4473674B2/ja not_active Expired - Fee Related
-
2005
- 2005-05-12 CN CN200580026424.4A patent/CN100470768C/zh not_active Expired - Fee Related
- 2005-05-12 US US11/659,468 patent/US7808096B2/en not_active Expired - Fee Related
- 2005-05-12 WO PCT/JP2005/008697 patent/WO2006013664A1/ja active Application Filing
- 2005-07-19 TW TW094124368A patent/TWI277188B/zh not_active IP Right Cessation
-
2010
- 2010-08-26 US US12/869,172 patent/US20100320614A1/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0722542A (ja) * | 1993-06-29 | 1995-01-24 | Hitachi Ltd | 半導体装置および半導体装置の実装構造 |
JP2002094035A (ja) * | 2000-09-14 | 2002-03-29 | Shinko Electric Ind Co Ltd | 光透過用キャップ及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN100470768C (zh) | 2009-03-18 |
TW200620606A (en) | 2006-06-16 |
JP2006049690A (ja) | 2006-02-16 |
US7808096B2 (en) | 2010-10-05 |
TWI277188B (en) | 2007-03-21 |
JP4473674B2 (ja) | 2010-06-02 |
CN101002317A (zh) | 2007-07-18 |
US20100320614A1 (en) | 2010-12-23 |
US20080132002A1 (en) | 2008-06-05 |
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