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WO2006009025A1 - Dispositif semiconducteur et procédé de fabrication de ce dispositif semiconducteur - Google Patents

Dispositif semiconducteur et procédé de fabrication de ce dispositif semiconducteur Download PDF

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Publication number
WO2006009025A1
WO2006009025A1 PCT/JP2005/012890 JP2005012890W WO2006009025A1 WO 2006009025 A1 WO2006009025 A1 WO 2006009025A1 JP 2005012890 W JP2005012890 W JP 2005012890W WO 2006009025 A1 WO2006009025 A1 WO 2006009025A1
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Prior art keywords
metal
semiconductor device
film
metal compound
heat treatment
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PCT/JP2005/012890
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English (en)
Japanese (ja)
Inventor
Masayuki Terai
Motofumi Saitoh
Ayuka Tada
Hirohito Watanabe
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Nec Corporation
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Priority to JP2006529077A priority Critical patent/JPWO2006009025A1/ja
Publication of WO2006009025A1 publication Critical patent/WO2006009025A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane

Definitions

  • the present invention relates to a semiconductor device having a high dielectric constant thin film and a method for manufacturing the semiconductor device, and more particularly, a MOSFET (Metal—Oxide—Semiconductor Field Effect Transistor) that realizes high performance and low power consumption. And a method for manufacturing the semiconductor device, in which the reliability of the gate insulating film constituting the semiconductor device is improved.
  • MOSFET Metal—Oxide—Semiconductor Field Effect Transistor
  • a silicon oxide film is useful as a gate insulating film material for a MOSFET because of its high process stability and excellent insulating properties.
  • the gate insulation film has become thinner with the miniaturization of devices, and for devices with a gate length of lOOnm or less, the required power of the scaling rule is also less than 2. Onm. It is necessary to be.
  • the tunnel current force flowing through the insulating layer when a gate bias is applied is a value that cannot be ignored with respect to the source Z drain current. Therefore, in order to improve the performance and power consumption of MOS FETs, the effective (electrical) gate insulating film thickness is reduced and the tunnel current is kept within the allowable range in device design. At present, research and development is actively underway.
  • nitrogen is added to the silicon oxide film to increase the dielectric constant and reduce the physical film thickness compared to pure silicon oxide film.
  • a method for forming such a silicon oxynitride film after forming an oxide film on the surface of the silicon substrate, nitrogen is introduced by performing high-temperature heat treatment in a nitrogen-containing gas such as ammonia (H).
  • a technique in which a silicon oxide film is exposed to elementary plasma and the surface side is selectively nitrided is being studied.
  • the relative dielectric constant of a pure silicon nitride film is about twice that of a silicon oxide film, it has a high dielectric constant due to nitrogen addition to the silicon oxide film. Has a limit and the relative permittivity It is impossible in principle to make it 10 or more.
  • Silicate materials in which silicon is mixed into these metal oxides are also considered as candidate materials because they have improved thermal stability although their relative permittivity is reduced. If these materials are used, it is possible to achieve a physical thickness that can reduce the tunnel current while maintaining the gate insulating film capacitance consistent with the scaling law even if the gate length is made fine.
  • the threshold voltage (VT) of the transistor changes during operation, making it difficult to ensure long-term stability of the output current of the transistor.
  • a high dielectric constant film is directly deposited on the surface of a silicon substrate, or an extremely thin (usually less than lnm) silicon oxide film is used.
  • an extremely thin (usually less than lnm) silicon oxide film is used.
  • a high dielectric constant film is deposited, and the reaction between the deposited high dielectric constant film and the base is suppressed as much as possible (see, for example, Patent Document 1).
  • the deposition method of high dielectric constant gate insulating film on the silicon substrate surface is mainly researched and developed using MOCVD (Metal Organic and Chemical Vapor Deposition) and ALCVD (Atomic Layer Chemical Vapor Deposition) equipment.
  • Metal oxide (or oxygen concentration is not excessive or deficient in the stoichiometric composition of the high dielectric constant film deposited by optimizing the deposition temperature and deposition sequence.
  • the conditions are set so as to coincide with the silicate composition because structural defects such as oxygen vacancies in the film are considered to be one of the causes of electron traps in the film.
  • a silicon oxide film is formed in advance on the surface of the silicon substrate, at least one kind of metal is ion-implanted into the formed silicon oxide film, and the injected metal is converted into silicon oxide by heat treatment.
  • a method for manufacturing a semiconductor device that diffuses into a film, has a good interface state with a semiconductor substrate, and has a good leak characteristic see, for example, Patent Document 2).
  • a semiconductor with excellent interfacial properties between a silicon substrate and a metal silicate layer which can contain metal atoms in the silicon oxide film as necessary and sufficiently to control, forms a metal silicate layer with a high dielectric constant
  • Patent Document 3 There is a device manufacturing method (see, for example, Patent Document 3).
  • Patent Document 1 Japanese Patent Laid-Open No. 2002-289844
  • Patent Document 2 JP 2002-314074 A
  • Patent Document 3 Japanese Patent Laid-Open No. 2001-332547
  • Non-Patent Document 1 A. Morioka et. All, ⁇ High Mobility MISFET with Low Trapped Charge in HfSiO FilmsJ, 2003 Symposium on VLSI Technological Digest oi fechnical Papers, p. Up 5
  • the silicon oxide film improves the interfacial thermal stability.
  • the relative dielectric constant of the silicon oxide film is low, It is considered important that the initial silicon oxide film formed on the substrate surface has a thickness of 0.6 nm or less.
  • Patent Document 2 described above is that when a metal is ion-implanted into a silicon oxide film, a defect is generated and the diffusion of the metal element cannot be controlled immediately during the heat treatment. It becomes.
  • Patent Document 3 described above controls metal atoms by suppressing diffusion due to a solid solution limit. Although it can be contained in the silicon oxide film with sufficient and sufficient properties, a metal silicate layer with a high dielectric constant will be formed, but there will be a region where metal atoms cannot be contained in the silicon oxide film. In such a case, there is a risk of causing characteristic deterioration.
  • the present invention has been made in view of the above circumstances, and enables the formation of a high-quality gate insulating film at the interface of a silicon substrate, and the manufacture of a semiconductor device and a semiconductor device with improved interface electrical characteristics It is intended to provide a method.
  • the present invention has the following features.
  • a semiconductor device is a semiconductor device having a gate insulating film that electrically insulates a gate electrode from a silicon substrate, wherein a base layer containing silicon is formed on the silicon substrate, A metal compound as a metal diffusion source is deposited on the formed underlayer and heat treated to diffuse the metal element of the metal compound into the underlayer and form a high dielectric constant gate insulating film on the silicon substrate.
  • the metal atomic weight in the metal compound is in the range of 1.5E + 15 cm- 2 force and 2.6E + 15 cm- 2 .
  • the semiconductor device according to the present invention has a thickness (nm) of a metal compound as a metal diffusion source.
  • the amount of metal in the metal compound is 0.6 or more and 0.9 or less. To do.
  • the underlayer also has a silicon oxide or silicon oxynitride force.
  • the heat treatment is performed in an atmosphere containing at least ammonia or oxygen, whereby a metal diffusion film in which the metal element of the metal compound is diffused into the underlayer is formed. It is a feature.
  • the heat treatment is performed in an inert gas, and then the heat treatment is performed in an atmosphere containing at least ammonia or oxygen, whereby the metal element of the metal compound is applied to the underlayer.
  • a diffused metal diffusion film is formed.
  • the semiconductor device according to the present invention performs the heat treatment performed in an atmosphere containing at least ammonia or oxygen at 700 ° C. or higher and 950 ° C. or lower, so that the metal element of the metal compound is A metal diffusion film diffused in the underlayer is formed.
  • the heat treatment is performed at 750 ° C. or more and 900 ° C. or less in an atmosphere containing at least ammonia, and the amount of metal atoms in the metal compound is 1S 2.3E + 15 cm- 2 force or the like. 2. It is characterized by being in the range of 6E + 15cm- 2 .
  • the heat treatment is performed at 700 ° C. or more and less than 750 ° C. in an atmosphere containing at least ammonia, and the amount of metal atoms in the metal compound is 1S 1.5E + 15 cm- 2 force or the like. 1. 7E + 15cm- 2 range.
  • the heat treatment is performed in an inert gas, and thereafter, the metal element of the metal compound is diffused into the underlying layer by exposure to an atmosphere containing nitrogen radicals. A diffusion film is formed.
  • the heat treatment is performed in an atmosphere containing at least oxygen, and then exposed to an atmosphere containing nitrogen radicals, whereby the metal element of the metal compound diffuses into the underlayer.
  • a metal diffusion film is formed.
  • the semiconductor device according to the present invention is characterized in that the lower part of the underlayer is oxidized during the heat treatment in an atmosphere containing at least oxygen.
  • the semiconductor device according to the present invention is characterized in that the metal concentration of the metal compound (number of metal atoms Z (number of silicon atoms + number of metal atoms)) is 0.3 or more.
  • the semiconductor device according to the present invention has an oxide layer equivalent film thickness of the high dielectric constant gate oxide film after the heat treatment, the underlying layer used when forming the high dielectric constant gate oxide film. It is characterized by becoming thinner.
  • the metal compound includes Zr, Hf, Ta, Al, Ti, Nb, Sc, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, It is characterized by containing at least one metal element of Dy, Ho, Er, Tm, Yb, and Lu.
  • a method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device having a gate insulating film for electrically insulating a gate electrode from a silicon substrate, and includes silicon on the silicon substrate.
  • a step of forming an underlayer to be deposited, a step of depositing a metal compound as a metal diffusion source on the underlayer, a heat treatment to the underlayer and the metal compound, and diffusing the metal element of the metal compound into the underlayer A high dielectric constant gate insulating film on the silicon substrate.
  • the amount of metal atoms in the metal compound is from 1.5E + 15cm to 2.6
  • the amount of the metal in the metal compound determined by the product of is in the range of 0.6 or more and 0.9 or less.
  • the underlayer is made of silicon oxide.
  • the silicon oxynitride force is also obtained.
  • the heat treatment is performed in an atmosphere containing at least ammonia or oxygen so that the metal element of the metal compound diffuses into the underlayer. A film is formed.
  • the heat treatment is performed in an inert gas, and then performed in an atmosphere containing at least ammonia or oxygen, so that the metal element of the metal compound is applied to the underlayer. It is characterized by forming a diffused metal diffusion film.
  • the heat treatment performed in an atmosphere containing at least ammonia or oxygen is performed at 700 ° C or higher and 950 ° C or lower. is there.
  • the heat treatment is performed at 750 ° C or more and 900 ° C or less in an atmosphere containing at least ammonia, and the amount of metal atoms in the metal compound is 2. is characterized in that in the range of from 3E + 15cm- 2 of 2. 6E + 15cm- 2.
  • the heat treatment is performed at 700 ° C or more and less than 750 ° C in an atmosphere containing at least ammonia, and the amount of metal atoms in the metal compound is 1. is characterized in that in the range of 1. 7E + 15cm- 2 from 5E + 15cm- 2.
  • the heat treatment is performed in an inert gas, and then exposed to an atmosphere containing nitrogen radicals, so that the metal compound gold is exposed.
  • a metal diffusion film in which a metal element is diffused in an underlayer is formed.
  • the heat treatment is performed in an atmosphere containing at least oxygen, and then the metal element of the metal compound is exposed to an atmosphere containing nitrogen radicals. It is characterized by forming a diffused metal film in the underlayer.
  • the lower portion of the underlayer is oxidized during the heat treatment in an atmosphere containing at least oxygen.
  • the metal concentration of the metal compound (number of metal atoms Z (number of silicon atoms + number of metal atoms)) is 0.3 or more. It is.
  • a gate oxide film having a high dielectric constant in terms of an oxide film equivalent film thickness of the high dielectric constant gate oxide film after the heat treatment is obtained. It is characterized by being thinner than the underlying layer used for forming.
  • the metal compound includes Zr, Hf, Ta, Al, Ti, Nb, Sc, Y, La, Ce, Pr, Nd, Sm, It contains at least one metal element of Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu.
  • a base silicon oxide film is formed on the silicon substrate, and the formed base silicon oxide
  • a metal oxide, metal silicon oxynitride, or nitride containing at least one metal element of Lu is deposited, and heat treatment is performed to promote the interfacial silicate reaction.
  • the metal atomic weight in the metal oxide film (nitride film) is 1.5E + 15cm— is characterized in that it is 2 ⁇ 2. 6E + 15cm- 2 range.
  • the deposition method of the metal silicon oxide film or the metal nitride film used as the metal diffusion source can be any metal deposition method including any metal deposition method. In order to form a solid phase reaction film, it is essential to set the amount of metal contained in the oxide or metal nitride to an appropriate value. The same applies when a silicon oxynitride film is used as the base layer instead of the base silicon oxide film.
  • the present invention may employ a low-cost and excellent reproducibility method of forming a metal silicon oxynitride after metal diffusion or during metal diffusion. By nitriding the metal oxide, the dielectric constant is greatly increased.
  • the relationship between the Hf concentration, the film thickness, and the Hf amount in the present invention is not just a design matter. For example, even if a film is formed with a film thickness or Si concentration, a solid-phase reaction must be performed. Therefore, it will not be possible to reduce electronic traps.
  • a semiconductor device and a method for manufacturing a semiconductor device according to the present invention include forming a base layer containing silicon on a silicon substrate in a semiconductor device having a gate insulating film that electrically insulates the gate electrode of the gate electrode. Then, a metal compound is deposited as a metal diffusion source on the formed underlayer, heat treatment is performed on the underlayer and the metal compound, the metal element of the metal compound is diffused into the underlayer, and a high concentration is formed on the silicon substrate.
  • forming a gate insulating film of a dielectric constant a metal atom content in the metal compound is characterized in range der Rukoto of 1. 5E + 15cm 2 power et al 2. 6E + 15cm- 2. In this way, by optimizing the film formation conditions, it is possible to form a high-quality gate insulating film on the interface of the silicon substrate, and to improve the interface electrical characteristics.
  • the semiconductor device in this embodiment includes a step (FIG. 1 (a)) of forming a base layer (oxide film or oxynitride film) (102) containing silicon on the surface of a silicon substrate (101), and a base layer (102 )
  • the process (Fig. 1 (a) of forming a base layer (oxide film or oxynitride film) (102) containing silicon on the surface of a silicon substrate (101), and a base layer (102 )
  • a high-quality gate insulating film (106) can be formed on the interface of the silicon substrate (101), and the electrical interface characteristics can be improved (FIG. L (d)).
  • the gate insulating film (106) is composed of an Hf rich region (104) and an Si rich region (105).
  • the semiconductor device according to the present embodiment is not directly deposited on a silicon substrate (101) with a high dielectric constant gate insulating film made of silicate, as shown in FIG. 1 (c).
  • a high-quality silicate film formed by the interfacial reaction between the base layer (102) and the metal compound layer (103) is used as the gate insulating film (106).
  • This gate insulating film (106) has a high dielectric constant, and can be an extremely thin insulating film.
  • the metal compound in the metal compound layer (103) has a metal atom amount in the range of 1.5E + 15 cm— 2 forces and 2.6E + 15 cm— 2 as a metal diffusion source.
  • the amount of metal in the metal compound determined by the product of the film thickness (nm) of the metal compound and the metal concentration (number of metal atoms Z (number of silicon atoms + number of metal atoms)) is not less than 0.6. It is characterized by a range of 9 or less.
  • metal compounds with different film thicknesses (nm) and concentrations can be used as metal diffusion sources to maximize electron trap reduction and leakage current reduction. A method for forming a solid phase reaction film will be described.
  • FIG. 1 suggests a manufacturing process of a high-quality HfSiO gate insulating film in the present embodiment.
  • the silicon substrate (101) is washed with sulfuric acid-hydrogen peroxide and ammonia-hydrogen peroxide, and then subjected to thermal oxidation to form silicon oxide that becomes the base oxide film layer (102).
  • the film thickness is 1.8 nm (Fig. L (a)).
  • hafnium silicate (103) HfSiO film or HfO film with different Hf concentration is applied to the surface of the base oxide film layer (102).
  • MOCVD Metal Organic Chemical Vapor Deposition
  • ALCVD Atomic Layer Chemical Vapor Deposition
  • PVD Physical Vapor Deposition
  • HTB tertiary butoxy hafnium
  • Si source silane or disilane
  • Hf SiO layer (103) is formed. accumulate. Then, annealing is performed in an oxygen or ozone atmosphere.
  • TDEAH is used as the Hf source gas.
  • the HfSiO film (103) is deposited using TDMAS as the Si raw material.
  • the deposition method using the ALCVD method includes a step of oxidizing the HF source material and the Si source material after depositing the Hf source material and the Si source material using TEMAH as the Hf source gas. By repeating, the HfSiO film (103) is formed.
  • sputtering is performed by sputtering Hf atoms.
  • the Hf layer is oxidized to form the HfO film (103).
  • the heat treatment for the metal diffusion reaction in the present embodiment was performed under conditions of 800 ° C and 10 minutes in an ammonia atmosphere so that the metal element in the metal diffusion source could be sufficiently diffused.
  • FIGS. 2 to 4 were prepared by fixing the thickness of the HfSiO film (103) deposited on the base oxide film layer (102) to 1.5 nm and changing the amount of supplied Hf. This suggests the results of MISFET characterization of solid phase reaction HfSiON film (103).
  • FIG. 2 suggests the dependence of the gate-side insulating film (106) on the reverse leakage current reduction effect on the amount of Hf with respect to a SiON film having an equivalent electrical oxide film equivalent film thickness.
  • FIG. 3 suggests hysteresis measurement results at various Hf amounts.
  • Hysteresis corresponds to the phenomenon that charges are trapped in the electron traps in the gate insulating film (106) when a voltage is applied.
  • Figure 3 suggests the measurement results when the voltage sweep width is changed to 1.8V.
  • Fig. 3 shows that the hysteresis decreases as the Hf amount decreases. This is because the unreacted surplus Hf atoms left in the HfSiO film (103) serving as the metal diffusion source are reduced.
  • Hf amount 2.
  • Hf amount for 6E + 15cm 2 hysteresis is several mV or less in the following and a very Teigu hysteresis suppressed 2.
  • 6E + 15cm - it can be seen that it is necessary to 2 or less.
  • FIG. 4 shows the comparison of the on-current (Ion) of the transistor with the characteristics of the transistor having the reference SiON gate insulating film, normalized by the inversion capacitance. It can be seen that the Hf amount has a peak of on-current at 2.3E + 15cm " 2 to 2.6E + 15cm- 2, and that the on-state current deteriorates abruptly at Hf amounts greater than 2.6E + 15cm- 2 . [0069] In other words, it is completely consistent with the hysteresis tendency suggested in Fig. 3, and it can be seen that the mobility is improved by reducing the excess Hf atoms in the metal diffusion source and reducing the number of electron traps. .
  • the amount of metal that can be supplied is reduced by lowering the heat treatment temperature because the amount of Hf that can be subjected to solid-phase reaction is reduced, resulting in an increase in electron traps due to excess Hf. This is because the lowering of the crystallization temperature cannot be suppressed by lowering. Below 700 ° C, no solid phase reaction of Hf occurred, and there was no improvement in property deterioration.
  • the metal atom of the metal compound is in the range of 1. 5E + 15cm- 2 ⁇ 2. 6E + 15cm 2, and the thickness of the metal compound as a metal diffusion source (nm), If the amount of metal in the metal compound determined by the product of the metal concentration (number of metal atoms Z (number of silicon atoms + number of metal atoms)) is in the range of 0.6 or more and 0.9 or less, it is different. It can be seen that no matter how the Hf SiO film with the film thickness and composition is deposited, the film quality is the same after solid phase diffusion.
  • the heat treatment for the solid phase reaction of the metal diffusion source is performed in an atmosphere containing ammonia, but the diffusion reaction is performed in an inert gas such as nitrogen, Ar, or He instead of ammonia. And then heat treatment in an atmosphere containing at least ammonia. Similar results can be obtained by introducing nitrogen by exposure to nitrogen radicals. In other words, the electron traps are reduced by the solid phase reaction by the first heat treatment, and the heat resistance is improved by introducing nitrogen into the film in the next nitriding treatment. In particular, the final nitrogen concentration profile in the film when nitrogen radicals are used decreases as the substrate interface increases on the surface.
  • the nitrogen concentration at the substrate interface can be reduced, the BT reliability of the PMOS (VT shift amount after 10 years under the conditions of operating temperature 85 ° C and operating voltage 1. IV) is treated with ammonia. Compared to the case, it can be improved by 5mV or more.
  • a silicon oxide film is used for the base layer (102).
  • a silicon oxynitride film is used for the base layer (102)
  • the same electron trap reduction effect can be obtained.
  • the layer (102) has a high dielectric constant due to nitriding, it can be made thinner.
  • Hf nitride (HfN) or Hf silicon nitride (HfSiN) is used as the metal diffusion source.
  • thermal oxidation was performed to form a silicon oxide film of 1.8 nm, which becomes the base oxide film layer (102) (FIG. 1 (a)).
  • Any apparatus may be used to form the base oxide film layer (102).
  • a single-wafer type lamp aligner apparatus is used, and 50% nitrogen-diluted oxygen is used.
  • a base oxide film layer (102) is formed by heat treatment at 900 ° C. in an atmosphere.
  • an HfN layer (103) or an HfSiN layer (103) is deposited in a thickness of 0.5 nm to 2. Onm on the surface of the base oxide film layer (102) (FIG. 1 (b)).
  • the HfN layer (103) is formed using a metal Hf target and a mixed gas of argon and nitrogen as a sputtering gas (reactive gas).
  • the HfSiN layer (103) is formed by alternately using a metal Hf target and a Si target and using a mixed gas of argon and nitrogen as a reaction gas.
  • TEMAH is used as the Hf source gas, and after depositing the Hf source and the Si source, the process of nitriding in an ammonia atmosphere is repeated to form the HfSiN film layer (103) Then, the HfN film layer (103) is formed by eliminating the Si raw material deposition step.
  • the PVD method is mainly used.
  • the method of dividing the metal atom diffusing step and the nitriding step realizes the heat treatment conditions, the desired nitrogen concentration, and the nitrogen profile for sufficiently diffusing the metal atoms. Therefore, there is an advantage that the nitriding conditions can be controlled independently.
  • FIGS. 7 to 9 show the effects of reducing the gate leakage current when the amount of Hf in the 1.5 nm Hf nitride and Hf silicon nitride used as a metal diffusion source is changed (FIG. 7). ), Hysteresis (Fig. 8), and transistor on-current (Fig. 9) were evaluated.
  • FIG. 7 suggests the dependence of the gate insulating film on the inversion side leakage current with respect to the Hf amount dependence on the SiON film having the equivalent electrical oxide film equivalent film thickness.
  • the Hf content of the deposited HfSiO film must be at least 2.3E + 15cm.
  • Fig. 8 suggests hysteresis measurement results at various Hf amounts.
  • Hysteresis corresponds to the phenomenon that charges are trapped in electron traps in the gate insulating film when a voltage is applied.
  • Figure 8 suggests the measurement results when the voltage sweep width is changed to 1.8V.
  • Hf amount: 2. 3E + 15cm 2 indicates that it is necessary to set the amount of Hf of metal diffusion source 2. 3E + 15cm- 2 or less for very small sag hysteresis suppression and hysteresis of several mV or less in the following ing.
  • FIG. 9 is a graph in which the on-current (Ion) of the transistor is normalized by the inversion capacitance and compared with the characteristics of the transistor having the reference SiO N gate insulating film. So the suggested in Figure 9, there is a peak of Hf weight 2. 3E + 15cm- 2 ⁇ 2. 6E + 15cm- 2 near the on-current, 2. 6 E + 15cm- 2 or more on-current abruptly in the amount of Hf It turns out that it deteriorates. In other words, it is completely consistent with the hysteresis trend suggested in Fig. 8, and it can be seen that the mobility is improved by reducing the excess Hf atoms in the metal diffusion source and reducing the number of electron traps. In addition, as suggested in Fig. 9, when the Hf content is in the range of 2.3E + 15cm- 2 to 2.6E + 15cm- 2 , it is possible to achieve characteristics of about 90% of SiON.
  • the deterioration of TZDB decreases the strength of nitriding, This is because the decrease in the conversion temperature cannot be suppressed.
  • the hysteresis and defect density in the low-temperature solid-phase diffusion is possible to improve by reducing the amount of Hf, 5 mv or less hysteresis by the amount of Hf to 1. 5E + 15cm 2 ⁇ 1. 7E + 15cm- 2 It is possible to improve the defect density to 1 / cm 2 .
  • the processing temperature for the solid phase reaction is 700 ° C or more and less than 750 ° C
  • the optimum amount of Hf for Hf diffusion reaction is lower than that of 750 ° C or more 1.5E + 15cm— 2 to 1.7E + 15 cm— 2 .
  • solid phase diffusion did not occur.
  • the silicon oxide film is used as the underlayer.
  • the same electron trap reduction effect can be obtained by using a silicon oxynitride film instead of the silicon oxide film. Become. In this case, since the underlayer has a high dielectric constant due to nitriding, it becomes thinner.
  • metal is diffused from the metal diffusion layer (203) to the underlayer (202) by solid phase diffusion.
  • heat treatment is performed in an atmosphere containing at least oxygen.
  • Figure 10 shows a high-quality HfSiO gate insulating film when a solid phase diffusion of metal from the metal diffusion layer (203) to the underlayer (202) is performed in an atmosphere containing at least oxygen ( 206) is shown.
  • a silicon oxide film to be the underlayer (202) is formed to 1.5 nm (FIG. 10 (a)). Then, the metal diffusion of HfSiO film, HfO film, HfN film, or HfSiN film, which becomes a metal diffusion source, is formed on the surface of the underlying silicon oxide film (202).
  • a scattering layer (203) is deposited (Fig. 10 (b)).
  • the Hf content in the film is 2.5E + 15 cm 2 HfSiO film or HfSiN film 1.5 Deposit nm.
  • the decrease in inversion layer capacitance due to an oxide film increase of 1 angstrom or more offsets the increase in mobility, and the transistor on-current improvement was about 4%. Therefore, it is necessary to make the underlying silicon oxide film (202) thin for at least 1 angstrom or more and adjust the final oxide film equivalent film thickness to a desired film thickness.
  • the interface silicate reaction proceeds to the silicate region at the interface between the base layer (202) for forming the gate insulating film (206) and the metal compound layer (203), and the Hf-rich region. (204) and Si-rich region (205).
  • HfSiN Metal diffusion sources are Zr, Hf, Ta, Al, Ti, Nb, Sc, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm Similar results are obtained when using metal oxides, metal nitrides, or silicate materials characterized by containing at least one element of Yb, Lu.
  • the gate electrode is electrically connected from the silicon substrate.
  • a base silicon oxide film is formed on a silicon substrate, and a metal oxide, metal nitride or a silicate thereof is used as a metal diffusion source on the formed base silicon oxide film.
  • the interfacial silicate reaction is promoted, and the metal element is diffused into the underlying silicon oxide film to form a high dielectric constant gate insulating film on the silicon substrate.
  • the metal diffusion source having the film thickness containing Hf and the composition ratio shown in this embodiment the maximum gate leakage reduction is possible regardless of the method of forming the metal diffusion source.
  • the effect and transistor on-current can be realized.
  • the base oxide film thickness can be set larger than the equivalent oxide film thickness of the gate dielectric film having a high dielectric constant, it is possible to have a thin film characteristic.
  • the semiconductor device and the method for manufacturing the semiconductor device according to the present invention can be applied to a semiconductor device having a high dielectric constant thin film and a method for manufacturing the semiconductor device.
  • FIG. 1 A diagram suggesting a manufacturing process of a Hf silicate high dielectric constant film in the present embodiment.
  • FIG. 2 This figure suggests the dependence of the gate leakage reduction effect on the amount of Hf compared to the SiON film when the film thickness of the metal diffusion source (HfSiO) is 1.5 nm.
  • FIG. 3 This figure suggests the dependence of hysteresis on the amount of Hf when the thickness of the metal diffusion source (HfSiO) is 1.5 nm.
  • FIG. 4 A graph showing the dependence of the transistor on-current on the Hf content compared to the SiON film, normalized by the inversion capacitance, when the film thickness of the metal diffusion source (HfSiO) is 1.5 nm.
  • FIG. 5 is a diagram suggesting the processing temperature dependence of hysteresis.
  • FIG. 6 This figure suggests the optimum film thickness and composition ratio of the HfSiO film when used as a metal diffusion source.
  • FIG. 8 This figure suggests the dependence of hysteresis on the amount of Hf when the thickness of the metal diffusion source (HfSiN) is 1.5 nm.
  • FIG. 9 This figure is normalized by the inversion capacitance when the film thickness of the metal diffusion source (HfSiN) is 1.5 nm, and suggests the dependence of the transistor on-current on the Hf amount compared to the SiON film.
  • FIG. 10 is a diagram suggesting a manufacturing process of the Hf silicate high dielectric constant film in the third embodiment.

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Abstract

Cette invention a pour objet un dispositif semi-conducteur comprenant en outre une pellicule isolante à gâchette de haute qualité, formée sur l’interface d’un substrat de silicium, et dont les caractéristiques électriques sont développées. Sur la surface du substrat de silicium (101), se forme une couche de base (pellicule d’oxyde ou pellicule d’oxynitrure) (102), incluant du silicium. Sur la surface de cette couche de base formée (102), une couche de composé métallique (103) est déposée et sert de source fournisseuse de métal ou de source diffuseuse de métal. La couche de base (102) et la couche de composé métallique (103) sont traitées thermiquement afin de diffuser, dans cette couche de base (102), un élément métallique extrait du composé métallique compris dans la couche de composé métallique (103). Puis, sur le substrat de silicium (101), se forme une pellicule isolant la gâchette (106) dont la constante diélectrique est élevée, et se forme également un dispositif semi-conducteur dont la quantité d’atomes métalliques, dans le composé métallique de la couche de composé métallique (103), est comprise entre 1,5E+15cm-2 et 2,6E+15cm-2.
PCT/JP2005/012890 2004-07-20 2005-07-13 Dispositif semiconducteur et procédé de fabrication de ce dispositif semiconducteur WO2006009025A1 (fr)

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JP2006319091A (ja) * 2005-05-12 2006-11-24 Renesas Technology Corp 半導体装置の製造方法
JP2009021560A (ja) * 2007-06-15 2009-01-29 Hitachi Kokusai Electric Inc 半導体装置の製造方法および基板処理装置
KR101451103B1 (ko) * 2007-01-31 2014-10-15 재팬 디스프레이 웨스트 인코포레이트 박막 반도체장치의 제조방법
WO2016159355A1 (fr) * 2015-04-01 2016-10-06 株式会社ワコム研究所 Procédé de formation de film et appareil de formation de film pour la formation d'un film de nitrure à l'aide d'un appareil mocvd, et douchette

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006319091A (ja) * 2005-05-12 2006-11-24 Renesas Technology Corp 半導体装置の製造方法
KR101451103B1 (ko) * 2007-01-31 2014-10-15 재팬 디스프레이 웨스트 인코포레이트 박막 반도체장치의 제조방법
JP2009021560A (ja) * 2007-06-15 2009-01-29 Hitachi Kokusai Electric Inc 半導体装置の製造方法および基板処理装置
WO2016159355A1 (fr) * 2015-04-01 2016-10-06 株式会社ワコム研究所 Procédé de formation de film et appareil de formation de film pour la formation d'un film de nitrure à l'aide d'un appareil mocvd, et douchette
JP2016195214A (ja) * 2015-04-01 2016-11-17 株式会社 ワコム研究所 Ｍｏｃｖｄ装置による窒化膜を成膜する成膜方法及び成膜装置、並びにシャワーヘッド

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