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WO2006007757A1 - Transistor a film en couches minces en polysilicium a faible temperature - Google Patents

Transistor a film en couches minces en polysilicium a faible temperature Download PDF

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Publication number
WO2006007757A1
WO2006007757A1 PCT/CN2004/000822 CN2004000822W WO2006007757A1 WO 2006007757 A1 WO2006007757 A1 WO 2006007757A1 CN 2004000822 W CN2004000822 W CN 2004000822W WO 2006007757 A1 WO2006007757 A1 WO 2006007757A1
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WO
WIPO (PCT)
Prior art keywords
thin film
layer
film transistor
low temperature
region
Prior art date
Application number
PCT/CN2004/000822
Other languages
English (en)
Chinese (zh)
Inventor
Zhengzhang Guo
Original Assignee
Quanta Display Inc.
Quanta Display Japan Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Quanta Display Inc., Quanta Display Japan Inc. filed Critical Quanta Display Inc.
Priority to PCT/CN2004/000822 priority Critical patent/WO2006007757A1/fr
Publication of WO2006007757A1 publication Critical patent/WO2006007757A1/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H10D86/0227—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials using structural arrangements to control crystal growth, e.g. placement of grain filters

Definitions

  • the invention relates to a method for manufacturing a thin film transistor and a channel layer thereof, and particularly to a method for manufacturing a low temperature poly-silicon (LTPS) transistor and a channel layer thereof.
  • LTPS low temperature poly-silicon
  • switches are required to drive the operation of the components.
  • an actively driven display element it is usually a Thin Film Transistor (TFT) as a driving switch.
  • TFT Thin Film Transistor
  • the thin film transistor can be divided into amorphous silicon (abbreviated as a-Si) thin film transistor and polycrystalline silicon (poly-silicon) thin film transistor according to the material of the channel region, because the polycrystalline silicon thin film transistor consumes compared with the amorphous silicon thin film transistor.
  • the power is small and the electron mobility is large, so it is gradually receiving attention from the market.
  • the polycrystalline silicon thin film is formed by first forming an amorphous silicon thin film on the substrate, and then melting (melting) the amorphous silicon thin film to become a polycrystalline silicon thin film.
  • 1A and 1B are schematic cross-sectional views showing a manufacturing process of a conventional low-temperature polysilicon film.
  • a commonly used laser annealing process is an Excimer Laser Annealing (ELA) process.
  • ELA Excimer Laser Annealing
  • FIG. 1A after the amorphous silicon film 102 is formed on the substrate 100, the excimer laser beam 106 is used.
  • a laser annealing process is performed to melt the amorphous silicon film 102 to recrystallize the silicon molecules into the polysilicon film 102a, as shown in FIG.
  • the grain size of the polysilicon film 102a formed by the ELA process is too small and the uniformity of the uniformity is poor, there are many grain boundaries in the polysilicon film 102a, so that the electrons are in the polysilicon film.
  • the mobility in the channel region of 102a is only about 100 to 200 cm-sec, which has a considerable influence on the performance of the thin film transistor.
  • SLS Sequential Lateral Solidification
  • the SLS process utilizes a mask 104 to define a range in which the amorphous silicon film 102 is irradiated by the laser beam 106 to melt the amorphous silicon film 102 in the partial region, that is, the amorphous silicon film 102 in the region 110.
  • the reticle 104 is controlled by the machine to translate so that the laser beam passes through the holes 108 in the reticle 104 to illuminate all of the amorphous silicon film 102 in the region 110.
  • the molten amorphous silicon film 102 (that is, the amorphous silicon film 102 in the region 110) will grow laterally with the unmelted amorphous silicon film 102 as a crystal nucleus. Further, a polysilicon film 202a is formed in the region 110.
  • the SLS process can form a polysilicon film 202a having a large grain size.
  • the grain boundary in the polysilicon film 202a formed by the SLS process is small, so the SLS process can improve the mobility of electrons in the polysilicon film and improve the efficiency of the thin film transistor compared with the conventional ELA process.
  • the grain orientation of the polysilicon film is more uniform.
  • Another object of the present invention is to provide a method for fabricating a channel layer of a low temperature polysilicon thin film transistor which can control the grain size and crystal orientation in the channel region of the transistor, thereby increasing the mobility of electrons therein.
  • the manufacturing equipment used in this manufacturing method can be compatible with existing manufacturing equipment, thereby saving manufacturing costs.
  • the present invention provides a low temperature polysilicon thin film transistor suitable for being disposed on a substrate.
  • the low temperature polysilicon thin film transistor is mainly composed of a cap layer, a polysilicon film, and a gate.
  • the top cover layer is disposed above the substrate and has a gap region between the substrate and the substrate.
  • the polysilicon film is disposed on the cap layer and can be divided into a channel region and source/drain regions on both sides of the channel region.
  • the channel region is located above the gap region, and the polysilicon film in the channel region is the channel layer of the transistor.
  • the gate is placed above the channel area.
  • the CMOS transistor further includes a buffer layer disposed on the substrate between the cap layer and the substrate to block undesired diffusion of impurities in the substrate during the process. This in turn affects the performance of the component.
  • the gap region is located, for example, between the cap layer and the buffer layer, and the gap region has a thermal conductivity lower than that of the buffer layer and the substrate.
  • the OLED film is further provided with a gate dielectric layer disposed on the polysilicon film.
  • the grains of the polysilicon film in the channel region are, for example, larger than the grains of the polysilicon film in the source/drain regions, thereby causing the transistor to have a higher driving current. And lower leakage current.
  • the grain size in the channel region is large, the number of grain interfaces therein is less than the number of grain interfaces in the source/drain regions, so electrons can be moved by the electric field in the channel region but are not easy. It is scattered by the grain interface, so it has better electron mobility.
  • the width of the gate is preferably smaller than the size of the grains in the channel region.
  • the gate is, for example, a double-noisy structure, which further reduces the influence of electrons directly on the unique grain interface in the center of the channel, thereby significantly improving the performance of the transistor.
  • the CMOS transistor further includes a dielectric layer, a source/drain contact hole, and a source/drain conductor layer.
  • the dielectric layer is disposed on the polysilicon film and covers the gate.
  • the source/drain contact holes are disposed in the dielectric layer and the gate dielectric layer and are in electrical contact with the source/drain regions.
  • the source/drain conductor layer is disposed on the dielectric layer and filled in the source/drain contact holes to be electrically connected to the source/drain regions.
  • the present invention also provides a method for fabricating a channel layer of a low temperature polysilicon thin film transistor.
  • the method first forms a sacrificial layer over the substrate, and sequentially forms a cap layer and an amorphous silicon film on the sacrificial layer.
  • the sacrificial layer is then removed to form a gap region between the substrate and the cap layer.
  • the amorphous silicon film is melted and then recrystallized to form a polysilicon channel layer on the cap layer above the gap region.
  • the method further includes forming a buffer layer on the substrate to prevent unintended diffusion of impurities in the substrate during the process before forming the sacrificial layer.
  • the sacrificial layer is then formed on the buffer layer.
  • the method of removing the sacrificial layer is, for example, a wet etching process which immerses the formed structure in an etchant, for example.
  • the etch rate of the sacrificial layer is greater than the etch rate of the other layers.
  • the step of melting the amorphous silicon film and recrystallizing to form the polysilicon channel layer comprises first irradiating the amorphous silicon film with an excimer laser to melt the amorphous silicon film into a liquid silicon material. An annealing process is then performed to rearrange the grains in the silicon material A polysilicon film is formed.
  • the polysilicon film located above the gap region is a polysilicon channel layer, and the silicon grains in the polysilicon channel layer are larger than the silicon grains in the polysilicon film in other regions.
  • the crystal orientation of the crystal grains in the polycrystalline silicon film formed by the present invention is parallel to the direction of electron transport of the subsequent transistor in the operating state, thereby improving the mobility of electrons in the channel region, thereby improving the operational efficiency of the transistor.
  • 1A and 1B are schematic cross-sectional views showing a manufacturing process of a conventional low-temperature polysilicon film.
  • 2A to 2B are schematic cross-sectional views showing a manufacturing process of another conventional low-temperature polysilicon film.
  • FIG 3 is a cross-sectional view showing a low temperature polysilicon thin film transistor in accordance with a preferred embodiment of the present invention.
  • Fig. 4A is a top plan view showing a low temperature polysilicon thin film transistor in an embodiment of the present invention.
  • Fig. 4B is a top view of a low temperature polysilicon thin film transistor in another embodiment of the present invention.
  • 5A to 5E are cross-sectional views showing the manufacturing process of a channel layer of a low-temperature polysilicon thin film transistor according to a preferred embodiment of the present invention.
  • FIGS. 6A to 6D show upper views thereof corresponding to Figs. 5A to 5E, respectively. detailed description
  • the invention removes amorphous silicon before converting the amorphous silicon film into a polycrystalline silicon film.
  • the thin film is formed as a sacrificial layer under the region of the polysilicon channel to form a gap region with low thermal conductivity on both sides, so that the crystallization rate of the silicon crystal grains above is higher than that of the silicon crystal grains in the two regions.
  • the rate is slow, which in turn causes the grains to grow laterally from both sides toward the center and grow into larger sized grains in the channel region.
  • the low temperature polysilicon thin film transistor 330 of the present invention is mainly composed of a substrate 300, a cap layer 306, a polysilicon film 308a, a gate 316, and a source/drain conductor layer 336.
  • the top cover layer 306 is disposed above the substrate 300, and in the embodiment, a buffer layer 302 between the top cover layer 306 and the substrate 300 is disposed on the substrate 300 to block impurities in the substrate. Unexpected diffusion occurs, which in turn affects the performance of the component.
  • the gap region 310 there is a gap region 310 between the top cover layer 306 and the buffer layer 302.
  • the gap region 310 has, for example, air or other gas having a low heat transfer coefficient.
  • the polysilicon film 308a is disposed on the cap layer 306, and can be divided into a channel region 322 and a source/drain region 318 doped with a dopant.
  • the channel region 322 is located above the gap region 310, and the channel region
  • the polysilicon film 308a in 322 is the polysilicon channel layer of the low temperature polysilicon thin film transistor 330.
  • the gate 316 is disposed above the channel region 322 of the polysilicon film 308a, and the gate dielectric layer 314 is disposed, for example, on the polysilicon film 308a.
  • Dielectric layer 324 is disposed over gate dielectric layer 314 and covers gate 316.
  • the source/drain conductor layer 336 is disposed on the dielectric layer 324, and the source/drain conductor layer 336 is disposed through the source/drain contact holes 332 disposed in the dielectric layer 324 and the gate dielectric layer 314. Electrically coupled to source/drain regions 318.
  • the silicon grains 340 in the polysilicon film 308a in the channel region 322 are, for example, larger than the silicon grains 350 in the polysilicon film 308a in the source/drain regions 318, and
  • the preferred size is approximately half the length L of the channel region 322, so the temperature is much lower
  • the crystalline silicon thin film transistor 330 can have a higher driving current.
  • the number of die interfaces 360 within the channel region 322 may be less than the number of die interfaces 360 within the source/drain regions 318.
  • the crystal orientation of the crystal grains is parallel to the transmission direction of the electrons in the low temperature polysilicon thin film transistor 330, so when the low temperature polysilicon thin film transistor 330 is in operation, the electron carrier can easily pass through the channel region 322 without being affected by the channel region.
  • the grain boundary 360 in 322 is excessively scattered and scatters, resulting in a decrease in electron mobility.
  • the present invention can also reduce the width of the gate 316 of the low temperature polysilicon thin film transistor 330 to be smaller than the size of the die 340 (as shown in FIG. 4A), thereby avoiding the channel region of the thin film transistor crossing the grain interface.
  • the thin film transistor can have better performance.
  • grain size herein generally refers to the length of the grain parallel to the width of the gate.
  • the present invention can also configure a dual gate structure 416 on the low temperature polysilicon thin film transistor, as shown in FIG. 4B, which shows a low temperature polysilicon thin film transistor in another embodiment of the present invention.
  • FIG. 4B shows a low temperature polysilicon thin film transistor in another embodiment of the present invention.
  • This dual gate structure 416 also reduces electrons directly from the unique grain interface in the center of the channel, thereby significantly improving transistor efficiency.
  • the present invention accomplishes a low temperature polycrystalline silicon thin film transistor having better characteristics in the above-described channel region by a special process, and a method of manufacturing the channel layer of the above low temperature polysilicon thin film transistor will be described below by way of an embodiment.
  • 5A to 5E are cross-sectional views showing the manufacturing process of a channel layer of a low-temperature polysilicon thin film transistor according to a preferred embodiment of the present invention.
  • 6A to 6D show their upper views corresponding to Figs. 5A to 5E, respectively.
  • a buffer layer 302 and a sacrificial layer 304 are formed on the substrate 300 in sequence, for example, by chemical vapor deposition (deposition) or sputtering (sputtering).
  • the material of the layer 304 is, for example, metal. Material.
  • the buffer layer 302 is an optional component, and its function is as described in the foregoing embodiment, and details are not described herein again. Those skilled in the art can determine the presence or absence of the buffer layer 302 according to the actual process requirements, which is not limited by the present invention.
  • the sacrificial layer 304 is, for example, a rectangular patterned film layer disposed on the buffer layer 302, as shown in FIG. 6A.
  • a cap layer 306 and an amorphous silicon film 308 are sequentially formed on the buffer layer 302, and the sacrificial layer 304 is covered.
  • a channel layer of a low temperature polysilicon thin film transistor is formed in a region 312 above the sacrificial layer 304, and source/drain regions are formed in both sides of the region 312. Therefore, the width of the sacrificial layer 304 determines the length of the channel layer of the low temperature polysilicon thin film transistor. In other words, the length of the channel region in the low temperature polysilicon thin film transistor can be effectively controlled by controlling the width of the sacrificial layer 304.
  • the sacrificial layer 304 is then removed to form a gap region 310 between the cap layer 306 and the buffer layer 302, and the gap region 310 has, for example, air.
  • This step is performed, for example, by removing the sacrificial layer 304 by wet etching, that is, immersing the structure illustrated in FIG. 5B in an etchant (not shown), and the etch rate of the etchant to the sacrificial layer 304 is large.
  • the etch rate of the other layers is so that this step can remove the sacrificial layer 304 while the other layers remain intact.
  • a laser annealing process is performed to melt the amorphous silicon film 308 and then recrystallize to form a polysilicon film 308a on the cap layer 306 above the gap region 310.
  • a polysilicon channel layer 522 i.e., a polysilicon film 308a located within region 312 is formed.
  • the laser annealing process used in this embodiment is, for example, an excimer laser annealing process, as shown in FIG. 5D, which irradiates the amorphous silicon film 308 with an excimer laser beam 326 to melt it into liquid silicon (not shown). Out).
  • the liquid silicon slowly cools down and recrystallizes into a polysilicon film.
  • the region 312 since the region 312 is located above the gap region 310, and the gap region 310 has, for example, air, and the heat conductivity of the air is about 0.025 W/cm K:, much smaller than the heat conduction of the cap layer 306 and the buffer layer 302. Coefficient. Therefore, the liquid crystallization rate in the region 312 is slower than that of the liquid silicon on both sides.
  • the silicon atoms will grow from the sides to the center of the region 312 to form a polysilicon film 308a, and the polysilicon film 308a in the region 312 is the polysilicon channel layer 522 of the transistor, as shown in FIG. 5E and FIG. 6D. Show.
  • the grain size formed is larger than that formed in the both regions, that is, the crystal grains in the polysilicon channel layer 522 have a larger size.
  • the size for example, is slightly larger than half the length L of the polysilicon channel layer 322.
  • the number of grain boundaries in the polysilicon channel layer 322 is less than the number of grain interfaces in the side regions, electrons can have better mobility in the polysilicon channel layer 322, thereby improving the operational efficiency of the transistor.
  • the low temperature polysilicon thin film transistor of the present invention has the following advantages -
  • the transistor of the present invention Since the crystal grains in the channel region of the transistor have a large size and a preferable size uniformity, the transistor of the present invention has a high driving current and a high electron mobility.
  • the width and length of the channel region in this transistor depends on the width and length of the sacrificial layer. Therefore, the width-to-length ratio of the channel region can adjust the size of the sacrificial layer according to the actual process, and the process margin is large.
  • the manufacturing apparatus of the present invention is compatible with existing manufacturing equipment, for example, the apparatus of the existing excimer laser annealing process can be used to achieve the level of the Sequential Lateral Solidification (SLS) process, that is, the present
  • SLS Sequential Lateral Solidification
  • the invention can also save the cost of the process equipment while improving the quality of the product, so as to achieve the maximum production profit.

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  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un transistor en couches minces en polysilicium à faible température comprenant une couche supérieure, un film en couches minces en polysilicium, et une électrode de grille. La couche supérieure est disposée sur un substrat, et un espace creux les sépare. Le film en couches minces en polysilicium est disposé sur la couche supérieure, et divisé en une région de canaux et une région source/ drain sur les deux côtés de la région de canaux. La région de canaux est placée au-dessus de la partie supérieure. L'électrode de grille est placée sur la région de canaux. L'espace creux se trouve sur la région de canaux, lorsqu'un traitement de recuit au laser est effectué, la conductivité thermique de la région diminue, l'atome de silicium de la région présente un temps de recristallisation plus long, de sorte que les grains présentent une taille plus importante, et que la limite entre les grains dans la région de canaux est réduite. L'orientation des grains du film en polysilicium est parallèle au sens de transmission des électrons dans le transistor de film en couches minces en polysilicium, ceci améliorant le fonctionnement dudit transistor.
PCT/CN2004/000822 2004-07-16 2004-07-16 Transistor a film en couches minces en polysilicium a faible temperature WO2006007757A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2004/000822 WO2006007757A1 (fr) 2004-07-16 2004-07-16 Transistor a film en couches minces en polysilicium a faible temperature

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Application Number Priority Date Filing Date Title
PCT/CN2004/000822 WO2006007757A1 (fr) 2004-07-16 2004-07-16 Transistor a film en couches minces en polysilicium a faible temperature

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106783875A (zh) * 2016-12-07 2017-05-31 信利（惠州）智能显示有限公司 低温多晶硅膜制备方法、薄膜晶体管及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58212177A (ja) * 1982-06-02 1983-12-09 Matsushita Electric Ind Co Ltd 絶縁ゲ−ト型トランジスタおよびその製造方法
CN1153311A (zh) * 1995-04-21 1997-07-02 大宇电子株式会社 构成薄膜致动的反射镜阵列的方法
WO2002047144A2 (fr) * 2000-12-08 2002-06-13 Infineon Technologies Ag Isolant enterre modele
CN1497685A (zh) * 2002-10-21 2004-05-19 ����Sdi��ʽ���� 制造使用双重或多重栅极的薄膜晶体管的方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58212177A (ja) * 1982-06-02 1983-12-09 Matsushita Electric Ind Co Ltd 絶縁ゲ−ト型トランジスタおよびその製造方法
CN1153311A (zh) * 1995-04-21 1997-07-02 大宇电子株式会社 构成薄膜致动的反射镜阵列的方法
WO2002047144A2 (fr) * 2000-12-08 2002-06-13 Infineon Technologies Ag Isolant enterre modele
CN1497685A (zh) * 2002-10-21 2004-05-19 ����Sdi��ʽ���� 制造使用双重或多重栅极的薄膜晶体管的方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106783875A (zh) * 2016-12-07 2017-05-31 信利（惠州）智能显示有限公司 低温多晶硅膜制备方法、薄膜晶体管及其制备方法

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