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WO2006006842A2 - Processeur numerique et procede de traitement de donnees numeriques - Google Patents

Processeur numerique et procede de traitement de donnees numeriques Download PDF

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Publication number
WO2006006842A2
WO2006006842A2 PCT/NL2004/000505 NL2004000505W WO2006006842A2 WO 2006006842 A2 WO2006006842 A2 WO 2006006842A2 NL 2004000505 W NL2004000505 W NL 2004000505W WO 2006006842 A2 WO2006006842 A2 WO 2006006842A2
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WO
WIPO (PCT)
Prior art keywords
data word
bit data
dna
arithmetic
knowledge
Prior art date
Application number
PCT/NL2004/000505
Other languages
English (en)
Other versions
WO2006006842B1 (fr
WO2006006842A3 (fr
Inventor
Halil Kilic
Original Assignee
Halil Kilic
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Halil Kilic filed Critical Halil Kilic
Priority to EP04748730A priority Critical patent/EP1831782A2/fr
Priority to PCT/NL2004/000505 priority patent/WO2006006842A2/fr
Priority to CN2004800439691A priority patent/CN101091157B/zh
Publication of WO2006006842A2 publication Critical patent/WO2006006842A2/fr
Publication of WO2006006842A3 publication Critical patent/WO2006006842A3/fr
Publication of WO2006006842B1 publication Critical patent/WO2006006842B1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/4915—Multiplying; Dividing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
    • G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
    • G06F7/496—Multiplying; Dividing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/491—Indexing scheme relating to groups G06F7/491 - G06F7/4917
    • G06F2207/49195—Using pure decimal representation, e.g. 10-valued voltage signal, 1-out-of-10 code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G06F7/4833—Logarithmic number system

Definitions

  • the present invention relates to digital processing.
  • the invention particularly relates to a digital processor arranged to process data words coded in a specific genetics based way.
  • ECO effective computing power-output
  • the object is achieved by providing a digital processor comprising:
  • a first processing unit arranged to receive a first N-bit data word, and comprising:
  • a first decoder arranged to receive a first part of said first N-bit data word and to decode said first part of said first N-bit data word into a first D-bit data word, wherein N, D are positive integers, and
  • a first read out circuit arranged to read out specific bits of a second part of said first N-bit data word so as to produce a first knowledge signal
  • a second processing unit arranged to receive a second N-bit data word, and comprising:
  • a second decoder arranged to receive a first part of said second N-bit data word and to decode said first part of said second N-bit data word into a second D-bit data word
  • a second read out circuit arranged to read out specific bits of a second part of said second N-bit data word so as to produce a second knowledge signal
  • each arithmetic module being arranged to receive said first and said second D-bit data word, and arranged to perform a predefined arithmetic operation on said first and said second D-bit data word;
  • the processor according to the invention has a new architecture enabling a fast and parallel processing of data, with minimal number of logical gate operation per calculation.
  • VLIW superscalar and super pipelined processors
  • the invention is based on the insight that the density of a dye (which can be MOS/CMOS) is not the most important problem of the main developments mentioned in the preamble.
  • the limitation of the computing power i.e. the amount of logical operations per second
  • the ROC values in current processors is very low. In a processor according to the invention, the ROC value is improved dramatically, as will become apparent form the examples shown.
  • a computer comprising a digital processor as described above.
  • a method of processing digital data according to claim 8 is provided.
  • Fig. 1 shows a part of a digital processor according to an embodiment of the invention
  • Fig. 2 is a simple example of a calculation, executed by a processor according to an embodiment
  • Fig. 3 is another example of a calculation
  • Fig. 4 shows an example of the multiplication of 254 x 2
  • Fig. 5 schematically depicts the relation between the I/O Bus and the digital processor
  • Fig. 6 shows an example of a axiom for multiplying decimal values
  • Fig. 7 is a table listing of a possible coding used in an embodiment of the invention
  • an Fig. 8 is an example of a hardware implementation of a decoder comprised in an embodiment of the invention.
  • FIG 1 a part of a digital processor according to an embodiment of the invention is shown.
  • the digital processor comprises at least a first processing unit 1 and a second processing unit 2.
  • Processing units 1, 2 each comprise a decoder 3, 4 arranged to decode a first part of an input data word comprising N bits, see arrows 6, 8, into a D-bit data word depicted as 5, 7 respectively.
  • Processing units 1, 2 further comprise a read out circuit 9, 11 (also referred to as DNA decoder) for receiving a second part of an input data word.
  • the read out circuits 9, 11 convert the second part of the N-bit data words into so-called knowledge signals 13, 15 which are led to a instruction circuit 17.
  • the instruction circuit is arranged to receive an input instruction signal 19 and convert the input instruction signal 19 into an activation signal depending on said knowledge signals 13, 15.
  • the digital processor further comprises a plurality of arithmetic modules 25, 27, 29, 31 arranged to perform arithmetic operations on the D-bit data words 5, 7, received from the decoders 3, 4 of the first and second processing unit.
  • Each of the arithmetic modules 25, 27, 29, 31 may embody a different arithmetic operation, such as multiplying, adding, subtracting, comparing, etc.
  • the instruction circuit 17 is arranged to produce an activation signal 33, which is sent to the different arithmetic modules 25, 27, 29, 31.
  • the arithmetic modules 25, 27, 29, 31 will perform their specific arithmetic operation, only if they receive an activation signal from the instruction circuit 17.
  • the outcomes 35 of the specific arithmetic operations are represented in a format using the same coding as the one which is used to code the input data words, hi this way, the output of the arithmetic modules can be input for other processing units, for further processing.
  • the decoders 3, 4 are arranged to convert binary code into D-bit data word, which is coded in a format wherein only one bit is active at a time.
  • Decoders 3, 4 may for example comprise 10 output gates, each output gate representing one decimal value.
  • Each of the output gates of the decoders can be routed to a specific arithmetic module which then only needs to perform a calculation on two bits. This results in very simple architecture of the arithmetic modules 25, 27, 29, 31, which in turn is favourable for the speed of the digital processor.
  • FIG 2 a simple example of a calculation is shown.
  • a very simple multiplication of 1 x 3 (decimal) is described.
  • the value 1 is stored in a register 40, which may be part of the first processing unit 1. It should be noted that this register may well be part of an I/O bus, providing the processing units 1, 2 with data.
  • the decimal value 3 is stored in register 41. Both decimal values are binary coded.
  • the first part of a first N-bit data word 40 is input for a decoder 3, which converts the digital value into a first D-bit data word wherein only one output gate is high, in this case output gate labelled "1" is high.
  • the other output gates are low and are not of interest for this example.
  • FIG. 1 The first part of a second N-bit data word 41 is input for decoder 4, which convert it to a second D-bit data word wherein only an output gate "3" is high.
  • Output of the decoders 3, 4 is sent to a multiplier 43, which comprises an AND gate and two OR gates 46, 47.
  • Figure 2 also shows an example of an instruction circuit 17, which receives an instruction signal 19, having a value ⁇ 0>.
  • the instruction circuit 17 comprises one NAND 51, which receives the instruction signal 19 and data from a specific bit in the knowledge data part of the two N-bit data words. Both bits are indicative for whether the cell cores contain numerical values or not. Here, they both contain a ⁇ 0>, which in this case means that both values are numeric.
  • the instruction circuit 17 will sent an activation signal 53 to the multiplier 43, such as to activate the multiplier.
  • the result of this multiplication is that a digital code 00011 is produces, see output buffer 54.
  • the output buffer 54 may be an input buffer of a further processing unit, not shown.
  • the multiplier 43 may also comprise an inverter 57, which is connected to an input gate of the output buffer 54 to fill the bit concerning information on the output value being a numeric value, in this case a ⁇ 0> will stored in the appropriate position of the second part 55 of the output buffer 54. It should be noted that this filling of knowledge data into the output buffer 54 may well be performed by the instruction circuit 17.
  • Figure 3 shows a calculation of 10 2 x 10 3 (i.e. 100 x 1000 decimal).
  • the value 10 2 is stored in an ABGED code format in a register 60, which means that the cell core contains ⁇ 00010> and that a specific bit in the knowledge data (i.e. the second part of the data word) is ⁇ 1>, representing the fact that the cell core contains an exponential value.
  • the value 10 3 is stored in a register 61, see figure 3.
  • Each of the decoders 3, 4 will decode the digital cell core data into a D-bit data word, which are input for both a multiplier 63 and an adder 65.
  • the instruction circuit 17 receives knowledge information from the second parts of the input N-bit data words, via a read out circuit, which is not shown.
  • the instruction circuit 17 receives a multiplication instruction signal 19 and converts it into an activation signal 75.
  • the activation signal 75 is sent to an adder 65, but not to the multiplexer 63.
  • This is a result of the knowledge present in the second part of the input data words. This knowledge is represented by specific bits, which in turn activate adequate logical gates in the instruction circuit. This will lead to activation signals, which indirectly embody the arithmetic knowledge that multiplying two exponential values with the same base, can be performed by adding the exponent and keeping the base unchanged.
  • the adder 65 will fill an output register 77 wherein a cell core will be filled with the value ⁇ 00001> and the second part of the data word, representing the knowledge of the output data word (e.g. the outcome has base 10 (decimal)), will be filled in such a way that the exponent bit El is ⁇ 1>.
  • a decimal value with more than one decimal is represented by a plurality of cells, referred to as 'cell chain'.
  • the decimal value 254 is represented by a cell chain of three cells.
  • Each of the three decimal values is coded into a binary code and stored in a first part of a data word.
  • the N-bit data word contains at least 26 bits.
  • a second part of a cell contains bits representing additional knowledge on the value present in the cell core (i.e., the first part of the data word).
  • each cell is represented (i.e. processed) by one active processing unit, so a cell chain is represented by a number of processing units.
  • the digital processor comprises a plurality of processing units, and a plurality of arithmetic modules and at least one instruction circuit, wherein each of said plurality of processing units is arranged to decode a first part of a N-bit data word into a D-bit data word, and arranged to output said D-bit data word to at least one of said plurality of arithmetic modules, said plurality of arithmetic modules being arranged to be activated by activation signals produced by said at least one instruction circuit depending on knowledge signals produced by read out circuits comprised in said plurality of processing units.
  • decoders 85, 86, 87, 91 are connected to arithmetic modules. Decoder 85 and decoder 91 are connected to arithmetic module 93, decoder 86 and decoder 91 are connected to arithmetic module 95. Decoder 87 and decoder 91 are connected to arithmetic module 97. As was explained in figure 2, the arithmetic modules will produce an outcome, which will be sent to inputs of following processing units 100, 104, 101, 102. Figure 4 only shows part of these following processing units.
  • Arithmetic module 93 outputs its data to processing unitlOO, arithmetic module 95 outputs its value to processing unitlOl and arithmetic module 97 outputs its value to processing unitlO2.
  • the arithmetic module 95 is processing the multiplication of 5 x 2, which results in the decimal value 10. Since this decimal value cannot be represented by one processing unit (note: one processing unit can only represent one symbol, i.e. one decimal number), a further arithmetic module 94 and processing unit 104 are activated. This activation signal is realized by some kind of 'overflow' signal coming from arithmetic module 95, possibly coming via a separate instruction circuit, not shown.
  • Processing unit 104 is connected to another processing unit 107 via an adder.
  • the adder comprises two wires connected to the adequate input gates of the processing unit 107.
  • This adder also receives input from processing unit 100.
  • the adder will be activated as a result of the activation of processing unit 104 and an activation signal from an instruction circuit having knowledge about the fact that processing unit 101 did not represent (i.e. contains) the most left number of a cell-chain.
  • the result of the adding of adder i.e. the decimal value 5
  • the final results of this multiplication are three active processing units 107, 101 and 102, containing ABGED code representing the decimal value 508.
  • the second part comprises three groups, i.e., DNA-A group, DNA-B group and DNA-C group.
  • Table 1 a diagram is shown wherein the structure of a cell is explained and in particular the relation between the different DNA groups and the cell core.
  • the cell core comprising five bits representing a alphanumeric symbol.
  • the DNA-A group contains values representing the length of the bit strings of the DNA-C group and the DNA-B group. Besides this length information, the DNA-A group may also comprise a set of bits indicating the beginning or the end of a specific amount of data to be processed, or of a specific operation. A possible coding of this third helix in the DNA-A group is:
  • the cell core contains data, if equal to 1, then the cell core is operation code:
  • the DNA-B group contains information on what kind of data is contained in the cell core.
  • the DNA-C group has variable length. Since a cell can have a variable length, so more than 26 bits, more than one unit is needed to store a cell.
  • There are several registers units I call this DNA-map-registers which contains information about the length of DNA-A, DNA-B and DNA-C and its positions of each cell.
  • the mapping of data can be serial and/or parallel executed.
  • the processing circuits 25, 27, 29, 31 shown in figure 1 each perform certain arithmetic operations. It should be noted that the number of processing circuits is not limited to four, but can be much more.
  • FIG. 5 shows an example of a configuration of an I/O Bus 600 which may be used in a processor according to the invention.
  • the function of an I/O Bus manager, see 601 is to analyse the structure of the incoming data by reading the DNA-A group and saving this information. For example, a specific cell begins from bit no. 1 end it ends at bit no. 26 from right to left.
  • the size of the I/O bus 600 is relatively flexible.
  • the external I/O bus 602 has one size (this depends of the number of pins used.
  • the flexibility of the I/O bus 600 is realized by the I/O Bus manager 601, which reads and calculates the next begin position of the next cell within a cell chain. This information is stored in a position register, not shown. When all the positions are stored in the position register, a map of the cells and cell chains can be created by the I/O bus 600.
  • Figure 6 shows an example of a axiom for multiplying decimal values, which may be implemented by a processing circuit in the digital processor.
  • the axiom is implemented in a processing circuit by connecting certain input gates via logical gates to output gates of the processing circuits. This means that the table shown in figure 6 with multiplier and multiple values is hard wired in a processing circuit. It will be clear to the skilled reader how an adder, divider, comparing will be implemented.
  • a word like MOV can be coded in for example ABGED code and be processed by the processor, wherein the processor will process the cell chain containing the cells "M 5 O 5 V".
  • the processing characters are stored (represented) by the processing units as a character of a high level computer language (such as Assembler or C) 5 and they are directly interpretable by the hardware of the digital processor. Natural languages, such as English or Vietnamese can be used to execute the digital processor. A combination of one or more programming characters will be executed by one or more processing units.
  • the process letters can be organized like a sentence structure, e.g. subject, verbs, time, place and time etc.
  • the sign of the processing command "contr-p" will be stored by the DNA-A group, using the first 3 bits, this is helix 1 (followed by helix 2: the length_A and followed by helix 3: length_B).
  • Figure 7 shows a table of a possible coding used in an embodiment of the invention.
  • the table shows the digital coding of symbols varying from the numeric values to capital letters.
  • Each row of the table contains a simple cell with fixed length. The length of a cell may vary, as was described above.
  • the bits of a cell core are referred to as
  • the DNA-C group contains information on the position of a symbol represented by the cell core.
  • the bits in DNA-C group are referred to as DNA-C(a), DNA-C(d), DNA-C(c), DNA-C(b).
  • the table of figure 7 contains a DNA-B group and a DNA-A group comprising the bits DNA-B (a), DNA- B(d), DNA-B(c), DNA-B(b) and DNA-A(a), DNA- A(c), DNA-A(b).
  • C(a) the key bit, this a sign bit which supplies the DNA-C processor information on the position of the cell in a cell chain, which can be (when the cell core is a number according to DNA-B) at the front or at the back of a comma or a fraction.
  • This notation allows positions of 10 ⁇ 30 (this means we can make a number like for example: "123 (which has 10 ⁇ 30 digits), 1233 08" (which has 10 ⁇ 30 digits after the comma)
  • Core ⁇ >
  • the DNA-B group informs an arithmetic module about which position the cell has within a cell chain.
  • a cell chain may for example be 543, representing a decimal value, hi the ABGED code, this decimal value may be represented by three cells in the cell chain.
  • the position within the cell chain is encoded in the DNA-B group.
  • the first bit of this group DNA-B(a) is the key bit. If this key bit is equal to 0, then the position of this cell in a cell chain is before the decimal comma. Please note that in English notation, the decimal point is used instead of the comma. So, if in this description the term decimal comma is used, it can also be read as decimal point. If the key bit of the cell core, i.e.
  • DNA-A helix l: ⁇ 001> helix 2: ⁇ 001> helix3 ⁇ 001>; DNA-B: ⁇ 000>; DNA-C: ⁇ 00000>; Cell-core: ⁇ 01101> which means a comma,
  • DNA-A helix l: ⁇ 001> helix 2: ⁇ 001> helix3 ⁇ 001>; DNA-B: ⁇ 000>; >; DNA-C: ⁇ 10001>; Cell-core: ⁇ 00000> which means a zero.
  • the number of zeros required depends of the number of positions that the input A has. This means that if the number of positions after the comma is two, the DNA-B has to introduce a same number of zeros (i.e. two zeros).
  • additional cells i.e. activating additional processing units
  • the knowledge part of the N-bit data words also comprises a group called the DNA-B group, comprising coding for knowledge about the type of the symbol encoded in the core.
  • This DNA-B group may, for example, comprise four bits, as shown in the table of figure 7.
  • the first bit DNA-B(a) is the key bit. If this key bit is equal to 0, then the cell core contains a numeric value.
  • the DNA-B group may comprises several helixes.
  • a helix is defined as a group of genes (i.e. bits) within a DNA-group, which are related to each other and are representing a specific interpretation of the DNA part of the cell.
  • the DNA-B group only comprises one helix with four bits.
  • the cell core contains a letter, character or logical function.
  • a third DNA group comprises three helixes, see table 1.
  • information is stored on the number of helixes in the DNA-B group.
  • information is stored on the number of helixes in the DNA-C group.
  • information is stored at the start and end of an operation or of data, as was described above.
  • Using this DNA-A group creates the possibility to process encoded data words with flexible length, making it possible to represent a very large number of values and/or symbol strings.
  • the second helix of DNA-A is ⁇ 0010>, see table 1, it means that the position of the cell-core in a cell chain is represented by 2 digits, so in this case it can vary from 10 to 99.
  • a decoder comprises several logical gates receiving data form input gates and/or other logical gates.
  • the ABGED code contains "knowledge at bit level", i.e. what kind of value or symbol is stored in the cell core. By analyzing the bits in the different DNA groups, the knowledge on the data to be processed can be used. This makes it possible to perform mathematical operations on relatively short data words.
  • Those memory maps can also be negative values.
  • Addressing can be done in a sequential order, or a register address can be given a specific name that defines the specific meaning of said cell represented by said register in a verb.
  • Those verbs can be organized like the natural language grammar, so that addressing in a sequence of verbs (i.e. sentences) is possible.
  • register addresses are e.g. from 0 to 9; A to Z; a to z; 0 to -9 ; 0 to 9 at exponential scale; 0 to 9 at "+" or "-" LOG scale.
  • the addressing can be done in alphabetic vocabulary words combined with Extended Decimals. Even computer operation instructions as such can be represented by a specific sentence (i.e. chain of words) at the machine level, without the need for a translation from higher computer language to machine code, as is necessary when using for example Assembler.
  • ABGED code knowledge about an operand (e.g. is it a decimal value or an exponential value) is used before the actual calculation is performed.
  • the digital data in a core of a cell is decoded into a decimal value. With that value it is possible to process it in the decimal system.
  • different scales are used, like for example exponential or logarithmic scales, hi the processor according to the invention the basic algebra rules are implemented hardwired. Below, some examples are shown of decimal calculations which are processed by the invention using the same algebra rule as normally is done by a person.
  • the number of logical operations for one calculation is small as compared to the state of the art. This will be explained using an example, hi this example the decimal operation 32*234 is executed using a BCD code.
  • ABSED bit level with extended decimal system

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Abstract

La présente invention concerne une nouvelle architecture d'ordinateur. Un processeur numérique comprend des unités de traitement, lesquelles comprennent des décodeurs destinés à décoder une première partie du mot de données à N bits en code numérique avec uniquement un bit. Ces bits sont traités dans des modules arithmétiques qui reçoivent des sorties de deux unités de traitement et, un signal d'activation produit par un circuit d'instruction. Ce circuit d'instruction reçoit une connaissance des données à traiter par la lecture de la seconde partie du mot de données à N bits. Cette seconde partie peut-être divisée en ce qu'on appelle plusieurs groupes d'ADN. Le groupe d'ADN contient des informations sur le type des symboles/valeurs des données à traiter. On peut exécuter grâce à cette connaissance de données, un traitement parallèle très rapide est très simple. .
PCT/NL2004/000505 2004-07-12 2004-07-12 Processeur numerique et procede de traitement de donnees numeriques WO2006006842A2 (fr)

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EP04748730A EP1831782A2 (fr) 2004-07-12 2004-07-12 Processeur numerique et procede de traitement de donnees numeriques
PCT/NL2004/000505 WO2006006842A2 (fr) 2004-07-12 2004-07-12 Processeur numerique et procede de traitement de donnees numeriques
CN2004800439691A CN101091157B (zh) 2004-07-12 2004-07-12 用于处理数字数据的数字处理器和方法

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